diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info index 167cc03..4737fc9 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/OpenFPGAEngine.info @@ -1,43 +1,48 @@ -commit 48b2bff0d909e2c6d0740d2a5386123eb238349f +commit 55f7a2c187139d471143f91dc368bb1497e2eb78 +Merge: 1f3e656f 93e7107d +Author: Laboratory for Nano Integrated Systems (LNIS) <40280375+LNIS-Projects@users.noreply.github.com> +Date: Wed Nov 4 21:55:37 2020 -0700 + + Merge pull request #116 from LNIS-Projects/dev + + Extended I/O Support for SoC I/O interface + +commit 93e7107d800259ad9031c6b5d4572e8a971c6403 Author: tangxifan -Date: Sun Sep 27 20:08:11 2020 -0600 +Date: Wed Nov 4 20:59:34 2020 -0700 - [OpenFPGA Tool] Update fabric key data structure to support regions + [Test] Add new test to CI -commit bbdea4a46b7aadd8a6f0fc45abdd39d1cc6d3057 +commit bce8233019cec3b7f778befd9457c9c637b05c6c Author: tangxifan -Date: Sun Sep 27 19:23:13 2020 -0600 +Date: Wed Nov 4 20:58:58 2020 -0700 - [Regression Test] Remove out-of-update sub modules + [Arch] Bug fix in caravel arch -commit e95eacfbd9ec5e8d9aecab7572d4bad5265d9590 -Merge: 32c43ffb 94047037 +commit 6b48ee7f0bd6c86181cdbbb468c4cf8e7af5c4c6 Author: tangxifan -Date: Sun Sep 27 17:01:57 2020 -0600 +Date: Wed Nov 4 20:58:40 2020 -0700 - Merge branch 'dev' into ganesh_dev + [Test] Add new test for caravel io support -commit 94047037c570b6a432fea8f363a5147df9bc918d +commit c85edb4738a24c394b5eeefb08586da7bd4ead6a Author: tangxifan -Date: Sun Sep 27 14:33:14 2020 -0600 +Date: Wed Nov 4 20:52:47 2020 -0700 - [OpenFPGA Tool] Streamline codes in openfpga arch parser - -commit 94a1324f0527276546c3b2571b1a1b7700a473f7 -Author: tangxifan -Date: Sat Sep 26 14:31:57 2020 -0600 - - [Documentation] Remove deprecated XML syntax -On branch dev -Your branch is up to date with 'origin/dev'. + [Arch] Bug fix for embedded io arch +On branch master +Your branch is up to date with 'origin/master'. Untracked files: (use "git add ..." to include in what will be committed) openfpga/openfpga + openfpga_flow/tasks/FPGA1212_FC_HD_SKY_task + openfpga_flow/tasks/FPGA1212_HIER_SKY_SC_MS_task openfpga_flow/tasks/FPGA128128_FLAT_task openfpga_flow/tasks/FPGA1616_FLAT_task openfpga_flow/tasks/FPGA22_FLAT_task openfpga_flow/tasks/FPGA22_FRAME_task + openfpga_flow/tasks/FPGA22_HIER_SKY_SC_MS_task openfpga_flow/tasks/FPGA22_HIER_SKY_task openfpga_flow/tasks/FPGA22_HIER_task openfpga_flow/tasks/FPGA22_MB_task diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v index 49d1358..a1e1538 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/fpga_core.v @@ -1,18 +1,17 @@ module fpga_core -( - input [0:0] prog_clk, - input [0:0] Test_en, - input [0:0] clk, - input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN, - output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT, - output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR, - input [0:0] ccff_head, - output [0:0] ccff_tail, - input sc_head, - output sc_tail -); +( prog_clk, Test_en, clk, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, ccff_head, ccff_tail, sc_head, sc_tail ); + input [0:0] prog_clk; + input [0:0] Test_en; + input [0:0] clk; + input [0:17] gfpga_pad_EMBEDDED_IO_SOC_IN; + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_OUT; + output [0:17] gfpga_pad_EMBEDDED_IO_SOC_DIR; + input [0:0] ccff_head; + output [0:0] ccff_tail; + input sc_head; + output sc_tail; wire [0:0] cbx_1__0__0_bottom_grid_pin_0_; wire [0:0] cbx_1__0__0_bottom_grid_pin_10_; @@ -425,8 +424,6 @@ module fpga_core wire [0:19] sb_2__2__0_chanx_left_out; wire [0:19] sb_2__2__0_chany_bottom_out; wire [1:0] UNCONN; - wire [2:0] sc_out_wires; - wire [2:0] sc_in_wires; wire [12:0] scff_Wires; grid_clb @@ -434,7 +431,6 @@ module fpga_core ( .SC_OUT_BOT(scff_Wires[5]), .SC_IN_TOP(scff_Wires[3]), - .top_width_0_height_0__pin_33_(sc_in_wires[0]), .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), @@ -506,7 +502,6 @@ module fpga_core .right_width_0_height_0__pin_49_upper(grid_clb_0_right_width_0_height_0__pin_49_upper[0]), .right_width_0_height_0__pin_49_lower(grid_clb_0_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_0_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_0_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_0_ccff_tail[0]) ); @@ -516,7 +511,6 @@ module fpga_core ( .SC_OUT_BOT(scff_Wires[2]), .SC_IN_TOP(scff_Wires[1]), - .bottom_width_0_height_0__pin_51_(sc_out_wires[0]), .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), @@ -537,7 +531,6 @@ module fpga_core .top_width_0_height_0__pin_14_(cbx_1__2__0_bottom_grid_pin_14_[0]), .top_width_0_height_0__pin_15_(cbx_1__2__0_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(grid_clb_1__2__undriven_top_width_0_height_0__pin_32_[0]), - .top_width_0_height_0__pin_33_(grid_clb_1__2__undriven_top_width_0_height_0__pin_33_[0]), .right_width_0_height_0__pin_16_(cby_1__1__1_left_grid_pin_16_[0]), .right_width_0_height_0__pin_17_(cby_1__1__1_left_grid_pin_17_[0]), .right_width_0_height_0__pin_18_(cby_1__1__1_left_grid_pin_18_[0]), @@ -598,7 +591,6 @@ module fpga_core ( .SC_OUT_TOP(scff_Wires[9]), .SC_IN_BOT(scff_Wires[8]), - .top_width_0_height_0__pin_33_(sc_in_wires[1]), .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), @@ -670,7 +662,6 @@ module fpga_core .right_width_0_height_0__pin_49_upper(grid_clb_2_right_width_0_height_0__pin_49_upper[0]), .right_width_0_height_0__pin_49_lower(grid_clb_2_right_width_0_height_0__pin_49_lower[0]), .bottom_width_0_height_0__pin_50_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_[0]), - .bottom_width_0_height_0__pin_51_(grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_[0]), .ccff_tail(grid_clb_2_ccff_tail[0]) ); @@ -680,7 +671,6 @@ module fpga_core ( .SC_OUT_TOP(scff_Wires[11]), .SC_IN_BOT(scff_Wires[10]), - .bottom_width_0_height_0__pin_51_(sc_out_wires[1]), .prog_clk(prog_clk[0]), .Test_en(Test_en[0]), .clk(clk[0]), @@ -701,7 +691,6 @@ module fpga_core .top_width_0_height_0__pin_14_(cbx_1__2__1_bottom_grid_pin_14_[0]), .top_width_0_height_0__pin_15_(cbx_1__2__1_bottom_grid_pin_15_[0]), .top_width_0_height_0__pin_32_(direct_interc_2_out[0]), - .top_width_0_height_0__pin_33_(direct_interc_5_out[0]), .right_width_0_height_0__pin_16_(cby_2__1__1_left_grid_pin_16_[0]), .right_width_0_height_0__pin_17_(cby_2__1__1_left_grid_pin_17_[0]), .right_width_0_height_0__pin_18_(cby_2__1__1_left_grid_pin_18_[0]), @@ -1145,8 +1134,6 @@ module fpga_core ( .SC_OUT_BOT(scff_Wires[3]), .SC_IN_TOP(scff_Wires[2]), - .CLB_SC_OUT(sc_in_wires[0]), - .CLB_SC_IN(sc_out_wires[0]), .prog_clk(prog_clk[0]), .chanx_left_in(sb_0__1__0_chanx_right_out[0:19]), .chanx_right_in(sb_1__1__0_chanx_left_out[0:19]), @@ -1178,8 +1165,6 @@ module fpga_core ( .SC_OUT_TOP(scff_Wires[10]), .SC_IN_BOT(scff_Wires[9]), - .CLB_SC_OUT(sc_in_wires[1]), - .CLB_SC_IN(sc_out_wires[1]), .prog_clk(prog_clk[0]), .chanx_left_in(sb_1__1__0_chanx_right_out[0:19]), .chanx_right_in(sb_2__1__0_chanx_left_out[0:19]), diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v index 03671f6..47bb2d6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_clb.v @@ -1,86 +1,85 @@ module grid_clb -( - input [0:0] prog_clk, - input [0:0] Test_en, - input [0:0] clk, - input [0:0] top_width_0_height_0__pin_0_, - input [0:0] top_width_0_height_0__pin_1_, - input [0:0] top_width_0_height_0__pin_2_, - input [0:0] top_width_0_height_0__pin_3_, - input [0:0] top_width_0_height_0__pin_4_, - input [0:0] top_width_0_height_0__pin_5_, - input [0:0] top_width_0_height_0__pin_6_, - input [0:0] top_width_0_height_0__pin_7_, - input [0:0] top_width_0_height_0__pin_8_, - input [0:0] top_width_0_height_0__pin_9_, - input [0:0] top_width_0_height_0__pin_10_, - input [0:0] top_width_0_height_0__pin_11_, - input [0:0] top_width_0_height_0__pin_12_, - input [0:0] top_width_0_height_0__pin_13_, - input [0:0] top_width_0_height_0__pin_14_, - input [0:0] top_width_0_height_0__pin_15_, - input [0:0] top_width_0_height_0__pin_32_, - input [0:0] top_width_0_height_0__pin_33_, - input [0:0] right_width_0_height_0__pin_16_, - input [0:0] right_width_0_height_0__pin_17_, - input [0:0] right_width_0_height_0__pin_18_, - input [0:0] right_width_0_height_0__pin_19_, - input [0:0] right_width_0_height_0__pin_20_, - input [0:0] right_width_0_height_0__pin_21_, - input [0:0] right_width_0_height_0__pin_22_, - input [0:0] right_width_0_height_0__pin_23_, - input [0:0] right_width_0_height_0__pin_24_, - input [0:0] right_width_0_height_0__pin_25_, - input [0:0] right_width_0_height_0__pin_26_, - input [0:0] right_width_0_height_0__pin_27_, - input [0:0] right_width_0_height_0__pin_28_, - input [0:0] right_width_0_height_0__pin_29_, - input [0:0] right_width_0_height_0__pin_30_, - input [0:0] right_width_0_height_0__pin_31_, - input [0:0] left_width_0_height_0__pin_52_, - input [0:0] ccff_head, - output [0:0] top_width_0_height_0__pin_34_upper, - output [0:0] top_width_0_height_0__pin_34_lower, - output [0:0] top_width_0_height_0__pin_35_upper, - output [0:0] top_width_0_height_0__pin_35_lower, - output [0:0] top_width_0_height_0__pin_36_upper, - output [0:0] top_width_0_height_0__pin_36_lower, - output [0:0] top_width_0_height_0__pin_37_upper, - output [0:0] top_width_0_height_0__pin_37_lower, - output [0:0] top_width_0_height_0__pin_38_upper, - output [0:0] top_width_0_height_0__pin_38_lower, - output [0:0] top_width_0_height_0__pin_39_upper, - output [0:0] top_width_0_height_0__pin_39_lower, - output [0:0] top_width_0_height_0__pin_40_upper, - output [0:0] top_width_0_height_0__pin_40_lower, - output [0:0] top_width_0_height_0__pin_41_upper, - output [0:0] top_width_0_height_0__pin_41_lower, - output [0:0] right_width_0_height_0__pin_42_upper, - output [0:0] right_width_0_height_0__pin_42_lower, - output [0:0] right_width_0_height_0__pin_43_upper, - output [0:0] right_width_0_height_0__pin_43_lower, - output [0:0] right_width_0_height_0__pin_44_upper, - output [0:0] right_width_0_height_0__pin_44_lower, - output [0:0] right_width_0_height_0__pin_45_upper, - output [0:0] right_width_0_height_0__pin_45_lower, - output [0:0] right_width_0_height_0__pin_46_upper, - output [0:0] right_width_0_height_0__pin_46_lower, - output [0:0] right_width_0_height_0__pin_47_upper, - output [0:0] right_width_0_height_0__pin_47_lower, - output [0:0] right_width_0_height_0__pin_48_upper, - output [0:0] right_width_0_height_0__pin_48_lower, - output [0:0] right_width_0_height_0__pin_49_upper, - output [0:0] right_width_0_height_0__pin_49_lower, - output [0:0] bottom_width_0_height_0__pin_50_, - output [0:0] bottom_width_0_height_0__pin_51_, - output [0:0] ccff_tail, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, Test_en, clk, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_1_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_3_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_5_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_7_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_9_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_11_, top_width_0_height_0__pin_12_, top_width_0_height_0__pin_13_, top_width_0_height_0__pin_14_, top_width_0_height_0__pin_15_, top_width_0_height_0__pin_32_, top_width_0_height_0__pin_33_, right_width_0_height_0__pin_16_, right_width_0_height_0__pin_17_, right_width_0_height_0__pin_18_, right_width_0_height_0__pin_19_, right_width_0_height_0__pin_20_, right_width_0_height_0__pin_21_, right_width_0_height_0__pin_22_, right_width_0_height_0__pin_23_, right_width_0_height_0__pin_24_, right_width_0_height_0__pin_25_, right_width_0_height_0__pin_26_, right_width_0_height_0__pin_27_, right_width_0_height_0__pin_28_, right_width_0_height_0__pin_29_, right_width_0_height_0__pin_30_, right_width_0_height_0__pin_31_, left_width_0_height_0__pin_52_, ccff_head, top_width_0_height_0__pin_34_upper, top_width_0_height_0__pin_34_lower, top_width_0_height_0__pin_35_upper, top_width_0_height_0__pin_35_lower, top_width_0_height_0__pin_36_upper, top_width_0_height_0__pin_36_lower, top_width_0_height_0__pin_37_upper, top_width_0_height_0__pin_37_lower, top_width_0_height_0__pin_38_upper, top_width_0_height_0__pin_38_lower, top_width_0_height_0__pin_39_upper, top_width_0_height_0__pin_39_lower, top_width_0_height_0__pin_40_upper, top_width_0_height_0__pin_40_lower, top_width_0_height_0__pin_41_upper, top_width_0_height_0__pin_41_lower, right_width_0_height_0__pin_42_upper, right_width_0_height_0__pin_42_lower, right_width_0_height_0__pin_43_upper, right_width_0_height_0__pin_43_lower, right_width_0_height_0__pin_44_upper, right_width_0_height_0__pin_44_lower, right_width_0_height_0__pin_45_upper, right_width_0_height_0__pin_45_lower, right_width_0_height_0__pin_46_upper, right_width_0_height_0__pin_46_lower, right_width_0_height_0__pin_47_upper, right_width_0_height_0__pin_47_lower, right_width_0_height_0__pin_48_upper, right_width_0_height_0__pin_48_lower, right_width_0_height_0__pin_49_upper, right_width_0_height_0__pin_49_lower, bottom_width_0_height_0__pin_50_, bottom_width_0_height_0__pin_51_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:0] Test_en; + input [0:0] clk; + input [0:0] top_width_0_height_0__pin_0_; + input [0:0] top_width_0_height_0__pin_1_; + input [0:0] top_width_0_height_0__pin_2_; + input [0:0] top_width_0_height_0__pin_3_; + input [0:0] top_width_0_height_0__pin_4_; + input [0:0] top_width_0_height_0__pin_5_; + input [0:0] top_width_0_height_0__pin_6_; + input [0:0] top_width_0_height_0__pin_7_; + input [0:0] top_width_0_height_0__pin_8_; + input [0:0] top_width_0_height_0__pin_9_; + input [0:0] top_width_0_height_0__pin_10_; + input [0:0] top_width_0_height_0__pin_11_; + input [0:0] top_width_0_height_0__pin_12_; + input [0:0] top_width_0_height_0__pin_13_; + input [0:0] top_width_0_height_0__pin_14_; + input [0:0] top_width_0_height_0__pin_15_; + input [0:0] top_width_0_height_0__pin_32_; + input [0:0] top_width_0_height_0__pin_33_; + input [0:0] right_width_0_height_0__pin_16_; + input [0:0] right_width_0_height_0__pin_17_; + input [0:0] right_width_0_height_0__pin_18_; + input [0:0] right_width_0_height_0__pin_19_; + input [0:0] right_width_0_height_0__pin_20_; + input [0:0] right_width_0_height_0__pin_21_; + input [0:0] right_width_0_height_0__pin_22_; + input [0:0] right_width_0_height_0__pin_23_; + input [0:0] right_width_0_height_0__pin_24_; + input [0:0] right_width_0_height_0__pin_25_; + input [0:0] right_width_0_height_0__pin_26_; + input [0:0] right_width_0_height_0__pin_27_; + input [0:0] right_width_0_height_0__pin_28_; + input [0:0] right_width_0_height_0__pin_29_; + input [0:0] right_width_0_height_0__pin_30_; + input [0:0] right_width_0_height_0__pin_31_; + input [0:0] left_width_0_height_0__pin_52_; + input [0:0] ccff_head; + output [0:0] top_width_0_height_0__pin_34_upper; + output [0:0] top_width_0_height_0__pin_34_lower; + output [0:0] top_width_0_height_0__pin_35_upper; + output [0:0] top_width_0_height_0__pin_35_lower; + output [0:0] top_width_0_height_0__pin_36_upper; + output [0:0] top_width_0_height_0__pin_36_lower; + output [0:0] top_width_0_height_0__pin_37_upper; + output [0:0] top_width_0_height_0__pin_37_lower; + output [0:0] top_width_0_height_0__pin_38_upper; + output [0:0] top_width_0_height_0__pin_38_lower; + output [0:0] top_width_0_height_0__pin_39_upper; + output [0:0] top_width_0_height_0__pin_39_lower; + output [0:0] top_width_0_height_0__pin_40_upper; + output [0:0] top_width_0_height_0__pin_40_lower; + output [0:0] top_width_0_height_0__pin_41_upper; + output [0:0] top_width_0_height_0__pin_41_lower; + output [0:0] right_width_0_height_0__pin_42_upper; + output [0:0] right_width_0_height_0__pin_42_lower; + output [0:0] right_width_0_height_0__pin_43_upper; + output [0:0] right_width_0_height_0__pin_43_lower; + output [0:0] right_width_0_height_0__pin_44_upper; + output [0:0] right_width_0_height_0__pin_44_lower; + output [0:0] right_width_0_height_0__pin_45_upper; + output [0:0] right_width_0_height_0__pin_45_lower; + output [0:0] right_width_0_height_0__pin_46_upper; + output [0:0] right_width_0_height_0__pin_46_lower; + output [0:0] right_width_0_height_0__pin_47_upper; + output [0:0] right_width_0_height_0__pin_47_lower; + output [0:0] right_width_0_height_0__pin_48_upper; + output [0:0] right_width_0_height_0__pin_48_lower; + output [0:0] right_width_0_height_0__pin_49_upper; + output [0:0] right_width_0_height_0__pin_49_lower; + output [0:0] bottom_width_0_height_0__pin_50_; + output [0:0] bottom_width_0_height_0__pin_51_; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; assign top_width_0_height_0__pin_34_lower[0] = top_width_0_height_0__pin_34_upper[0]; assign top_width_0_height_0__pin_35_lower[0] = top_width_0_height_0__pin_35_upper[0]; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v deleted file mode 100644 index 2c819d1..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_bottom.v +++ /dev/null @@ -1,176 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_io_bottom(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - top_width_0_height_0__pin_0_, - top_width_0_height_0__pin_2_, - top_width_0_height_0__pin_4_, - top_width_0_height_0__pin_6_, - top_width_0_height_0__pin_8_, - top_width_0_height_0__pin_10_, - ccff_head, - top_width_0_height_0__pin_1_upper, - top_width_0_height_0__pin_1_lower, - top_width_0_height_0__pin_3_upper, - top_width_0_height_0__pin_3_lower, - top_width_0_height_0__pin_5_upper, - top_width_0_height_0__pin_5_lower, - top_width_0_height_0__pin_7_upper, - top_width_0_height_0__pin_7_lower, - top_width_0_height_0__pin_9_upper, - top_width_0_height_0__pin_9_lower, - top_width_0_height_0__pin_11_upper, - top_width_0_height_0__pin_11_lower, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] top_width_0_height_0__pin_0_; -// -input [0:0] top_width_0_height_0__pin_2_; -// -input [0:0] top_width_0_height_0__pin_4_; -// -input [0:0] top_width_0_height_0__pin_6_; -// -input [0:0] top_width_0_height_0__pin_8_; -// -input [0:0] top_width_0_height_0__pin_10_; -// -input [0:0] ccff_head; -// -output [0:0] top_width_0_height_0__pin_1_upper; -// -output [0:0] top_width_0_height_0__pin_1_lower; -// -output [0:0] top_width_0_height_0__pin_3_upper; -// -output [0:0] top_width_0_height_0__pin_3_lower; -// -output [0:0] top_width_0_height_0__pin_5_upper; -// -output [0:0] top_width_0_height_0__pin_5_lower; -// -output [0:0] top_width_0_height_0__pin_7_upper; -// -output [0:0] top_width_0_height_0__pin_7_lower; -// -output [0:0] top_width_0_height_0__pin_9_upper; -// -output [0:0] top_width_0_height_0__pin_9_lower; -// -output [0:0] top_width_0_height_0__pin_11_upper; -// -output [0:0] top_width_0_height_0__pin_11_lower; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - -wire [0:0] logical_tile_io_mode_io__0_ccff_tail; -wire [0:0] logical_tile_io_mode_io__1_ccff_tail; -wire [0:0] logical_tile_io_mode_io__2_ccff_tail; -wire [0:0] logical_tile_io_mode_io__3_ccff_tail; -wire [0:0] logical_tile_io_mode_io__4_ccff_tail; - -// -// -// - assign top_width_0_height_0__pin_1_lower[0] = top_width_0_height_0__pin_1_upper[0]; - assign top_width_0_height_0__pin_3_lower[0] = top_width_0_height_0__pin_3_upper[0]; - assign top_width_0_height_0__pin_5_lower[0] = top_width_0_height_0__pin_5_upper[0]; - assign top_width_0_height_0__pin_7_lower[0] = top_width_0_height_0__pin_7_upper[0]; - assign top_width_0_height_0__pin_9_lower[0] = top_width_0_height_0__pin_9_upper[0]; - assign top_width_0_height_0__pin_11_lower[0] = top_width_0_height_0__pin_11_upper[0]; -// - - logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(top_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_head[0]), - .io_inpad(top_width_0_height_0__pin_1_upper[0]), - .ccff_tail(logical_tile_io_mode_io__0_ccff_tail[0])); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__1 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[1]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[1]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[1]), - .io_outpad(top_width_0_height_0__pin_2_[0]), - .ccff_head(logical_tile_io_mode_io__0_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_3_upper[0]), - .ccff_tail(logical_tile_io_mode_io__1_ccff_tail[0])); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__2 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[2]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[2]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[2]), - .io_outpad(top_width_0_height_0__pin_4_[0]), - .ccff_head(logical_tile_io_mode_io__1_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_5_upper[0]), - .ccff_tail(logical_tile_io_mode_io__2_ccff_tail[0])); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__3 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[3]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[3]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[3]), - .io_outpad(top_width_0_height_0__pin_6_[0]), - .ccff_head(logical_tile_io_mode_io__2_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_7_upper[0]), - .ccff_tail(logical_tile_io_mode_io__3_ccff_tail[0])); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__4 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[4]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[4]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[4]), - .io_outpad(top_width_0_height_0__pin_8_[0]), - .ccff_head(logical_tile_io_mode_io__3_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_9_upper[0]), - .ccff_tail(logical_tile_io_mode_io__4_ccff_tail[0])); - - logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[5]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[5]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[5]), - .io_outpad(top_width_0_height_0__pin_10_[0]), - .ccff_head(logical_tile_io_mode_io__4_ccff_tail[0]), - .io_inpad(top_width_0_height_0__pin_11_upper[0]), - .ccff_tail(ccff_tail[0])); - -endmodule -// - - -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v deleted file mode 100644 index 53ad4f9..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_left.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_io_left(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - right_width_0_height_0__pin_0_, - ccff_head, - right_width_0_height_0__pin_1_upper, - right_width_0_height_0__pin_1_lower, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] right_width_0_height_0__pin_0_; -// -input [0:0] ccff_head; -// -output [0:0] right_width_0_height_0__pin_1_upper; -// -output [0:0] right_width_0_height_0__pin_1_lower; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - - -// -// -// - assign right_width_0_height_0__pin_1_lower[0] = right_width_0_height_0__pin_1_upper[0]; -// - - logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(right_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_head[0]), - .io_inpad(right_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0])); - -endmodule -// - - -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v deleted file mode 100644 index 5c65f69..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_right.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_io_right(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - left_width_0_height_0__pin_0_, - ccff_head, - left_width_0_height_0__pin_1_upper, - left_width_0_height_0__pin_1_lower, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] left_width_0_height_0__pin_0_; -// -input [0:0] ccff_head; -// -output [0:0] left_width_0_height_0__pin_1_upper; -// -output [0:0] left_width_0_height_0__pin_1_lower; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - - -// -// -// - assign left_width_0_height_0__pin_1_lower[0] = left_width_0_height_0__pin_1_upper[0]; -// - - logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(left_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_head[0]), - .io_inpad(left_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0])); - -endmodule -// - - -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v deleted file mode 100644 index 15931d1..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/lb/grid_io_top.v +++ /dev/null @@ -1,71 +0,0 @@ -// -// -// -// -// -// -// -// -`timescale 1ns / 1ps - -// -// -module grid_io_top(prog_clk, - gfpga_pad_EMBEDDED_IO_SOC_IN, - gfpga_pad_EMBEDDED_IO_SOC_OUT, - gfpga_pad_EMBEDDED_IO_SOC_DIR, - bottom_width_0_height_0__pin_0_, - ccff_head, - bottom_width_0_height_0__pin_1_upper, - bottom_width_0_height_0__pin_1_lower, - ccff_tail); -// -input [0:0] prog_clk; -// -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; -// -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; -// -input [0:0] bottom_width_0_height_0__pin_0_; -// -input [0:0] ccff_head; -// -output [0:0] bottom_width_0_height_0__pin_1_upper; -// -output [0:0] bottom_width_0_height_0__pin_1_lower; -// -output [0:0] ccff_tail; - -// -// - - -// -// - - - -// -// -// - assign bottom_width_0_height_0__pin_1_lower[0] = bottom_width_0_height_0__pin_1_upper[0]; -// - - logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( - .prog_clk(prog_clk[0]), - .gfpga_pad_EMBEDDED_IO_SOC_IN(gfpga_pad_EMBEDDED_IO_SOC_IN[0]), - .gfpga_pad_EMBEDDED_IO_SOC_OUT(gfpga_pad_EMBEDDED_IO_SOC_OUT[0]), - .gfpga_pad_EMBEDDED_IO_SOC_DIR(gfpga_pad_EMBEDDED_IO_SOC_DIR[0]), - .io_outpad(bottom_width_0_height_0__pin_0_[0]), - .ccff_head(ccff_head[0]), - .io_inpad(bottom_width_0_height_0__pin_1_upper[0]), - .ccff_tail(ccff_tail[0])); - -endmodule -// - - -// - diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v index 7e6adb0..05101ad 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__0_.v @@ -1,46 +1,45 @@ module cbx_1__0_ -( - input [0:0] prog_clk, - input [0:19] chanx_left_in, - input [0:19] chanx_right_in, - input [0:0] ccff_head, - output [0:19] chanx_left_out, - output [0:19] chanx_right_out, - output [0:0] bottom_grid_pin_0_, - output [0:0] bottom_grid_pin_2_, - output [0:0] bottom_grid_pin_4_, - output [0:0] bottom_grid_pin_6_, - output [0:0] bottom_grid_pin_8_, - output [0:0] bottom_grid_pin_10_, - output [0:0] ccff_tail, - input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN, - output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT, - output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR, - input [0:0] top_width_0_height_0__pin_0_, - input [0:0] top_width_0_height_0__pin_2_, - input [0:0] top_width_0_height_0__pin_4_, - input [0:0] top_width_0_height_0__pin_6_, - input [0:0] top_width_0_height_0__pin_8_, - input [0:0] top_width_0_height_0__pin_10_, - output [0:0] top_width_0_height_0__pin_1_upper, - output [0:0] top_width_0_height_0__pin_1_lower, - output [0:0] top_width_0_height_0__pin_3_upper, - output [0:0] top_width_0_height_0__pin_3_lower, - output [0:0] top_width_0_height_0__pin_5_upper, - output [0:0] top_width_0_height_0__pin_5_lower, - output [0:0] top_width_0_height_0__pin_7_upper, - output [0:0] top_width_0_height_0__pin_7_lower, - output [0:0] top_width_0_height_0__pin_9_upper, - output [0:0] top_width_0_height_0__pin_9_lower, - output [0:0] top_width_0_height_0__pin_11_upper, - output [0:0] top_width_0_height_0__pin_11_lower, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_2_, bottom_grid_pin_4_, bottom_grid_pin_6_, bottom_grid_pin_8_, bottom_grid_pin_10_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, top_width_0_height_0__pin_0_, top_width_0_height_0__pin_2_, top_width_0_height_0__pin_4_, top_width_0_height_0__pin_6_, top_width_0_height_0__pin_8_, top_width_0_height_0__pin_10_, top_width_0_height_0__pin_1_upper, top_width_0_height_0__pin_1_lower, top_width_0_height_0__pin_3_upper, top_width_0_height_0__pin_3_lower, top_width_0_height_0__pin_5_upper, top_width_0_height_0__pin_5_lower, top_width_0_height_0__pin_7_upper, top_width_0_height_0__pin_7_lower, top_width_0_height_0__pin_9_upper, top_width_0_height_0__pin_9_lower, top_width_0_height_0__pin_11_upper, top_width_0_height_0__pin_11_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chanx_left_in; + input [0:19] chanx_right_in; + input [0:0] ccff_head; + output [0:19] chanx_left_out; + output [0:19] chanx_right_out; + output [0:0] bottom_grid_pin_0_; + output [0:0] bottom_grid_pin_2_; + output [0:0] bottom_grid_pin_4_; + output [0:0] bottom_grid_pin_6_; + output [0:0] bottom_grid_pin_8_; + output [0:0] bottom_grid_pin_10_; + output [0:0] ccff_tail; + input [0:5] gfpga_pad_EMBEDDED_IO_SOC_IN; + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_OUT; + output [0:5] gfpga_pad_EMBEDDED_IO_SOC_DIR; + input [0:0] top_width_0_height_0__pin_0_; + input [0:0] top_width_0_height_0__pin_2_; + input [0:0] top_width_0_height_0__pin_4_; + input [0:0] top_width_0_height_0__pin_6_; + input [0:0] top_width_0_height_0__pin_8_; + input [0:0] top_width_0_height_0__pin_10_; + output [0:0] top_width_0_height_0__pin_1_upper; + output [0:0] top_width_0_height_0__pin_1_lower; + output [0:0] top_width_0_height_0__pin_3_upper; + output [0:0] top_width_0_height_0__pin_3_lower; + output [0:0] top_width_0_height_0__pin_5_upper; + output [0:0] top_width_0_height_0__pin_5_lower; + output [0:0] top_width_0_height_0__pin_7_upper; + output [0:0] top_width_0_height_0__pin_7_lower; + output [0:0] top_width_0_height_0__pin_9_upper; + output [0:0] top_width_0_height_0__pin_9_lower; + output [0:0] top_width_0_height_0__pin_11_upper; + output [0:0] top_width_0_height_0__pin_11_lower; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; @@ -179,7 +178,7 @@ module cbx_1__0_ ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) ); @@ -190,7 +189,7 @@ module cbx_1__0_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) ); @@ -201,7 +200,7 @@ module cbx_1__0_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) ); @@ -212,7 +211,7 @@ module cbx_1__0_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) ); @@ -223,7 +222,7 @@ module cbx_1__0_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v index 2c3eebd..59817c2 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__1_.v @@ -1,37 +1,34 @@ module cbx_1__1_ -( - input [0:0] prog_clk, - input [0:19] chanx_left_in, - input [0:19] chanx_right_in, - input [0:0] ccff_head, - output [0:19] chanx_left_out, - output [0:19] chanx_right_out, - output [0:0] bottom_grid_pin_0_, - output [0:0] bottom_grid_pin_1_, - output [0:0] bottom_grid_pin_2_, - output [0:0] bottom_grid_pin_3_, - output [0:0] bottom_grid_pin_4_, - output [0:0] bottom_grid_pin_5_, - output [0:0] bottom_grid_pin_6_, - output [0:0] bottom_grid_pin_7_, - output [0:0] bottom_grid_pin_8_, - output [0:0] bottom_grid_pin_9_, - output [0:0] bottom_grid_pin_10_, - output [0:0] bottom_grid_pin_11_, - output [0:0] bottom_grid_pin_12_, - output [0:0] bottom_grid_pin_13_, - output [0:0] bottom_grid_pin_14_, - output [0:0] bottom_grid_pin_15_, - output [0:0] ccff_tail, - input CLB_SC_IN, - output CLB_SC_OUT, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chanx_left_in; + input [0:19] chanx_right_in; + input [0:0] ccff_head; + output [0:19] chanx_left_out; + output [0:19] chanx_right_out; + output [0:0] bottom_grid_pin_0_; + output [0:0] bottom_grid_pin_1_; + output [0:0] bottom_grid_pin_2_; + output [0:0] bottom_grid_pin_3_; + output [0:0] bottom_grid_pin_4_; + output [0:0] bottom_grid_pin_5_; + output [0:0] bottom_grid_pin_6_; + output [0:0] bottom_grid_pin_7_; + output [0:0] bottom_grid_pin_8_; + output [0:0] bottom_grid_pin_9_; + output [0:0] bottom_grid_pin_10_; + output [0:0] bottom_grid_pin_11_; + output [0:0] bottom_grid_pin_12_; + output [0:0] bottom_grid_pin_13_; + output [0:0] bottom_grid_pin_14_; + output [0:0] bottom_grid_pin_15_; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; @@ -120,7 +117,6 @@ module cbx_1__1_ assign chanx_left_out[17] = chanx_right_in[17]; assign chanx_left_out[18] = chanx_right_in[18]; assign chanx_left_out[19] = chanx_right_in[19]; - assign CLB_SC_OUT = CLB_SC_IN; assign SC_IN_TOP = SC_IN_BOT; assign SC_OUT_TOP = SC_OUT_BOT; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v index 4b0b6f0..569a3a3 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cbx_1__2_.v @@ -1,42 +1,41 @@ module cbx_1__2_ -( - input [0:0] prog_clk, - input [0:19] chanx_left_in, - input [0:19] chanx_right_in, - input [0:0] ccff_head, - output [0:19] chanx_left_out, - output [0:19] chanx_right_out, - output [0:0] top_grid_pin_0_, - output [0:0] bottom_grid_pin_0_, - output [0:0] bottom_grid_pin_1_, - output [0:0] bottom_grid_pin_2_, - output [0:0] bottom_grid_pin_3_, - output [0:0] bottom_grid_pin_4_, - output [0:0] bottom_grid_pin_5_, - output [0:0] bottom_grid_pin_6_, - output [0:0] bottom_grid_pin_7_, - output [0:0] bottom_grid_pin_8_, - output [0:0] bottom_grid_pin_9_, - output [0:0] bottom_grid_pin_10_, - output [0:0] bottom_grid_pin_11_, - output [0:0] bottom_grid_pin_12_, - output [0:0] bottom_grid_pin_13_, - output [0:0] bottom_grid_pin_14_, - output [0:0] bottom_grid_pin_15_, - output [0:0] ccff_tail, - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, - input [0:0] bottom_width_0_height_0__pin_0_, - output [0:0] bottom_width_0_height_0__pin_1_upper, - output [0:0] bottom_width_0_height_0__pin_1_lower, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chanx_left_in, chanx_right_in, ccff_head, chanx_left_out, chanx_right_out, top_grid_pin_0_, bottom_grid_pin_0_, bottom_grid_pin_1_, bottom_grid_pin_2_, bottom_grid_pin_3_, bottom_grid_pin_4_, bottom_grid_pin_5_, bottom_grid_pin_6_, bottom_grid_pin_7_, bottom_grid_pin_8_, bottom_grid_pin_9_, bottom_grid_pin_10_, bottom_grid_pin_11_, bottom_grid_pin_12_, bottom_grid_pin_13_, bottom_grid_pin_14_, bottom_grid_pin_15_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, bottom_width_0_height_0__pin_0_, bottom_width_0_height_0__pin_1_upper, bottom_width_0_height_0__pin_1_lower, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chanx_left_in; + input [0:19] chanx_right_in; + input [0:0] ccff_head; + output [0:19] chanx_left_out; + output [0:19] chanx_right_out; + output [0:0] top_grid_pin_0_; + output [0:0] bottom_grid_pin_0_; + output [0:0] bottom_grid_pin_1_; + output [0:0] bottom_grid_pin_2_; + output [0:0] bottom_grid_pin_3_; + output [0:0] bottom_grid_pin_4_; + output [0:0] bottom_grid_pin_5_; + output [0:0] bottom_grid_pin_6_; + output [0:0] bottom_grid_pin_7_; + output [0:0] bottom_grid_pin_8_; + output [0:0] bottom_grid_pin_9_; + output [0:0] bottom_grid_pin_10_; + output [0:0] bottom_grid_pin_11_; + output [0:0] bottom_grid_pin_12_; + output [0:0] bottom_grid_pin_13_; + output [0:0] bottom_grid_pin_14_; + output [0:0] bottom_grid_pin_15_; + output [0:0] ccff_tail; + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; + input [0:0] bottom_width_0_height_0__pin_0_; + output [0:0] bottom_width_0_height_0__pin_1_upper; + output [0:0] bottom_width_0_height_0__pin_1_lower; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; @@ -228,7 +227,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) ); @@ -239,7 +238,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) ); @@ -250,7 +249,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) ); @@ -261,7 +260,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) ); @@ -272,7 +271,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) ); @@ -283,7 +282,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) ); @@ -294,7 +293,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) ); @@ -305,7 +304,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) ); @@ -407,7 +406,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) ); @@ -418,7 +417,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) ); @@ -429,7 +428,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) ); @@ -440,7 +439,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) ); @@ -451,7 +450,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) ); @@ -462,7 +461,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) ); @@ -473,7 +472,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) ); @@ -484,7 +483,7 @@ module cbx_1__2_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v index a7f5a19..0b8a313 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_0__1_.v @@ -1,22 +1,21 @@ module cby_0__1_ -( - input [0:0] prog_clk, - input [0:19] chany_bottom_in, - input [0:19] chany_top_in, - input [0:0] ccff_head, - output [0:19] chany_bottom_out, - output [0:19] chany_top_out, - output [0:0] left_grid_pin_0_, - output [0:0] ccff_tail, - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, - input [0:0] right_width_0_height_0__pin_0_, - output [0:0] right_width_0_height_0__pin_1_upper, - output [0:0] right_width_0_height_0__pin_1_lower -); +( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_0_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, right_width_0_height_0__pin_0_, right_width_0_height_0__pin_1_upper, right_width_0_height_0__pin_1_lower ); + input [0:0] prog_clk; + input [0:19] chany_bottom_in; + input [0:19] chany_top_in; + input [0:0] ccff_head; + output [0:19] chany_bottom_out; + output [0:19] chany_top_out; + output [0:0] left_grid_pin_0_; + output [0:0] ccff_tail; + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; + input [0:0] right_width_0_height_0__pin_0_; + output [0:0] right_width_0_height_0__pin_1_upper; + output [0:0] right_width_0_height_0__pin_1_lower; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v index 0c41972..a9e4085 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_1__1_.v @@ -1,31 +1,30 @@ module cby_1__1_ -( - input [0:0] prog_clk, - input [0:19] chany_bottom_in, - input [0:19] chany_top_in, - input [0:0] ccff_head, - output [0:19] chany_bottom_out, - output [0:19] chany_top_out, - output [0:0] left_grid_pin_16_, - output [0:0] left_grid_pin_17_, - output [0:0] left_grid_pin_18_, - output [0:0] left_grid_pin_19_, - output [0:0] left_grid_pin_20_, - output [0:0] left_grid_pin_21_, - output [0:0] left_grid_pin_22_, - output [0:0] left_grid_pin_23_, - output [0:0] left_grid_pin_24_, - output [0:0] left_grid_pin_25_, - output [0:0] left_grid_pin_26_, - output [0:0] left_grid_pin_27_, - output [0:0] left_grid_pin_28_, - output [0:0] left_grid_pin_29_, - output [0:0] left_grid_pin_30_, - output [0:0] left_grid_pin_31_, - output [0:0] ccff_tail -); +( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_bottom_in; + input [0:19] chany_top_in; + input [0:0] ccff_head; + output [0:19] chany_bottom_out; + output [0:19] chany_top_out; + output [0:0] left_grid_pin_16_; + output [0:0] left_grid_pin_17_; + output [0:0] left_grid_pin_18_; + output [0:0] left_grid_pin_19_; + output [0:0] left_grid_pin_20_; + output [0:0] left_grid_pin_21_; + output [0:0] left_grid_pin_22_; + output [0:0] left_grid_pin_23_; + output [0:0] left_grid_pin_24_; + output [0:0] left_grid_pin_25_; + output [0:0] left_grid_pin_26_; + output [0:0] left_grid_pin_27_; + output [0:0] left_grid_pin_28_; + output [0:0] left_grid_pin_29_; + output [0:0] left_grid_pin_30_; + output [0:0] left_grid_pin_31_; + output [0:0] ccff_tail; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v index b4f8f45..5dcc50c 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/cby_2__1_.v @@ -1,38 +1,37 @@ module cby_2__1_ -( - input [0:0] prog_clk, - input [0:19] chany_bottom_in, - input [0:19] chany_top_in, - input [0:0] ccff_head, - output [0:19] chany_bottom_out, - output [0:19] chany_top_out, - output [0:0] right_grid_pin_0_, - output [0:0] left_grid_pin_16_, - output [0:0] left_grid_pin_17_, - output [0:0] left_grid_pin_18_, - output [0:0] left_grid_pin_19_, - output [0:0] left_grid_pin_20_, - output [0:0] left_grid_pin_21_, - output [0:0] left_grid_pin_22_, - output [0:0] left_grid_pin_23_, - output [0:0] left_grid_pin_24_, - output [0:0] left_grid_pin_25_, - output [0:0] left_grid_pin_26_, - output [0:0] left_grid_pin_27_, - output [0:0] left_grid_pin_28_, - output [0:0] left_grid_pin_29_, - output [0:0] left_grid_pin_30_, - output [0:0] left_grid_pin_31_, - output [0:0] ccff_tail, - input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT, - output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR, - input [0:0] left_width_0_height_0__pin_0_, - output [0:0] left_width_0_height_0__pin_1_upper, - output [0:0] left_width_0_height_0__pin_1_lower -); +( prog_clk, chany_bottom_in, chany_top_in, ccff_head, chany_bottom_out, chany_top_out, right_grid_pin_0_, left_grid_pin_16_, left_grid_pin_17_, left_grid_pin_18_, left_grid_pin_19_, left_grid_pin_20_, left_grid_pin_21_, left_grid_pin_22_, left_grid_pin_23_, left_grid_pin_24_, left_grid_pin_25_, left_grid_pin_26_, left_grid_pin_27_, left_grid_pin_28_, left_grid_pin_29_, left_grid_pin_30_, left_grid_pin_31_, ccff_tail, gfpga_pad_EMBEDDED_IO_SOC_IN, gfpga_pad_EMBEDDED_IO_SOC_OUT, gfpga_pad_EMBEDDED_IO_SOC_DIR, left_width_0_height_0__pin_0_, left_width_0_height_0__pin_1_upper, left_width_0_height_0__pin_1_lower ); + input [0:0] prog_clk; + input [0:19] chany_bottom_in; + input [0:19] chany_top_in; + input [0:0] ccff_head; + output [0:19] chany_bottom_out; + output [0:19] chany_top_out; + output [0:0] right_grid_pin_0_; + output [0:0] left_grid_pin_16_; + output [0:0] left_grid_pin_17_; + output [0:0] left_grid_pin_18_; + output [0:0] left_grid_pin_19_; + output [0:0] left_grid_pin_20_; + output [0:0] left_grid_pin_21_; + output [0:0] left_grid_pin_22_; + output [0:0] left_grid_pin_23_; + output [0:0] left_grid_pin_24_; + output [0:0] left_grid_pin_25_; + output [0:0] left_grid_pin_26_; + output [0:0] left_grid_pin_27_; + output [0:0] left_grid_pin_28_; + output [0:0] left_grid_pin_29_; + output [0:0] left_grid_pin_30_; + output [0:0] left_grid_pin_31_; + output [0:0] ccff_tail; + input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT; + output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR; + input [0:0] left_width_0_height_0__pin_0_; + output [0:0] left_width_0_height_0__pin_1_upper; + output [0:0] left_width_0_height_0__pin_1_lower; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; @@ -222,7 +221,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(ccff_head[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_0_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_0_sram_inv[0:3]) ); @@ -233,7 +232,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_1_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_1_sram_inv[0:3]) ); @@ -244,7 +243,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_2_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_2_sram_inv[0:3]) ); @@ -255,7 +254,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_2_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_3_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_3_sram_inv[0:3]) ); @@ -266,7 +265,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_4_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_4_sram_inv[0:3]) ); @@ -277,7 +276,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_5_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_5_sram_inv[0:3]) ); @@ -288,7 +287,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_6_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_6_sram_inv[0:3]) ); @@ -299,7 +298,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size10_7_sram[0:3]), .mem_outb(mux_tree_tapbuf_size10_7_sram_inv[0:3]) ); @@ -401,7 +400,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_1_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_0_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_0_sram_inv[0:3]) ); @@ -412,7 +411,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_0_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_1_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_1_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_1_sram_inv[0:3]) ); @@ -423,7 +422,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_3_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_2_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_2_sram_inv[0:3]) ); @@ -434,7 +433,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_2_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_3_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_3_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_3_sram_inv[0:3]) ); @@ -445,7 +444,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_5_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_4_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_4_sram_inv[0:3]) ); @@ -456,7 +455,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_4_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_5_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_5_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_5_sram_inv[0:3]) ); @@ -467,7 +466,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size10_mem_7_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_6_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_6_sram_inv[0:3]) ); @@ -478,7 +477,7 @@ module cby_2__1_ ( .prog_clk(prog_clk[0]), .ccff_head(mux_tree_tapbuf_size8_mem_6_ccff_tail[0]), - .ccff_tail(ccff_tail_mid), + .ccff_tail(mux_tree_tapbuf_size8_mem_7_ccff_tail[0]), .mem_out(mux_tree_tapbuf_size8_7_sram[0:3]), .mem_outb(mux_tree_tapbuf_size8_7_sram_inv[0:3]) ); diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v index 520177c..48f09c7 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__0_.v @@ -1,22 +1,21 @@ module sb_0__0_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_1_, - input [0:19] chanx_right_in, - input [0:0] right_bottom_grid_pin_1_, - input [0:0] right_bottom_grid_pin_3_, - input [0:0] right_bottom_grid_pin_5_, - input [0:0] right_bottom_grid_pin_7_, - input [0:0] right_bottom_grid_pin_9_, - input [0:0] right_bottom_grid_pin_11_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chanx_right_out, - output [0:0] ccff_tail -); +( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_1_; + input [0:19] chanx_right_in; + input [0:0] right_bottom_grid_pin_1_; + input [0:0] right_bottom_grid_pin_3_; + input [0:0] right_bottom_grid_pin_5_; + input [0:0] right_bottom_grid_pin_7_; + input [0:0] right_bottom_grid_pin_9_; + input [0:0] right_bottom_grid_pin_11_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chanx_right_out; + output [0:0] ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v index dc3f1ab..045ce88 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__1_.v @@ -1,27 +1,26 @@ module sb_0__1_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_1_, - input [0:19] chanx_right_in, - input [0:0] right_bottom_grid_pin_34_, - input [0:0] right_bottom_grid_pin_35_, - input [0:0] right_bottom_grid_pin_36_, - input [0:0] right_bottom_grid_pin_37_, - input [0:0] right_bottom_grid_pin_38_, - input [0:0] right_bottom_grid_pin_39_, - input [0:0] right_bottom_grid_pin_40_, - input [0:0] right_bottom_grid_pin_41_, - input [0:19] chany_bottom_in, - input [0:0] bottom_left_grid_pin_1_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chanx_right_out, - output [0:19] chany_bottom_out, - output [0:0] ccff_tail -); +( prog_clk, chany_top_in, top_left_grid_pin_1_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_1_; + input [0:19] chanx_right_in; + input [0:0] right_bottom_grid_pin_34_; + input [0:0] right_bottom_grid_pin_35_; + input [0:0] right_bottom_grid_pin_36_; + input [0:0] right_bottom_grid_pin_37_; + input [0:0] right_bottom_grid_pin_38_; + input [0:0] right_bottom_grid_pin_39_; + input [0:0] right_bottom_grid_pin_40_; + input [0:0] right_bottom_grid_pin_41_; + input [0:19] chany_bottom_in; + input [0:0] bottom_left_grid_pin_1_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chanx_right_out; + output [0:19] chany_bottom_out; + output [0:0] ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v index 6d4a63a..551751f 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_0__2_.v @@ -1,29 +1,28 @@ module sb_0__2_ -( - input [0:0] prog_clk, - input [0:19] chanx_right_in, - input [0:0] right_top_grid_pin_1_, - input [0:0] right_bottom_grid_pin_34_, - input [0:0] right_bottom_grid_pin_35_, - input [0:0] right_bottom_grid_pin_36_, - input [0:0] right_bottom_grid_pin_37_, - input [0:0] right_bottom_grid_pin_38_, - input [0:0] right_bottom_grid_pin_39_, - input [0:0] right_bottom_grid_pin_40_, - input [0:0] right_bottom_grid_pin_41_, - input [0:19] chany_bottom_in, - input [0:0] bottom_left_grid_pin_1_, - input [0:0] ccff_head, - output [0:19] chanx_right_out, - output [0:19] chany_bottom_out, - output [0:0] ccff_tail, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_1_, ccff_head, chanx_right_out, chany_bottom_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chanx_right_in; + input [0:0] right_top_grid_pin_1_; + input [0:0] right_bottom_grid_pin_34_; + input [0:0] right_bottom_grid_pin_35_; + input [0:0] right_bottom_grid_pin_36_; + input [0:0] right_bottom_grid_pin_37_; + input [0:0] right_bottom_grid_pin_38_; + input [0:0] right_bottom_grid_pin_39_; + input [0:0] right_bottom_grid_pin_40_; + input [0:0] right_bottom_grid_pin_41_; + input [0:19] chany_bottom_in; + input [0:0] bottom_left_grid_pin_1_; + input [0:0] ccff_head; + output [0:19] chanx_right_out; + output [0:19] chany_bottom_out; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:1] mux_tree_tapbuf_size2_0_sram; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v index 2b08218..926ad96 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__0_.v @@ -1,41 +1,40 @@ module sb_1__0_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_42_, - input [0:0] top_left_grid_pin_43_, - input [0:0] top_left_grid_pin_44_, - input [0:0] top_left_grid_pin_45_, - input [0:0] top_left_grid_pin_46_, - input [0:0] top_left_grid_pin_47_, - input [0:0] top_left_grid_pin_48_, - input [0:0] top_left_grid_pin_49_, - input [0:19] chanx_right_in, - input [0:0] right_bottom_grid_pin_1_, - input [0:0] right_bottom_grid_pin_3_, - input [0:0] right_bottom_grid_pin_5_, - input [0:0] right_bottom_grid_pin_7_, - input [0:0] right_bottom_grid_pin_9_, - input [0:0] right_bottom_grid_pin_11_, - input [0:19] chanx_left_in, - input [0:0] left_bottom_grid_pin_1_, - input [0:0] left_bottom_grid_pin_3_, - input [0:0] left_bottom_grid_pin_5_, - input [0:0] left_bottom_grid_pin_7_, - input [0:0] left_bottom_grid_pin_9_, - input [0:0] left_bottom_grid_pin_11_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chanx_right_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_1_, right_bottom_grid_pin_3_, right_bottom_grid_pin_5_, right_bottom_grid_pin_7_, right_bottom_grid_pin_9_, right_bottom_grid_pin_11_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_right_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_42_; + input [0:0] top_left_grid_pin_43_; + input [0:0] top_left_grid_pin_44_; + input [0:0] top_left_grid_pin_45_; + input [0:0] top_left_grid_pin_46_; + input [0:0] top_left_grid_pin_47_; + input [0:0] top_left_grid_pin_48_; + input [0:0] top_left_grid_pin_49_; + input [0:19] chanx_right_in; + input [0:0] right_bottom_grid_pin_1_; + input [0:0] right_bottom_grid_pin_3_; + input [0:0] right_bottom_grid_pin_5_; + input [0:0] right_bottom_grid_pin_7_; + input [0:0] right_bottom_grid_pin_9_; + input [0:0] right_bottom_grid_pin_11_; + input [0:19] chanx_left_in; + input [0:0] left_bottom_grid_pin_1_; + input [0:0] left_bottom_grid_pin_3_; + input [0:0] left_bottom_grid_pin_5_; + input [0:0] left_bottom_grid_pin_7_; + input [0:0] left_bottom_grid_pin_9_; + input [0:0] left_bottom_grid_pin_11_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chanx_right_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:3] mux_tree_tapbuf_size11_0_sram; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v index 0296f7a..5fce9c4 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__1_.v @@ -1,51 +1,50 @@ module sb_1__1_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_42_, - input [0:0] top_left_grid_pin_43_, - input [0:0] top_left_grid_pin_44_, - input [0:0] top_left_grid_pin_45_, - input [0:0] top_left_grid_pin_46_, - input [0:0] top_left_grid_pin_47_, - input [0:0] top_left_grid_pin_48_, - input [0:0] top_left_grid_pin_49_, - input [0:19] chanx_right_in, - input [0:0] right_bottom_grid_pin_34_, - input [0:0] right_bottom_grid_pin_35_, - input [0:0] right_bottom_grid_pin_36_, - input [0:0] right_bottom_grid_pin_37_, - input [0:0] right_bottom_grid_pin_38_, - input [0:0] right_bottom_grid_pin_39_, - input [0:0] right_bottom_grid_pin_40_, - input [0:0] right_bottom_grid_pin_41_, - input [0:19] chany_bottom_in, - input [0:0] bottom_left_grid_pin_42_, - input [0:0] bottom_left_grid_pin_43_, - input [0:0] bottom_left_grid_pin_44_, - input [0:0] bottom_left_grid_pin_45_, - input [0:0] bottom_left_grid_pin_46_, - input [0:0] bottom_left_grid_pin_47_, - input [0:0] bottom_left_grid_pin_48_, - input [0:0] bottom_left_grid_pin_49_, - input [0:19] chanx_left_in, - input [0:0] left_bottom_grid_pin_34_, - input [0:0] left_bottom_grid_pin_35_, - input [0:0] left_bottom_grid_pin_36_, - input [0:0] left_bottom_grid_pin_37_, - input [0:0] left_bottom_grid_pin_38_, - input [0:0] left_bottom_grid_pin_39_, - input [0:0] left_bottom_grid_pin_40_, - input [0:0] left_bottom_grid_pin_41_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chanx_right_out, - output [0:19] chany_bottom_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail -); +( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, chanx_right_in, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_42_; + input [0:0] top_left_grid_pin_43_; + input [0:0] top_left_grid_pin_44_; + input [0:0] top_left_grid_pin_45_; + input [0:0] top_left_grid_pin_46_; + input [0:0] top_left_grid_pin_47_; + input [0:0] top_left_grid_pin_48_; + input [0:0] top_left_grid_pin_49_; + input [0:19] chanx_right_in; + input [0:0] right_bottom_grid_pin_34_; + input [0:0] right_bottom_grid_pin_35_; + input [0:0] right_bottom_grid_pin_36_; + input [0:0] right_bottom_grid_pin_37_; + input [0:0] right_bottom_grid_pin_38_; + input [0:0] right_bottom_grid_pin_39_; + input [0:0] right_bottom_grid_pin_40_; + input [0:0] right_bottom_grid_pin_41_; + input [0:19] chany_bottom_in; + input [0:0] bottom_left_grid_pin_42_; + input [0:0] bottom_left_grid_pin_43_; + input [0:0] bottom_left_grid_pin_44_; + input [0:0] bottom_left_grid_pin_45_; + input [0:0] bottom_left_grid_pin_46_; + input [0:0] bottom_left_grid_pin_47_; + input [0:0] bottom_left_grid_pin_48_; + input [0:0] bottom_left_grid_pin_49_; + input [0:19] chanx_left_in; + input [0:0] left_bottom_grid_pin_34_; + input [0:0] left_bottom_grid_pin_35_; + input [0:0] left_bottom_grid_pin_36_; + input [0:0] left_bottom_grid_pin_37_; + input [0:0] left_bottom_grid_pin_38_; + input [0:0] left_bottom_grid_pin_39_; + input [0:0] left_bottom_grid_pin_40_; + input [0:0] left_bottom_grid_pin_41_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chanx_right_out; + output [0:19] chany_bottom_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v index 5253fe0..3b3a57a 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_1__2_.v @@ -1,47 +1,46 @@ module sb_1__2_ -( - input [0:0] prog_clk, - input [0:19] chanx_right_in, - input [0:0] right_top_grid_pin_1_, - input [0:0] right_bottom_grid_pin_34_, - input [0:0] right_bottom_grid_pin_35_, - input [0:0] right_bottom_grid_pin_36_, - input [0:0] right_bottom_grid_pin_37_, - input [0:0] right_bottom_grid_pin_38_, - input [0:0] right_bottom_grid_pin_39_, - input [0:0] right_bottom_grid_pin_40_, - input [0:0] right_bottom_grid_pin_41_, - input [0:19] chany_bottom_in, - input [0:0] bottom_left_grid_pin_42_, - input [0:0] bottom_left_grid_pin_43_, - input [0:0] bottom_left_grid_pin_44_, - input [0:0] bottom_left_grid_pin_45_, - input [0:0] bottom_left_grid_pin_46_, - input [0:0] bottom_left_grid_pin_47_, - input [0:0] bottom_left_grid_pin_48_, - input [0:0] bottom_left_grid_pin_49_, - input [0:19] chanx_left_in, - input [0:0] left_top_grid_pin_1_, - input [0:0] left_bottom_grid_pin_34_, - input [0:0] left_bottom_grid_pin_35_, - input [0:0] left_bottom_grid_pin_36_, - input [0:0] left_bottom_grid_pin_37_, - input [0:0] left_bottom_grid_pin_38_, - input [0:0] left_bottom_grid_pin_39_, - input [0:0] left_bottom_grid_pin_40_, - input [0:0] left_bottom_grid_pin_41_, - input [0:0] ccff_head, - output [0:19] chanx_right_out, - output [0:19] chany_bottom_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chanx_right_in, right_top_grid_pin_1_, right_bottom_grid_pin_34_, right_bottom_grid_pin_35_, right_bottom_grid_pin_36_, right_bottom_grid_pin_37_, right_bottom_grid_pin_38_, right_bottom_grid_pin_39_, right_bottom_grid_pin_40_, right_bottom_grid_pin_41_, chany_bottom_in, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chanx_right_out, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chanx_right_in; + input [0:0] right_top_grid_pin_1_; + input [0:0] right_bottom_grid_pin_34_; + input [0:0] right_bottom_grid_pin_35_; + input [0:0] right_bottom_grid_pin_36_; + input [0:0] right_bottom_grid_pin_37_; + input [0:0] right_bottom_grid_pin_38_; + input [0:0] right_bottom_grid_pin_39_; + input [0:0] right_bottom_grid_pin_40_; + input [0:0] right_bottom_grid_pin_41_; + input [0:19] chany_bottom_in; + input [0:0] bottom_left_grid_pin_42_; + input [0:0] bottom_left_grid_pin_43_; + input [0:0] bottom_left_grid_pin_44_; + input [0:0] bottom_left_grid_pin_45_; + input [0:0] bottom_left_grid_pin_46_; + input [0:0] bottom_left_grid_pin_47_; + input [0:0] bottom_left_grid_pin_48_; + input [0:0] bottom_left_grid_pin_49_; + input [0:19] chanx_left_in; + input [0:0] left_top_grid_pin_1_; + input [0:0] left_bottom_grid_pin_34_; + input [0:0] left_bottom_grid_pin_35_; + input [0:0] left_bottom_grid_pin_36_; + input [0:0] left_bottom_grid_pin_37_; + input [0:0] left_bottom_grid_pin_38_; + input [0:0] left_bottom_grid_pin_39_; + input [0:0] left_bottom_grid_pin_40_; + input [0:0] left_bottom_grid_pin_41_; + input [0:0] ccff_head; + output [0:19] chanx_right_out; + output [0:19] chany_bottom_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v index e2a146e..a2f72b6 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__0_.v @@ -1,30 +1,29 @@ module sb_2__0_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_42_, - input [0:0] top_left_grid_pin_43_, - input [0:0] top_left_grid_pin_44_, - input [0:0] top_left_grid_pin_45_, - input [0:0] top_left_grid_pin_46_, - input [0:0] top_left_grid_pin_47_, - input [0:0] top_left_grid_pin_48_, - input [0:0] top_left_grid_pin_49_, - input [0:0] top_right_grid_pin_1_, - input [0:19] chanx_left_in, - input [0:0] left_bottom_grid_pin_1_, - input [0:0] left_bottom_grid_pin_3_, - input [0:0] left_bottom_grid_pin_5_, - input [0:0] left_bottom_grid_pin_7_, - input [0:0] left_bottom_grid_pin_9_, - input [0:0] left_bottom_grid_pin_11_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail -); +( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chanx_left_in, left_bottom_grid_pin_1_, left_bottom_grid_pin_3_, left_bottom_grid_pin_5_, left_bottom_grid_pin_7_, left_bottom_grid_pin_9_, left_bottom_grid_pin_11_, ccff_head, chany_top_out, chanx_left_out, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_42_; + input [0:0] top_left_grid_pin_43_; + input [0:0] top_left_grid_pin_44_; + input [0:0] top_left_grid_pin_45_; + input [0:0] top_left_grid_pin_46_; + input [0:0] top_left_grid_pin_47_; + input [0:0] top_left_grid_pin_48_; + input [0:0] top_left_grid_pin_49_; + input [0:0] top_right_grid_pin_1_; + input [0:19] chanx_left_in; + input [0:0] left_bottom_grid_pin_1_; + input [0:0] left_bottom_grid_pin_3_; + input [0:0] left_bottom_grid_pin_5_; + input [0:0] left_bottom_grid_pin_7_; + input [0:0] left_bottom_grid_pin_9_; + input [0:0] left_bottom_grid_pin_11_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; wire [0:1] mux_tree_tapbuf_size2_0_sram; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v index 8aa2dd2..0cbcc4e 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__1_.v @@ -1,43 +1,42 @@ module sb_2__1_ -( - input [0:0] prog_clk, - input [0:19] chany_top_in, - input [0:0] top_left_grid_pin_42_, - input [0:0] top_left_grid_pin_43_, - input [0:0] top_left_grid_pin_44_, - input [0:0] top_left_grid_pin_45_, - input [0:0] top_left_grid_pin_46_, - input [0:0] top_left_grid_pin_47_, - input [0:0] top_left_grid_pin_48_, - input [0:0] top_left_grid_pin_49_, - input [0:0] top_right_grid_pin_1_, - input [0:19] chany_bottom_in, - input [0:0] bottom_right_grid_pin_1_, - input [0:0] bottom_left_grid_pin_42_, - input [0:0] bottom_left_grid_pin_43_, - input [0:0] bottom_left_grid_pin_44_, - input [0:0] bottom_left_grid_pin_45_, - input [0:0] bottom_left_grid_pin_46_, - input [0:0] bottom_left_grid_pin_47_, - input [0:0] bottom_left_grid_pin_48_, - input [0:0] bottom_left_grid_pin_49_, - input [0:19] chanx_left_in, - input [0:0] left_bottom_grid_pin_34_, - input [0:0] left_bottom_grid_pin_35_, - input [0:0] left_bottom_grid_pin_36_, - input [0:0] left_bottom_grid_pin_37_, - input [0:0] left_bottom_grid_pin_38_, - input [0:0] left_bottom_grid_pin_39_, - input [0:0] left_bottom_grid_pin_40_, - input [0:0] left_bottom_grid_pin_41_, - input [0:0] ccff_head, - output [0:19] chany_top_out, - output [0:19] chany_bottom_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail -); +( prog_clk, chany_top_in, top_left_grid_pin_42_, top_left_grid_pin_43_, top_left_grid_pin_44_, top_left_grid_pin_45_, top_left_grid_pin_46_, top_left_grid_pin_47_, top_left_grid_pin_48_, top_left_grid_pin_49_, top_right_grid_pin_1_, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_top_out, chany_bottom_out, chanx_left_out, ccff_tail ); + input [0:0] prog_clk; + input [0:19] chany_top_in; + input [0:0] top_left_grid_pin_42_; + input [0:0] top_left_grid_pin_43_; + input [0:0] top_left_grid_pin_44_; + input [0:0] top_left_grid_pin_45_; + input [0:0] top_left_grid_pin_46_; + input [0:0] top_left_grid_pin_47_; + input [0:0] top_left_grid_pin_48_; + input [0:0] top_left_grid_pin_49_; + input [0:0] top_right_grid_pin_1_; + input [0:19] chany_bottom_in; + input [0:0] bottom_right_grid_pin_1_; + input [0:0] bottom_left_grid_pin_42_; + input [0:0] bottom_left_grid_pin_43_; + input [0:0] bottom_left_grid_pin_44_; + input [0:0] bottom_left_grid_pin_45_; + input [0:0] bottom_left_grid_pin_46_; + input [0:0] bottom_left_grid_pin_47_; + input [0:0] bottom_left_grid_pin_48_; + input [0:0] bottom_left_grid_pin_49_; + input [0:19] chanx_left_in; + input [0:0] left_bottom_grid_pin_34_; + input [0:0] left_bottom_grid_pin_35_; + input [0:0] left_bottom_grid_pin_36_; + input [0:0] left_bottom_grid_pin_37_; + input [0:0] left_bottom_grid_pin_38_; + input [0:0] left_bottom_grid_pin_39_; + input [0:0] left_bottom_grid_pin_40_; + input [0:0] left_bottom_grid_pin_41_; + input [0:0] ccff_head; + output [0:19] chany_top_out; + output [0:19] chany_bottom_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; wire [0:3] mux_tree_tapbuf_size10_0_sram; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v index cf2fdd6..61785a3 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/routing/sb_2__2_.v @@ -1,37 +1,36 @@ module sb_2__2_ -( - input [0:0] prog_clk, - input [0:19] chany_bottom_in, - input [0:0] bottom_right_grid_pin_1_, - input [0:0] bottom_left_grid_pin_42_, - input [0:0] bottom_left_grid_pin_43_, - input [0:0] bottom_left_grid_pin_44_, - input [0:0] bottom_left_grid_pin_45_, - input [0:0] bottom_left_grid_pin_46_, - input [0:0] bottom_left_grid_pin_47_, - input [0:0] bottom_left_grid_pin_48_, - input [0:0] bottom_left_grid_pin_49_, - input [0:19] chanx_left_in, - input [0:0] left_top_grid_pin_1_, - input [0:0] left_bottom_grid_pin_34_, - input [0:0] left_bottom_grid_pin_35_, - input [0:0] left_bottom_grid_pin_36_, - input [0:0] left_bottom_grid_pin_37_, - input [0:0] left_bottom_grid_pin_38_, - input [0:0] left_bottom_grid_pin_39_, - input [0:0] left_bottom_grid_pin_40_, - input [0:0] left_bottom_grid_pin_41_, - input [0:0] ccff_head, - output [0:19] chany_bottom_out, - output [0:19] chanx_left_out, - output [0:0] ccff_tail, - input SC_IN_TOP, - input SC_IN_BOT, - output SC_OUT_TOP, - output SC_OUT_BOT -); +( prog_clk, chany_bottom_in, bottom_right_grid_pin_1_, bottom_left_grid_pin_42_, bottom_left_grid_pin_43_, bottom_left_grid_pin_44_, bottom_left_grid_pin_45_, bottom_left_grid_pin_46_, bottom_left_grid_pin_47_, bottom_left_grid_pin_48_, bottom_left_grid_pin_49_, chanx_left_in, left_top_grid_pin_1_, left_bottom_grid_pin_34_, left_bottom_grid_pin_35_, left_bottom_grid_pin_36_, left_bottom_grid_pin_37_, left_bottom_grid_pin_38_, left_bottom_grid_pin_39_, left_bottom_grid_pin_40_, left_bottom_grid_pin_41_, ccff_head, chany_bottom_out, chanx_left_out, ccff_tail, SC_IN_TOP, SC_IN_BOT, SC_OUT_TOP, SC_OUT_BOT ); + input [0:0] prog_clk; + input [0:19] chany_bottom_in; + input [0:0] bottom_right_grid_pin_1_; + input [0:0] bottom_left_grid_pin_42_; + input [0:0] bottom_left_grid_pin_43_; + input [0:0] bottom_left_grid_pin_44_; + input [0:0] bottom_left_grid_pin_45_; + input [0:0] bottom_left_grid_pin_46_; + input [0:0] bottom_left_grid_pin_47_; + input [0:0] bottom_left_grid_pin_48_; + input [0:0] bottom_left_grid_pin_49_; + input [0:19] chanx_left_in; + input [0:0] left_top_grid_pin_1_; + input [0:0] left_bottom_grid_pin_34_; + input [0:0] left_bottom_grid_pin_35_; + input [0:0] left_bottom_grid_pin_36_; + input [0:0] left_bottom_grid_pin_37_; + input [0:0] left_bottom_grid_pin_38_; + input [0:0] left_bottom_grid_pin_39_; + input [0:0] left_bottom_grid_pin_40_; + input [0:0] left_bottom_grid_pin_41_; + input [0:0] ccff_head; + output [0:19] chany_bottom_out; + output [0:19] chanx_left_out; + output [0:0] ccff_tail; + input SC_IN_TOP; + input SC_IN_BOT; + output SC_OUT_TOP; + output SC_OUT_BOT; wire [0:1] mux_tree_tapbuf_size2_0_sram; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v deleted file mode 100644 index be56f7f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/SRC/sub_module/std_cell_extract.v +++ /dev/null @@ -1,29 +0,0 @@ -`timescale 1ns/1ps - -// -// -// -// -// -// - -// -// -// - -module GPIO (A, IE, OE, Y, in, out, mem_out); - output A; - output IE; - output OE; - output Y; - input in; - output out; - input mem_out; - - assign A = in; - assign out = Y; - assign IE = mem_out; - sky130_fd_sc_hd__inv_1 ie_oe_inv ( - .A (mem_out), - .Y (OE) ); -endmodule diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml index 220b379..c8f2ad8 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,7 +2,7 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Fri Nov 6 14:45:09 2020 + - Date: Sun Nov 8 17:53:57 2020 --> diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml index 35d7350..e9c2512 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Fri Nov 6 14:45:09 2020 + - Date: Sun Nov 8 17:53:56 2020 --> diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log index 8da0c6f..2eed1b2 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/openfpgashell.log @@ -83,7 +83,7 @@ Warning 18: [LINE 618] false logically-equivalent pin clb[0].I6[1]. Warning 19: [LINE 618] false logically-equivalent pin clb[0].I6[2]. Warning 20: [LINE 624] false logically-equivalent pin clb[0].I7[1]. Warning 21: [LINE 624] false logically-equivalent pin clb[0].I7[2]. -# Building complex block graph took 0.01 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) +# Building complex block graph took 0.00 seconds (max_rss 9.5 MiB, delta_rss +0.5 MiB) # Load circuit # Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) # Clean circuit @@ -250,12 +250,12 @@ Device Utilization: 0.25 (target 1.00) Netlist conversion complete. -# Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) +# Packing took 0.00 seconds (max_rss 10.6 MiB, delta_rss +0.7 MiB) # Load Packing Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) -Finished loading packed FPGA netlist file (took 0.01 seconds). +Finished loading packed FPGA netlist file (took 0 seconds). Warning 34: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.6 MiB, delta_rss +0.1 MiB) Warning 35: Netlist contains 0 global net to non-global architecture pin connections @@ -301,7 +301,7 @@ Device Utilization: 0.25 (target 1.00) Physical Tile clb: Block Utilization: 0.25 Logical Block: clb -## Build Device Grid took 0.00 seconds (max_rss 10.7 MiB, delta_rss +0.0 MiB) +## Build Device Grid took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) ## Build tileable routing resource graph X-direction routing channel width is 40 Y-direction routing channel width is 40 @@ -309,10 +309,10 @@ Warning 40: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi Warning 41: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 42: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 43: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) +## Build tileable routing resource graph took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) RR Graph Nodes: 756 RR Graph Edges: 2930 -# Create Device took 0.01 seconds (max_rss 11.2 MiB, delta_rss +0.5 MiB) +# Create Device took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Placement ## Computing placement delta delay look-up @@ -321,12 +321,12 @@ Warning 44: in check_rr_node: RR node: 119 type: OPIN location: (1,1) pin: 50 pi Warning 45: in check_rr_node: RR node: 120 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 46: in check_rr_node: RR node: 327 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 47: in check_rr_node: RR node: 328 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -### Build routing resource graph took 0.00 seconds (max_rss 11.2 MiB, delta_rss +0.0 MiB) +### Build routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) RR Graph Nodes: 756 RR Graph Edges: 2428 ### Computing delta delays -### Computing delta delays took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.0 MiB) -## Computing placement delta delay look-up took 0.00 seconds (max_rss 11.5 MiB, delta_rss +0.3 MiB) +### Computing delta delays took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) +## Computing placement delta delay look-up took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) There are 3 point to point connections in this circuit. @@ -440,7 +440,7 @@ Placement total # of swap attempts: 292 Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.5 MiB) +# Placement took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Routing ## Build tileable routing resource graph @@ -450,7 +450,7 @@ Warning 48: in check_rr_node: RR node: 105 type: OPIN location: (1,1) pin: 50 pi Warning 49: in check_rr_node: RR node: 106 type: OPIN location: (1,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. Warning 50: in check_rr_node: RR node: 195 type: OPIN location: (2,1) pin: 50 pin_name: clb.regout[0] capacity: 1 has no out-going edges. Warning 51: in check_rr_node: RR node: 196 type: OPIN location: (2,1) pin: 51 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -## Build tileable routing resource graph took 0.01 seconds (max_rss 11.7 MiB, delta_rss +0.0 MiB) +## Build tileable routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) RR Graph Nodes: 756 RR Graph Edges: 2930 Confirming router algorithm: TIMING_DRIVEN. @@ -464,7 +464,7 @@ Restoring best routing Critical path: 0.86731 ns Successfully routed after 2 routing iterations. Router Stats: total_nets_routed: 4 total_connections_routed: 4 total_heap_pushes: 289 total_heap_pops: 187 -# Routing took 0.01 seconds (max_rss 11.9 MiB, delta_rss +0.2 MiB) +# Routing took 0.01 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. @@ -562,9 +562,9 @@ Setup slack histogram: [ -8.7e-10: -8.7e-10) 0 ( 0.0%) | [ -8.7e-10: -8.7e-10) 0 ( 0.0%) | -Timing analysis took 0.000428495 seconds (0.000379131 STA, 4.9364e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). +Timing analysis took 0.000351611 seconds (0.000312774 STA, 3.8837e-05 slack) (54 full updates: 51 setup, 0 hold, 3 combined). VPR suceeded -The entire flow of VPR took 0.09 seconds (max_rss 11.9 MiB) +The entire flow of VPR took 0.07 seconds (max_rss 12.7 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -578,10 +578,10 @@ Warning 54: Automatically set circuit model 'sky130_fd_sc_hd__dfxbp_1' to be def Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'mux_tree_tapbuf' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfxbp_1' for circuit model 'frac_lut4' port 'sram') -Read OpenFPGA architecture took 0.00 seconds (max_rss 12.0 MiB, delta_rss +0.1 MiB) +Read OpenFPGA architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Check circuit library Checking circuit library passed. -Check circuit library took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) +Check circuit library took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Found 0 errors when checking configurable memory circuit models! Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml @@ -590,7 +590,7 @@ Confirm selected options when call command 'read_openfpga_simulation_setting': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Read OpenFPGA simulation settings -Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) +Read OpenFPGA simulation settings took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Command line to execute: link_openfpga_arch --activity_file top_ace_out.act --sort_gsb_chan_node_in_edges @@ -633,7 +633,7 @@ Done with 18 nodes mapping [88%] Backannotated GSB[2][1] [100%] Backannotated GSB[2][2] Backannotated 9 General Switch Blocks (GSBs). -# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) +# Build General Switch Block(GSB) annotation on top of routing resource graph took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Sort incoming edges for each routing track output node of General Switch Block(GSB) [11%] Sorted edges for GSB[0][0] [22%] Sorted edges for GSB[0][1] @@ -645,14 +645,14 @@ Backannotated 9 General Switch Blocks (GSBs). [88%] Sorted edges for GSB[2][1] [100%] Sorted edges for GSB[2][2] Sorted edges for 9 General Switch Blocks (GSBs). -# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.3 MiB, delta_rss +0.0 MiB) +# Sort incoming edges for each routing track output node of General Switch Block(GSB) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build a library of physical multiplexers Built a multiplexer library of 15 physical multiplexers. Maximum multiplexer size is 17. -# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.3 MiB) +# Build a library of physical multiplexers took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Build the annotation about direct connection between tiles Built 6 tile-to-tile direct connections -# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.5 MiB, delta_rss +0.0 MiB) +# Build the annotation about direct connection between tiles took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Building annotation for mapped blocks on grid locations...Done User specified the operating clock frequency to use VPR results Use VPR critical path delay 1.04077e-18 [ns] with a 20 [%] slack in OpenFPGA. @@ -662,7 +662,7 @@ Average net density: 0.42 Median net density: 0.00 Average net density after weighting: 0.42 Will apply 2 operating clock cycles to simulations -Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.3 MiB) +Link OpenFPGA architecture to VPR architecture took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_task/arch/fabric_key.xml @@ -676,7 +676,7 @@ Confirm selected options when call command 'build_fabric': --verbose: off Identify unique General Switch Blocks (GSBs) Detected 9 unique general switch blocks from a total of 9 (compression rate=0.00%) -Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.6 MiB, delta_rss +0.0 MiB) +Identify unique General Switch Blocks (GSBs) took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) Read Fabric Key Read Fabric Key took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) @@ -691,7 +691,7 @@ Build fabric module graph # Build local encoder (for multiplexers) modules # Build local encoder (for multiplexers) modules took 0.00 seconds (max_rss 12.7 MiB, delta_rss +0.0 MiB) # Building multiplexer modules -# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.3 MiB) +# Building multiplexer modules took 0.00 seconds (max_rss 12.9 MiB, delta_rss +0.2 MiB) # Build Look-Up Table (LUT) modules # Build Look-Up Table (LUT) modules took 0.00 seconds (max_rss 13.2 MiB, delta_rss +0.3 MiB) # Build wire modules @@ -703,7 +703,7 @@ Building logical tiles...Done Building physical tiles...Done # Build grid modules took 0.00 seconds (max_rss 13.7 MiB, delta_rss +0.5 MiB) # Build unique routing modules... -# Build unique routing modules... took 0.02 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB) +# Build unique routing modules... took 0.01 seconds (max_rss 16.5 MiB, delta_rss +2.8 MiB) # Build FPGA fabric module ## Add grid instances to top module ## Add grid instances to top module took 0.00 seconds (max_rss 16.5 MiB, delta_rss +0.0 MiB) @@ -720,7 +720,7 @@ Building physical tiles...Done ## Add module nets for configuration buses ## Add module nets for configuration buses took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) # Build FPGA fabric module took 0.01 seconds (max_rss 17.3 MiB, delta_rss +0.8 MiB) -Build fabric module graph took 0.03 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB) +Build fabric module graph took 0.02 seconds (max_rss 17.3 MiB, delta_rss +4.6 MiB) Create I/O location mapping for top module Create I/O location mapping for top module took 0.00 seconds (max_rss 17.3 MiB, delta_rss +0.0 MiB) @@ -756,7 +756,7 @@ Build fabric-independent bitstream for implementation 'top' took 0.01 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) Warning 56: Directory path is empty and nothing will be created. Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.03 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) +Write 2106 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.02 seconds (max_rss 17.8 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -777,7 +777,7 @@ Confirm selected options when call command 'write_fabric_bitstream': --verbose: off Warning 57: Directory path is empty and nothing will be created. Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.00 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) +Write 2106 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.01 seconds (max_rss 18.1 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml @@ -849,7 +849,7 @@ Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Written 73 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.16 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB) + took 0.17 seconds (max_rss 18.3 MiB, delta_rss +0.2 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping @@ -879,7 +879,7 @@ Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 0.04 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) + took 0.03 seconds (max_rss 18.3 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -887,6 +887,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 0.25 seconds +The entire OpenFPGA flow took 0.19 seconds Thank you for using OpenFPGA! diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl index 4954250..7fba78d 100644 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl +++ b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_Verilog/proj_const.tcl @@ -1,5 +1,5 @@ -set DIE_HEIGHT 1000 -set DIE_WIDTH 1000 +set DIE_HEIGHT 700 +set DIE_WIDTH 700 set DESIGN_NAME fpga_core set TASK_NAME FPGA22_HIER_SKY_task set VERILOG_PROJ_DIR FPGA22_HIER_SKY_Verilog @@ -7,6 +7,7 @@ set FPGA_ROW 2 set FPGA_COL 2 set INIT_DESIGN_INPUT DP_RM_NDM set TECHNOLOGY skywater -set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ grid_clb grid_io_bottom grid_io_left grid_io_right grid_io_top]; +set DP_BLOCK_REFS [list sb_0__0_ sb_0__1_ sb_0__2_ sb_1__0_ sb_1__1_ sb_1__2_ sb_2__0_ sb_2__1_ sb_2__2_ cbx_1__0_ cbx_1__1_ cbx_1__2_ cby_0__1_ cby_1__1_ cby_2__1_ grid_clb]; set DP_FLOW "hier"; set DESIGN_STYLE "hier"; +set STANDARD_CELLS sc_hd; diff --git a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v b/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v deleted file mode 100644 index be56f7f..0000000 --- a/FPGA22_HIER_SKY_PNR/FPGA22_HIER_SKY_task/sc_verilog/std_cell_extract.v +++ /dev/null @@ -1,29 +0,0 @@ -`timescale 1ns/1ps - -// -// -// -// -// -// - -// -// -// - -module GPIO (A, IE, OE, Y, in, out, mem_out); - output A; - output IE; - output OE; - output Y; - input in; - output out; - input mem_out; - - assign A = in; - assign out = Y; - assign IE = mem_out; - sky130_fd_sc_hd__inv_1 ie_oe_inv ( - .A (mem_out), - .Y (OE) ); -endmodule diff --git a/FPGA22_HIER_SKY_PNR/README.md b/FPGA22_HIER_SKY_PNR/README.md index 0c9ee97..f1baa09 100644 --- a/FPGA22_HIER_SKY_PNR/README.md +++ b/FPGA22_HIER_SKY_PNR/README.md @@ -5,11 +5,12 @@ FPGA22_HIER_SKY_PNR Updates ------------------- -- **Merged `grid_io` modules with connection blocks** -- **Pre-routed scan chain signals** -- **Created `carry_chain` feedthrough between `grid_clb` modules** -- Prerouting global signals (`Test_en`) -- Prerouting clock signals +- Merged `grid_io` modules with connection blocks +- Pre-routed scan chain signals +- Created `carry_chain` feedthrough between `grid_clb` modules +- **Prerouting global signals (`Test_en`)** +- **Prerouting clock signals** +- **Enabled Feed through generation for clock** Directory Structure ------------------- diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png new file mode 100644 index 0000000..3ffeb3c Binary files /dev/null and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigFlipFLop.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png new file mode 100644 index 0000000..c65d9cd Binary files /dev/null and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ConfigurationChain.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/ProgClockTree.png index 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a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/power_contacts.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png index 7236298..fae9f14 100644 Binary files a/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png and b/FPGA22_HIER_SKY_PNR/fpga_core/Screenshots/utilization.png differ diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v index 0e90ffa..2e6c6ec 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.fm.v @@ -4,11 +4,9 @@ // // // -module direct_interc_5 ( in , out ) ; +module direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; - -assign out[0] = in[0] ; endmodule @@ -32,7 +30,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__2 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_1_1 ( in , out ) ; +module direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -40,7 +38,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_0_1 ( in , out ) ; +module direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -48,7 +46,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_4 ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -56,40 +54,61 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; output [0:0] mem_outb ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; + +wire aps_rename_1_ ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_7 ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -98,25 +117,27 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; -EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -125,33 +146,33 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; -logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; -direct_interc_4 direct_interc_0_ ( + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -160,19 +181,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -181,19 +202,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -202,19 +223,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -223,19 +244,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -244,19 +265,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -265,19 +286,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -286,19 +307,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -307,23 +328,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_45 ( const1 ) ; +module cby_2__1__const1 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -333,8 +354,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_45 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -345,8 +367,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -362,20 +384,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15_11 ( const1 ) ; +module cby_2__1__const1_15 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -385,8 +405,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_15_11 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -397,8 +418,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -414,20 +435,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14_13 ( const1 ) ; +module cby_2__1__const1_14 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -437,8 +456,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -449,8 +469,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -466,20 +486,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_13 ( const1 ) ; +module cby_2__1__const1_13 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -489,8 +507,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_13_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -501,8 +520,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -518,20 +537,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_12_13 ( const1 ) ; +module cby_2__1__const1_12 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -541,8 +558,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_12_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -553,8 +571,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -570,20 +588,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_11_13 ( const1 ) ; +module cby_2__1__const1_11 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -593,8 +609,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_11_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -605,8 +622,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -622,20 +639,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_10_13 ( const1 ) ; +module cby_2__1__const1_10 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -645,8 +660,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_10_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -657,8 +673,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -674,20 +690,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_9_13 ( const1 ) ; +module cby_2__1__const1_9 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -697,8 +711,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_9_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -709,8 +724,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -726,16 +741,14 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -744,19 +757,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -765,19 +778,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -786,19 +799,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -807,19 +820,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -828,19 +841,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -849,19 +862,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -870,19 +883,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -891,19 +904,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -912,23 +925,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_8_13 ( const1 ) ; +module cby_2__1__const1_8 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -940,8 +953,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -958,8 +972,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -975,20 +989,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_7_13 ( const1 ) ; +module cby_2__1__const1_7 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1000,8 +1012,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1018,8 +1031,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1035,20 +1048,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_13 ( const1 ) ; +module cby_2__1__const1_6 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1060,8 +1071,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1078,8 +1090,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1095,20 +1107,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_13 ( const1 ) ; +module cby_2__1__const1_5 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1120,8 +1130,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1138,8 +1149,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1155,20 +1166,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_14 ( const1 ) ; +module cby_2__1__const1_4 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1180,8 +1189,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1198,8 +1208,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1215,20 +1225,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_14 ( const1 ) ; +module cby_2__1__const1_3 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1240,8 +1248,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1258,8 +1267,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1275,20 +1284,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_14 ( const1 ) ; +module cby_2__1__const1_2 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1300,8 +1307,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1318,8 +1326,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1335,20 +1343,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_14 ( const1 ) ; +module cby_2__1__const1_1 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1360,8 +1366,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1378,8 +1385,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1395,20 +1402,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0_14 ( const1 ) ; +module cby_2__1__const1_0 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1420,8 +1425,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1438,8 +1444,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1464,7 +1470,8 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1495,6 +1502,7 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1547,281 +1555,354 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) ) ; -mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) ) ; -mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) ) ; -mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) ) ; -mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) ) ; -mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) ) ; -mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) ) ; -mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) ) ; -mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) ) ; -mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) ) ; -mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) ) ; -mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) ) ; -mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) ) ; -mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) ) ; -mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) ) ; -mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1836,13 +1917,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1857,13 +1938,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1878,13 +1959,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1899,13 +1980,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1920,13 +2001,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1941,13 +2022,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1962,13 +2043,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1983,17 +2064,323 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_44 ( const1 ) ; +module cby_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2008,7 +2395,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_44 const1_0_ ( +cby_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -2035,12 +2422,12 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module const1_14_12 ( const1 ) ; +module cby_1__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2056,7 +2443,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14_12 const1_0_ ( +cby_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -2086,488 +2473,182 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_12 ( const1 ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_12_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_11_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_10_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_9_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_9_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_8_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_8_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2585,7 +2666,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_12 const1_0_ ( +cby_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2621,12 +2702,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_12 ( const1 ) ; +module cby_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2644,7 +2725,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_12 const1_0_ ( +cby_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2680,12 +2761,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_12 ( const1 ) ; +module cby_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2703,7 +2784,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_12 const1_0_ ( +cby_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2739,12 +2820,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_13 ( const1 ) ; +module cby_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2762,7 +2843,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_13 const1_0_ ( +cby_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2798,12 +2879,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_13 ( const1 ) ; +module cby_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2821,7 +2902,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_13 const1_0_ ( +cby_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2857,12 +2938,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_13 ( const1 ) ; +module cby_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2880,7 +2961,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_13 const1_0_ ( +cby_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2916,12 +2997,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_13 ( const1 ) ; +module cby_1__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2939,7 +3020,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_13 const1_0_ ( +cby_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2975,12 +3056,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0_13 ( const1 ) ; +module cby_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2998,7 +3079,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_13 const1_0_ ( +cby_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -3040,7 +3121,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3064,6 +3148,10 @@ output [0:0] left_grid_pin_29_ ; output [0:0] left_grid_pin_30_ ; output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -3113,327 +3201,354 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; endmodule -module direct_interc_3 ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -3441,8 +3556,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3451,13 +3566,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -3471,17 +3588,17 @@ wire aps_rename_2_ ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_6 ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 , p_abuf1 ) ; @@ -3498,22 +3615,24 @@ output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -3524,7 +3643,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -3532,17 +3651,17 @@ logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_3 direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc_3 direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3562,12 +3681,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module const1_43 ( const1 ) ; +module cby_0__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3585,10 +3704,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_43 const1_0_ ( +cby_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -3618,6 +3735,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -3626,7 +3745,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; + right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3641,250 +3760,246 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) ) ; endmodule -module direct_interc_2 ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -3892,8 +4007,14 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3902,15 +4023,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -3921,14 +4042,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_5 ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -3944,21 +4065,23 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -3969,7 +4092,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -3977,17 +4100,17 @@ logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_2 direct_interc_0_ ( +cbx_1__2__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__2__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4007,8 +4130,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4028,8 +4151,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4049,8 +4172,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4070,8 +4193,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4091,8 +4214,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4107,13 +4230,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4133,8 +4256,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4154,12 +4277,12 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module const1_42 ( const1 ) ; +module cbx_1__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4175,7 +4298,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_42 const1_0_ ( +cbx_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -4205,12 +4328,267 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15_10 ( const1 ) ; +module cbx_1__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4225,7 +4603,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_15_10 const1_0_ ( +cbx_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -4246,18 +4624,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_14_11 ( const1 ) ; +module cbx_1__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4273,7 +4651,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14_11 const1_0_ ( +cbx_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -4303,255 +4681,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_12_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_11_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_10_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_9_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_9_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4566,13 +4697,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4592,8 +4723,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4613,8 +4744,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4634,8 +4765,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4655,8 +4786,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4676,8 +4807,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4697,8 +4828,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4713,13 +4844,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4734,17 +4865,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8_11 ( const1 ) ; +module cbx_1__2__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4762,7 +4893,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8_11 const1_0_ ( +cbx_1__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -4798,12 +4929,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_7_11 ( const1 ) ; +module cbx_1__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4821,7 +4952,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_11 const1_0_ ( +cbx_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -4857,12 +4988,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_11 ( const1 ) ; +module cbx_1__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4880,7 +5011,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_11 const1_0_ ( +cbx_1__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -4916,12 +5047,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_11 ( const1 ) ; +module cbx_1__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4939,7 +5070,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_11 const1_0_ ( +cbx_1__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -4975,12 +5106,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_12 ( const1 ) ; +module cbx_1__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4998,7 +5129,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_12 const1_0_ ( +cbx_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -5034,12 +5165,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_12 ( const1 ) ; +module cbx_1__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5057,7 +5188,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_12 const1_0_ ( +cbx_1__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -5093,12 +5224,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_12 ( const1 ) ; +module cbx_1__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5116,7 +5247,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_12 const1_0_ ( +cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -5152,12 +5283,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_12 ( const1 ) ; +module cbx_1__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5173,12 +5304,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_12 const1_0_ ( +cbx_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -5204,19 +5332,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_0_12 ( const1 ) ; +module cbx_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5234,7 +5361,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_12 const1_0_ ( +cbx_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -5317,7 +5444,7 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -5371,327 +5498,386 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5706,13 +5892,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5727,13 +5913,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5748,13 +5934,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5769,13 +5955,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5790,13 +5976,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5811,13 +5997,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5832,13 +6018,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5853,17 +6039,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_41 ( const1 ) ; +module cbx_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5879,7 +6065,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_41 const1_0_ ( +cbx_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -5909,12 +6095,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14_10 ( const1 ) ; +module cbx_1__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5930,7 +6116,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14_10 const1_0_ ( +cbx_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -5960,165 +6146,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_10 ( const1 ) ; +module cbx_1__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_12_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_11_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6133,7 +6166,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10_10 const1_0_ ( +cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6154,18 +6187,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_9_10 ( const1 ) ; +module cbx_1__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6181,7 +6214,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_9_10 const1_0_ ( +cbx_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -6211,12 +6244,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_8_10 ( const1 ) ; +module cbx_1__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6232,7 +6265,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_8_10 const1_0_ ( +cbx_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -6262,180 +6295,333 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7_10 ( const1 ) ; +module cbx_1__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6453,7 +6639,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_10 const1_0_ ( +cbx_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6489,12 +6675,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_10 ( const1 ) ; +module cbx_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6512,7 +6698,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_10 const1_0_ ( +cbx_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6548,12 +6734,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_10 ( const1 ) ; +module cbx_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6571,7 +6757,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_10 const1_0_ ( +cbx_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6607,12 +6793,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_11 ( const1 ) ; +module cbx_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6630,7 +6816,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_11 const1_0_ ( +cbx_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6666,12 +6852,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_11 ( const1 ) ; +module cbx_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6689,7 +6875,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_11 const1_0_ ( +cbx_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6725,12 +6911,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_11 ( const1 ) ; +module cbx_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +cbx_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6748,7 +6989,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_11 const1_0_ ( +cbx_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -6784,12 +7025,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_11 ( const1 ) ; +module cbx_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6807,10 +7048,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_11 const1_0_ ( +cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6840,65 +7079,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_0_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_0_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -6909,8 +7091,8 @@ module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -6934,12 +7116,11 @@ output [0:0] bottom_grid_pin_13_ ; output [0:0] bottom_grid_pin_14_ ; output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -6991,318 +7172,394 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; + .X ( ropt_net_153 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; + .X ( ropt_net_156 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) ) ; + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) ) ; + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) ) ; + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7311,17 +7568,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7329,21 +7584,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7353,26 +7609,26 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7383,25 +7639,31 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_5 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7415,8 +7677,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7424,21 +7686,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7448,17 +7708,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7466,9 +7725,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7479,7 +7739,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7487,18 +7747,24 @@ logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_4 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7512,8 +7778,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7521,22 +7787,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7546,17 +7809,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7564,9 +7826,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7577,7 +7840,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7585,18 +7848,24 @@ logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_3 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7610,8 +7879,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7619,22 +7888,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7644,17 +7910,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7662,9 +7927,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7675,7 +7941,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7683,24 +7949,24 @@ logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_2 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7714,8 +7980,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7726,13 +7992,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -7748,12 +8015,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7761,9 +8029,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7774,7 +8043,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7783,16 +8052,16 @@ logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_0_ ( +cbx_1__0__direct_interc_1 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -direct_interc_1 direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -7800,14 +8069,14 @@ assign out[0] = in[0] ; endmodule -module direct_interc_0 ( in , out ) ; +module cbx_1__0__direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7821,8 +8090,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7833,13 +8102,13 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -7855,12 +8124,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7868,9 +8138,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7881,7 +8152,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7890,17 +8161,17 @@ logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_0 direct_interc_0_ ( +cbx_1__0__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -direct_interc_1 direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7915,13 +8186,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7936,13 +8207,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7957,13 +8228,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7978,13 +8249,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7999,13 +8270,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8020,17 +8291,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_40 ( const1 ) ; +module cbx_1__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8048,7 +8319,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_40 const1_0_ ( +cbx_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -8084,12 +8355,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_10 ( const1 ) ; +module cbx_1__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8107,7 +8378,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_10 const1_0_ ( +cbx_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -8143,12 +8414,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_10 ( const1 ) ; +module cbx_1__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8166,7 +8437,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_10 const1_0_ ( +cbx_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -8202,12 +8473,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_10 ( const1 ) ; +module cbx_1__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8225,7 +8496,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_10 const1_0_ ( +cbx_1__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -8261,71 +8532,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_10 ( const1 ) ; +module cbx_1__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_0_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8342,7 +8554,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_0_10 const1_0_ ( +cbx_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -8375,6 +8587,65 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -8390,7 +8661,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -8429,13 +8700,15 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -8455,375 +8728,401 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8839,7 +9138,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8856,8 +9155,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8873,12 +9172,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module const1_39 ( const1 ) ; +module sb_2__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8889,7 +9188,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_39 const1_0_ ( +sb_2__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -8904,12 +9203,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_33 ( const1 ) ; +module sb_2__2__const1_33 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8920,7 +9219,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_33 const1_0_ ( +sb_2__2__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -8935,12 +9234,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_32 ( const1 ) ; +module sb_2__2__const1_32 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8951,7 +9250,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_32 const1_0_ ( +sb_2__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -8966,7 +9265,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8979,14 +9278,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9002,8 +9299,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9019,8 +9316,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9036,8 +9333,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9053,8 +9350,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9070,8 +9367,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9087,8 +9384,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9104,8 +9401,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9121,8 +9418,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9138,8 +9435,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9155,8 +9452,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9172,8 +9469,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9189,8 +9486,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9206,8 +9503,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9223,8 +9520,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9240,8 +9537,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9257,8 +9554,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9274,8 +9571,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9291,8 +9588,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9308,8 +9605,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9325,8 +9622,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9342,8 +9639,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9359,8 +9656,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9376,12 +9673,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module const1_31_2 ( const1 ) ; +module sb_2__2__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9391,7 +9688,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31_2 const1_0_ ( +sb_2__2__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9403,12 +9700,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30_3 ( const1 ) ; +module sb_2__2__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9418,7 +9715,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30_3 const1_0_ ( +sb_2__2__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9430,12 +9727,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29_3 ( const1 ) ; +module sb_2__2__const1_29 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9445,7 +9742,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29_3 const1_0_ ( +sb_2__2__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9457,12 +9754,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28_4 ( const1 ) ; +module sb_2__2__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9472,7 +9769,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_28_4 const1_0_ ( +sb_2__2__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9484,12 +9781,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_27_4 ( const1 ) ; +module sb_2__2__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9499,7 +9796,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_27_4 const1_0_ ( +sb_2__2__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9511,12 +9808,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_26_7 ( const1 ) ; +module sb_2__2__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9526,7 +9823,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_26_7 const1_0_ ( +sb_2__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9538,12 +9835,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_25_7 ( const1 ) ; +module sb_2__2__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9553,7 +9850,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_25_7 const1_0_ ( +sb_2__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9565,12 +9862,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_24_7 ( const1 ) ; +module sb_2__2__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9580,7 +9877,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_24_7 const1_0_ ( +sb_2__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9592,12 +9889,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_23_7 ( const1 ) ; +module sb_2__2__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9607,7 +9904,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_23_7 const1_0_ ( +sb_2__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9619,12 +9916,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22_8 ( const1 ) ; +module sb_2__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9634,34 +9931,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_21_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_21_8 const1_0_ ( +sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9673,12 +9943,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20_8 ( const1 ) ; +module sb_2__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9688,7 +9958,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20_8 const1_0_ ( +sb_2__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9700,12 +9970,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19_8 ( const1 ) ; +module sb_2__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9715,7 +9985,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19_8 const1_0_ ( +sb_2__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9727,12 +9997,201 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18_9 ( const1 ) ; +module sb_2__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9741,7 +10200,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_18_9 const1_0_ ( +sb_2__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -9750,12 +10209,12 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17_9 ( const1 ) ; +module sb_2__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9765,7 +10224,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17_9 const1_0_ ( +sb_2__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -9777,12 +10236,66 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16_9 ( const1 ) ; +module sb_2__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9791,7 +10304,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_16_9 const1_0_ ( +sb_2__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -9800,219 +10313,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_15_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_14_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_14_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_13_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_12_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_12_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_11_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_11_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_10_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_10_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_9_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_9_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_8_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_8_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10031,8 +10332,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10050,8 +10351,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10069,8 +10370,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10088,12 +10389,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module const1_7_9 ( const1 ) ; +module sb_2__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10106,7 +10407,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_7_9 const1_0_ ( +sb_2__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -10127,12 +10428,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_6_9 ( const1 ) ; +module sb_2__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10145,7 +10446,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_6_9 const1_0_ ( +sb_2__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -10166,12 +10467,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5_9 ( const1 ) ; +module sb_2__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10184,7 +10485,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_5_9 const1_0_ ( +sb_2__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -10205,12 +10506,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4_9 ( const1 ) ; +module sb_2__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10223,10 +10524,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_4_9 const1_0_ ( +sb_2__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10241,10 +10540,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10263,8 +10566,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10282,8 +10585,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10301,8 +10604,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10320,12 +10623,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module const1_3_9 ( const1 ) ; +module sb_2__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10339,7 +10642,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_3_9 const1_0_ ( +sb_2__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -10363,12 +10666,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2_9 ( const1 ) ; +module sb_2__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10382,7 +10685,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_2_9 const1_0_ ( +sb_2__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -10406,12 +10709,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_1_9 ( const1 ) ; +module sb_2__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10425,7 +10728,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1_9 const1_0_ ( +sb_2__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -10449,12 +10752,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0_9 ( const1 ) ; +module sb_2__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10466,12 +10769,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0_9 const1_0_ ( +sb_2__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -10485,10 +10785,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -10640,433 +10939,451 @@ wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11078,15 +11395,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11097,13 +11416,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11114,13 +11433,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11131,13 +11450,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11148,13 +11467,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11165,17 +11484,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_38 ( const1 ) ; +module sb_2__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11185,7 +11504,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_38 const1_0_ ( +sb_2__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -11197,12 +11516,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_31_1 ( const1 ) ; +module sb_2__1__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11212,7 +11531,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31_1 const1_0_ ( +sb_2__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -11224,12 +11543,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30_2 ( const1 ) ; +module sb_2__1__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11239,7 +11558,34 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30_2 const1_0_ ( +sb_2__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -11251,12 +11597,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29_2 ( const1 ) ; +module sb_2__1__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11266,7 +11612,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29_2 const1_0_ ( +sb_2__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -11278,12 +11624,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28_3 ( const1 ) ; +module sb_2__1__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11293,46 +11639,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_28_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_27_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27_3 const1_0_ ( +sb_2__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11344,13 +11663,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11361,13 +11680,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11378,13 +11697,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11395,13 +11714,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11412,17 +11731,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_26_6 ( const1 ) ; +module sb_2__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11433,38 +11752,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_26_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_25_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_25_6 const1_0_ ( +sb_2__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -11479,12 +11767,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_24_6 ( const1 ) ; +module sb_2__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11495,7 +11783,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24_6 const1_0_ ( +sb_2__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -11510,12 +11798,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23_6 ( const1 ) ; +module sb_2__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11526,7 +11814,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23_6 const1_0_ ( +sb_2__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -11541,12 +11829,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22_7 ( const1 ) ; +module sb_2__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -11557,7 +11845,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22_7 const1_0_ ( +sb_2__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -11572,7 +11860,95 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11586,74 +11962,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_21_7 ( const1 ) ; +module sb_2__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11665,7 +11984,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_21_7 const1_0_ ( +sb_2__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -11683,12 +12002,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_20_7 ( const1 ) ; +module sb_2__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11700,7 +12019,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_20_7 const1_0_ ( +sb_2__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -11718,12 +12037,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_19_7 ( const1 ) ; +module sb_2__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11735,7 +12054,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_19_7 const1_0_ ( +sb_2__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -11753,12 +12072,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18_8 ( const1 ) ; +module sb_2__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11770,10 +12089,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18_8 const1_0_ ( +sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -11785,10 +12102,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11804,17 +12123,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_17_8 ( const1 ) ; +module sb_2__1__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11831,7 +12150,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_17_8 const1_0_ ( +sb_2__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -11864,7 +12183,45 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11878,55 +12235,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_16_8 ( const1 ) ; +module sb_2__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11940,7 +12259,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_16_8 const1_0_ ( +sb_2__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -11964,12 +12283,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_15_8 ( const1 ) ; +module sb_2__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11983,7 +12302,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_15_8 const1_0_ ( +sb_2__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -12007,12 +12326,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_14_8 ( const1 ) ; +module sb_2__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12026,10 +12345,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_14_8 const1_0_ ( +sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -12047,10 +12364,107 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -12064,13 +12478,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12083,112 +12497,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13_8 ( const1 ) ; +module sb_2__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12203,7 +12522,101 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_13_8 const1_0_ ( +sb_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -12230,12 +12643,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12_8 ( const1 ) ; +module sb_2__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12250,7 +12663,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_12_8 const1_0_ ( +sb_2__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -12272,17 +12685,17 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_11_8 ( const1 ) ; +module sb_2__1__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12297,7 +12710,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11_8 const1_0_ ( +sb_2__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -12324,12 +12737,55 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10_8 ( const1 ) ; +module sb_2__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12344,7 +12800,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10_8 const1_0_ ( +sb_2__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -12371,149 +12827,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_9_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module const1_8_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_8_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module const1_7_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_7_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12528,13 +12843,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12549,17 +12864,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_6_8 ( const1 ) ; +module sb_2__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12581,7 +12896,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_8 const1_0_ ( +sb_2__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -12629,12 +12944,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_8 ( const1 ) ; +module sb_2__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12656,7 +12971,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_8 const1_0_ ( +sb_2__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -12704,7 +13019,28 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -12720,13 +13056,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12741,38 +13077,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_4_8 ( const1 ) ; +module sb_2__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12788,7 +13103,58 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_4_8 const1_0_ ( +sb_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -12818,12 +13184,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_8 ( const1 ) ; +module sb_2__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12839,7 +13205,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_3_8 const1_0_ ( +sb_2__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -12869,59 +13235,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_2_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12936,13 +13251,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12957,17 +13272,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_1_8 ( const1 ) ; +module sb_2__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12985,7 +13300,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_8 const1_0_ ( +sb_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -13017,18 +13332,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_0_8 ( const1 ) ; +module sb_2__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -13046,7 +13359,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_8 const1_0_ ( +sb_2__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -13095,7 +13408,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -13131,6 +13444,8 @@ output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -13231,71 +13546,75 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram ; wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -mux_tree_tapbuf_size10_12 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size14_1 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -13304,8 +13623,8 @@ mux_tree_tapbuf_size14_1 mux_top_track_4 ( chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -13314,429 +13633,516 @@ mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6_10 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_9 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_9 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) ) ; + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13755,8 +14161,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13774,8 +14180,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13793,8 +14199,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13812,12 +14218,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module const1_37 ( const1 ) ; +module sb_2__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13829,7 +14235,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_37 const1_0_ ( +sb_2__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -13847,12 +14253,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_28_2 ( const1 ) ; +module sb_2__0__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13864,7 +14270,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_28_2 const1_0_ ( +sb_2__0__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -13882,12 +14288,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_27_2 ( const1 ) ; +module sb_2__0__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13899,7 +14305,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_27_2 const1_0_ ( +sb_2__0__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -13917,12 +14323,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26_5 ( const1 ) ; +module sb_2__0__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13934,10 +14340,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_26_5 const1_0_ ( +sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -13949,11 +14353,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13964,15 +14370,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13988,8 +14394,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14005,8 +14411,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14022,8 +14428,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14039,8 +14445,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14056,8 +14462,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14073,8 +14479,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14090,8 +14496,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14107,8 +14513,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14124,8 +14530,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14141,8 +14547,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14158,7 +14564,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14175,8 +14581,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14192,8 +14598,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14209,8 +14615,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14226,8 +14632,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14243,8 +14649,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14260,8 +14666,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14277,8 +14683,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14294,12 +14700,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module const1_25_5 ( const1 ) ; +module sb_2__0__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14309,78 +14715,24 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_25_5 const1_0_ ( +sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_24_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_24_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module const1_23_5 ( const1 ) ; +module sb_2__0__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_23_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_22_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14389,7 +14741,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_22_6 const1_0_ ( +sb_2__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -14398,12 +14750,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21_6 ( const1 ) ; +module sb_2__0__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14413,24 +14765,24 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21_6 const1_0_ ( +sb_2__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_20_6 ( const1 ) ; +module sb_2__0__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14440,7 +14792,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20_6 const1_0_ ( +sb_2__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14452,12 +14804,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19_6 ( const1 ) ; +module sb_2__0__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14467,7 +14819,215 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19_6 const1_0_ ( +sb_2__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_2__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_2__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14479,12 +15039,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18_7 ( const1 ) ; +module sb_2__0__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14494,7 +15054,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_18_7 const1_0_ ( +sb_2__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14506,12 +15066,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17_7 ( const1 ) ; +module sb_2__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14521,7 +15081,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17_7 const1_0_ ( +sb_2__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14533,12 +15093,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16_7 ( const1 ) ; +module sb_2__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14548,7 +15108,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16_7 const1_0_ ( +sb_2__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14560,12 +15120,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15_7 ( const1 ) ; +module sb_2__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14575,7 +15135,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15_7 const1_0_ ( +sb_2__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14587,12 +15147,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14_7 ( const1 ) ; +module sb_2__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14602,7 +15162,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14_7 const1_0_ ( +sb_2__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14614,12 +15174,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_13_7 ( const1 ) ; +module sb_2__0__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14629,7 +15189,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_13_7 const1_0_ ( +sb_2__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14641,12 +15201,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12_7 ( const1 ) ; +module sb_2__0__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14656,7 +15216,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12_7 const1_0_ ( +sb_2__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -14668,170 +15228,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_11_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_10_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_10_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_9_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_9_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_8_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_8_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_7_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_7_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_6_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_6_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14847,7 +15245,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14864,12 +15262,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module const1_5_7 ( const1 ) ; +module sb_2__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14880,7 +15278,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_5_7 const1_0_ ( +sb_2__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -14895,12 +15293,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_4_7 ( const1 ) ; +module sb_2__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14911,7 +15309,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_4_7 const1_0_ ( +sb_2__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -14926,7 +15324,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14945,8 +15343,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14964,12 +15362,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module const1_3_7 ( const1 ) ; +module sb_2__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14982,7 +15380,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3_7 const1_0_ ( +sb_2__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -15003,12 +15401,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2_7 ( const1 ) ; +module sb_2__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15021,7 +15419,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2_7 const1_0_ ( +sb_2__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -15042,7 +15440,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15061,8 +15459,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15080,12 +15478,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module const1_1_7 ( const1 ) ; +module sb_2__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15099,7 +15497,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1_7 const1_0_ ( +sb_2__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -15123,12 +15521,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0_7 ( const1 ) ; +module sb_2__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15142,8 +15540,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0_7 const1_0_ ( +sb_2__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -15161,8 +15561,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -15287,395 +15685,454 @@ wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_8 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15689,19 +16146,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_36 ( const1 ) ; +module sb_1__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15715,7 +16172,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_36 const1_0_ ( +sb_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -15739,7 +16196,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15751,17 +16208,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_26_4 ( const1 ) ; +module sb_1__2__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -15771,19 +16228,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_26_4 const1_0_ ( +sb_1__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15795,13 +16252,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15812,13 +16269,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15829,13 +16286,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15846,13 +16303,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15863,13 +16320,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15880,17 +16337,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_25_4 ( const1 ) ; +module sb_1__2__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -15901,7 +16358,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_25_4 const1_0_ ( +sb_1__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -15911,17 +16368,17 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_24_4 ( const1 ) ; +module sb_1__2__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -15932,7 +16389,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24_4 const1_0_ ( +sb_1__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -15947,12 +16404,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23_4 ( const1 ) ; +module sb_1__2__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -15963,7 +16420,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23_4 const1_0_ ( +sb_1__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -15978,12 +16435,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22_5 ( const1 ) ; +module sb_1__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -15994,7 +16451,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22_5 const1_0_ ( +sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -16009,12 +16466,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_21_5 ( const1 ) ; +module sb_1__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -16025,7 +16482,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_21_5 const1_0_ ( +sb_1__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -16040,12 +16497,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_20_5 ( const1 ) ; +module sb_1__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -16056,7 +16513,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_20_5 const1_0_ ( +sb_1__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -16071,7 +16528,45 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16085,55 +16580,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_19_5 ( const1 ) ; +module sb_1__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16145,7 +16602,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_19_5 const1_0_ ( +sb_1__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -16163,12 +16620,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18_6 ( const1 ) ; +module sb_1__2__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16180,7 +16637,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18_6 const1_0_ ( +sb_1__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -16198,12 +16655,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17_6 ( const1 ) ; +module sb_1__2__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16215,7 +16672,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17_6 const1_0_ ( +sb_1__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -16233,7 +16690,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16247,17 +16704,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_16_6 ( const1 ) ; +module sb_1__2__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16270,7 +16727,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_16_6 const1_0_ ( +sb_1__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -16291,7 +16748,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16305,13 +16876,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16324,131 +16895,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_15_6 ( const1 ) ; +module sb_1__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16463,54 +16920,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_15_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_14_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_14_6 const1_0_ ( +sb_1__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16537,12 +16947,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_13_6 ( const1 ) ; +module sb_1__2__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16557,7 +16967,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_13_6 const1_0_ ( +sb_1__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16584,12 +16994,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12_6 ( const1 ) ; +module sb_1__2__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16604,7 +17014,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_12_6 const1_0_ ( +sb_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16631,12 +17041,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_11_6 ( const1 ) ; +module sb_1__2__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16649,9 +17059,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11_6 const1_0_ ( +sb_1__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -16671,19 +17080,16 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module const1_10_6 ( const1 ) ; +module sb_1__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16698,7 +17104,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10_6 const1_0_ ( +sb_1__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16725,12 +17131,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9_6 ( const1 ) ; +module sb_1__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16745,7 +17151,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9_6 const1_0_ ( +sb_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16772,12 +17178,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8_6 ( const1 ) ; +module sb_1__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16792,7 +17198,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_8_6 const1_0_ ( +sb_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -16819,7 +17225,75 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16835,38 +17309,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7_6 ( const1 ) ; +module sb_1__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -16882,7 +17335,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_7_6 const1_0_ ( +sb_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -16912,12 +17365,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_6 ( const1 ) ; +module sb_1__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -16933,7 +17386,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_6_6 const1_0_ ( +sb_1__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -16963,8 +17416,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16979,13 +17432,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17000,17 +17453,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_5_6 ( const1 ) ; +module sb_1__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17032,7 +17485,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_6 const1_0_ ( +sb_1__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -17080,12 +17533,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_6 ( const1 ) ; +module sb_1__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17107,7 +17560,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_6 const1_0_ ( +sb_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -17155,7 +17608,49 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17171,59 +17666,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_3_6 ( const1 ) ; +module sb_1__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17240,7 +17693,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_3_6 const1_0_ ( +sb_1__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -17273,63 +17726,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_6 ( const1 ) ; +module sb_1__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_2_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17346,7 +17748,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_1_6 const1_0_ ( +sb_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -17379,8 +17781,63 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17395,17 +17852,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_0_6 ( const1 ) ; +module sb_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17423,7 +17880,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_6 const1_0_ ( +sb_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -17474,7 +17931,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -17514,6 +17973,8 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -17601,7 +18062,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_11 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -17609,52 +18070,55 @@ mux_tree_tapbuf_size10_11 mux_right_track_0 ( chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -17664,8 +18128,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -17674,439 +18138,531 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_8 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18120,76 +18676,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_35 ( const1 ) ; +module sb_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18204,7 +18701,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_35 const1_0_ ( +sb_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -18231,12 +18728,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26_3 ( const1 ) ; +module sb_1__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18251,7 +18748,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_26_3 const1_0_ ( +sb_1__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -18278,12 +18775,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_25_3 ( const1 ) ; +module sb_1__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18298,7 +18795,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_25_3 const1_0_ ( +sb_1__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -18325,12 +18822,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_24_3 ( const1 ) ; +module sb_1__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18343,12 +18840,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_24_3 const1_0_ ( +sb_1__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -18365,15 +18859,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18388,13 +18881,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18409,13 +18902,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18430,13 +18923,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18451,13 +18944,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18472,13 +18965,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18493,13 +18986,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18514,13 +19007,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18535,13 +19028,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18556,13 +19049,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18577,13 +19070,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18598,13 +19091,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18619,17 +19112,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_23_3 ( const1 ) ; +module sb_1__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18647,7 +19140,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_23_3 const1_0_ ( +sb_1__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18683,12 +19176,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_22_4 ( const1 ) ; +module sb_1__1__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18706,7 +19199,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22_4 const1_0_ ( +sb_1__1__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18742,12 +19235,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_21_4 ( const1 ) ; +module sb_1__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18765,7 +19258,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_21_4 const1_0_ ( +sb_1__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18801,12 +19294,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_20_4 ( const1 ) ; +module sb_1__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18824,7 +19317,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_20_4 const1_0_ ( +sb_1__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18860,12 +19353,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_19_4 ( const1 ) ; +module sb_1__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18883,7 +19376,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_19_4 const1_0_ ( +sb_1__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18919,12 +19412,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_18_5 ( const1 ) ; +module sb_1__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18942,7 +19435,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_18_5 const1_0_ ( +sb_1__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -18978,12 +19471,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_17_5 ( const1 ) ; +module sb_1__1__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19001,7 +19494,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_17_5 const1_0_ ( +sb_1__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19037,12 +19530,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_16_5 ( const1 ) ; +module sb_1__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19060,7 +19553,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_16_5 const1_0_ ( +sb_1__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19096,12 +19589,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15_5 ( const1 ) ; +module sb_1__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19119,7 +19612,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_15_5 const1_0_ ( +sb_1__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19155,12 +19648,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14_5 ( const1 ) ; +module sb_1__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19178,7 +19671,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_14_5 const1_0_ ( +sb_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19214,12 +19707,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13_5 ( const1 ) ; +module sb_1__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19237,7 +19730,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_13_5 const1_0_ ( +sb_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19273,12 +19766,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_12_5 ( const1 ) ; +module sb_1__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19296,7 +19789,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_12_5 const1_0_ ( +sb_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -19332,8 +19825,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19350,13 +19843,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19373,13 +19866,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19396,13 +19889,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19419,17 +19912,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_11_5 ( const1 ) ; +module sb_1__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -19453,7 +19946,173 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_11_5 const1_0_ ( +sb_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; @@ -19507,91 +20166,12 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module const1_10_5 ( const1 ) ; +module sb_1__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_10_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_9_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -19615,10 +20195,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_9_5 const1_0_ ( +sb_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -19666,94 +20244,13 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module const1_8_5 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_8_5 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19768,13 +20265,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19789,13 +20286,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19810,13 +20307,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19831,13 +20328,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19852,13 +20349,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19873,13 +20370,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19894,13 +20391,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19915,17 +20412,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_7_5 ( const1 ) ; +module sb_1__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19945,7 +20442,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7_5 const1_0_ ( +sb_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -19987,12 +20484,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6_5 ( const1 ) ; +module sb_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20012,7 +20509,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6_5 const1_0_ ( +sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20054,12 +20551,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5_5 ( const1 ) ; +module sb_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20079,7 +20576,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5_5 const1_0_ ( +sb_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20121,12 +20618,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4_5 ( const1 ) ; +module sb_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20146,7 +20643,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4_5 const1_0_ ( +sb_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20188,12 +20685,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3_5 ( const1 ) ; +module sb_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20213,7 +20710,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3_5 const1_0_ ( +sb_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20255,12 +20752,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2_5 ( const1 ) ; +module sb_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20280,7 +20777,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2_5 const1_0_ ( +sb_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20322,12 +20819,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_5 ( const1 ) ; +module sb_1__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20347,7 +20844,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1_5 const1_0_ ( +sb_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20389,12 +20886,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0_5 ( const1 ) ; +module sb_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20414,7 +20911,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0_5 const1_0_ ( +sb_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -20472,7 +20969,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail ) ; + chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -20516,6 +21016,11 @@ output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -20601,7 +21106,7 @@ wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -20609,8 +21114,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -20618,8 +21123,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -20627,8 +21132,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -20636,8 +21141,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -20645,8 +21150,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -20654,8 +21159,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -20663,8 +21168,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -20672,48 +21177,54 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -20722,9 +21233,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -20734,8 +21246,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -20744,9 +21256,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -20755,358 +21268,534 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; + .X ( ropt_net_168 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21120,38 +21809,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_34 ( const1 ) ; +module sb_1__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21164,7 +21832,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_34 const1_0_ ( +sb_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -21185,12 +21853,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26_2 ( const1 ) ; +module sb_1__0__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21203,7 +21871,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_26_2 const1_0_ ( +sb_1__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -21224,7 +21892,26 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21238,36 +21925,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_25_2 ( const1 ) ; +module sb_1__0__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21279,9 +21947,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_25_2 const1_0_ ( +sb_1__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21295,18 +21966,19 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module const1_24_2 ( const1 ) ; +module sb_1__0__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21318,9 +21990,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_24_2 const1_0_ ( +sb_1__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21334,14 +22009,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21356,13 +22032,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21377,17 +22053,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_23_2 ( const1 ) ; +module sb_1__0__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -21406,7 +22082,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_23_2 const1_0_ ( +sb_1__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; @@ -21445,12 +22121,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_22_3 ( const1 ) ; +module sb_1__0__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -21469,10 +22145,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22_3 const1_0_ ( +sb_1__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21505,10 +22179,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21520,17 +22196,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_21_3 ( const1 ) ; +module sb_1__0__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21540,7 +22216,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21_3 const1_0_ ( +sb_1__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -21552,7 +22228,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21564,13 +22240,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21581,13 +22257,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21598,13 +22274,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21615,13 +22291,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21632,13 +22308,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21649,13 +22325,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21666,17 +22342,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_20_3 ( const1 ) ; +module sb_1__0__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21687,7 +22363,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_20_3 const1_0_ ( +sb_1__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21702,12 +22378,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_19_3 ( const1 ) ; +module sb_1__0__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21718,7 +22394,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_19_3 const1_0_ ( +sb_1__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21733,12 +22409,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_18_4 ( const1 ) ; +module sb_1__0__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21749,7 +22425,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_18_4 const1_0_ ( +sb_1__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21764,12 +22440,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_17_4 ( const1 ) ; +module sb_1__0__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21780,7 +22456,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_17_4 const1_0_ ( +sb_1__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21795,12 +22471,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_16_4 ( const1 ) ; +module sb_1__0__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21811,7 +22487,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_16_4 const1_0_ ( +sb_1__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21826,12 +22502,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_15_4 ( const1 ) ; +module sb_1__0__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21842,7 +22518,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_15_4 const1_0_ ( +sb_1__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21857,12 +22533,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_14_4 ( const1 ) ; +module sb_1__0__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21873,7 +22549,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_14_4 const1_0_ ( +sb_1__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -21888,7 +22564,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21902,36 +22597,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13_4 ( const1 ) ; +module sb_1__0__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21943,7 +22619,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_13_4 const1_0_ ( +sb_1__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -21961,12 +22637,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12_4 ( const1 ) ; +module sb_1__0__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21978,7 +22654,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_12_4 const1_0_ ( +sb_1__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -21996,7 +22672,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22010,13 +22800,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22029,13 +22819,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22048,131 +22838,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_11_4 ( const1 ) ; +module sb_1__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22187,7 +22863,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11_4 const1_0_ ( +sb_1__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22214,12 +22890,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10_4 ( const1 ) ; +module sb_1__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22234,7 +22910,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10_4 const1_0_ ( +sb_1__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22261,12 +22937,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9_4 ( const1 ) ; +module sb_1__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22281,7 +22957,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9_4 const1_0_ ( +sb_1__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22308,12 +22984,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8_4 ( const1 ) ; +module sb_1__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22328,7 +23004,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_8_4 const1_0_ ( +sb_1__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22355,12 +23031,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_7_4 ( const1 ) ; +module sb_1__0__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22375,7 +23051,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_7_4 const1_0_ ( +sb_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22402,12 +23078,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_6_4 ( const1 ) ; +module sb_1__0__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22422,7 +23098,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_6_4 const1_0_ ( +sb_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22449,12 +23125,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5_4 ( const1 ) ; +module sb_1__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22469,7 +23145,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_5_4 const1_0_ ( +sb_1__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22496,12 +23172,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4_4 ( const1 ) ; +module sb_1__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22516,7 +23192,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_4_4 const1_0_ ( +sb_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22543,12 +23219,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_3_4 ( const1 ) ; +module sb_1__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22563,7 +23239,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_3_4 const1_0_ ( +sb_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -22590,7 +23266,49 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22606,59 +23324,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_2_4 ( const1 ) ; +module sb_1__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -22674,7 +23350,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_2_4 const1_0_ ( +sb_1__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -22704,12 +23380,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1_4 ( const1 ) ; +module sb_1__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -22725,7 +23401,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_1_4 const1_0_ ( +sb_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -22755,12 +23431,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0_4 ( const1 ) ; +module sb_1__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -22776,7 +23452,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_0_4 const1_0_ ( +sb_1__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -22817,7 +23493,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -22851,6 +23531,16 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -22937,271 +23627,292 @@ wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; -mux_tree_tapbuf_size4_6 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -23209,204 +23920,261 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23417,15 +24185,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23441,8 +24211,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23458,8 +24228,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23475,7 +24245,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23492,8 +24262,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23509,8 +24279,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23526,8 +24296,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23543,8 +24313,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23560,8 +24330,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23577,8 +24347,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23594,8 +24364,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23611,8 +24381,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23628,8 +24398,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23645,8 +24415,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23662,8 +24432,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23679,8 +24449,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23696,8 +24466,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23713,12 +24483,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module const1_33 ( const1 ) ; +module sb_0__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23728,7 +24498,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_33 const1_0_ ( +sb_0__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23740,12 +24510,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22_2 ( const1 ) ; +module sb_0__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23755,7 +24525,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22_2 const1_0_ ( +sb_0__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23767,12 +24537,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21_2 ( const1 ) ; +module sb_0__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23782,7 +24552,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21_2 const1_0_ ( +sb_0__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23794,12 +24564,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20_2 ( const1 ) ; +module sb_0__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23809,7 +24579,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20_2 const1_0_ ( +sb_0__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23821,12 +24591,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19_2 ( const1 ) ; +module sb_0__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23836,7 +24629,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19_2 const1_0_ ( +sb_0__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23848,12 +24641,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18_3 ( const1 ) ; +module sb_0__2__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23863,7 +24656,34 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_18_3 const1_0_ ( +sb_0__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23875,12 +24695,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17_3 ( const1 ) ; +module sb_0__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23890,7 +24710,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17_3 const1_0_ ( +sb_0__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23902,12 +24722,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16_3 ( const1 ) ; +module sb_0__2__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23917,7 +24737,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16_3 const1_0_ ( +sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23929,12 +24749,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15_3 ( const1 ) ; +module sb_0__2__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23944,7 +24764,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15_3 const1_0_ ( +sb_0__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23956,12 +24776,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14_3 ( const1 ) ; +module sb_0__2__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23971,7 +24791,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14_3 const1_0_ ( +sb_0__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -23983,12 +24803,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_13_3 ( const1 ) ; +module sb_0__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23998,7 +24818,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_13_3 const1_0_ ( +sb_0__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24010,12 +24830,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12_3 ( const1 ) ; +module sb_0__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24025,7 +24845,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12_3 const1_0_ ( +sb_0__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24037,12 +24857,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11_3 ( const1 ) ; +module sb_0__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24052,7 +24872,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_11_3 const1_0_ ( +sb_0__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24064,12 +24884,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_10_3 ( const1 ) ; +module sb_0__2__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24079,7 +24899,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_10_3 const1_0_ ( +sb_0__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24091,12 +24911,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_9_3 ( const1 ) ; +module sb_0__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24106,7 +24926,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_9_3 const1_0_ ( +sb_0__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24118,12 +24938,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_8_3 ( const1 ) ; +module sb_0__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24133,36 +24953,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_8_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) ) ; -endmodule - - -module const1_7_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_7_3 const1_0_ ( +sb_0__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -24174,35 +24965,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_6_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24218,7 +24982,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24235,12 +24999,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module const1_5_3 ( const1 ) ; +module sb_0__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24251,7 +25015,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_5_3 const1_0_ ( +sb_0__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -24266,12 +25030,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_4_3 ( const1 ) ; +module sb_0__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24282,7 +25046,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_4_3 const1_0_ ( +sb_0__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -24297,7 +25061,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24316,8 +25080,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24335,12 +25099,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module const1_3_3 ( const1 ) ; +module sb_0__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24353,7 +25117,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3_3 const1_0_ ( +sb_0__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -24374,12 +25138,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2_3 ( const1 ) ; +module sb_0__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24392,7 +25156,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2_3 const1_0_ ( +sb_0__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -24413,7 +25177,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24432,8 +25196,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24451,12 +25215,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module const1_1_3 ( const1 ) ; +module sb_0__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24470,7 +25234,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1_3 const1_0_ ( +sb_0__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -24494,12 +25258,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0_3 ( const1 ) ; +module sb_0__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24513,7 +25277,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0_3 const1_0_ ( +sb_0__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -24640,334 +25404,383 @@ wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24984,8 +25797,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25001,8 +25814,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25018,8 +25831,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25035,8 +25848,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25052,8 +25865,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25069,12 +25882,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module const1_32 ( const1 ) ; +module sb_0__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25084,7 +25897,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_32 const1_0_ ( +sb_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -25096,12 +25909,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_31 ( const1 ) ; +module sb_0__1__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25111,7 +25924,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31 const1_0_ ( +sb_0__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -25123,12 +25936,58 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30_1 ( const1 ) ; +module sb_0__1__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25138,7 +25997,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30_1 const1_0_ ( +sb_0__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -25150,12 +26009,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29_1 ( const1 ) ; +module sb_0__1__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25165,7 +26024,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29_1 const1_0_ ( +sb_0__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -25177,62 +26036,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_28_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_27_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25244,13 +26049,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25267,8 +26072,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25284,8 +26089,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25301,8 +26106,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25318,12 +26123,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module const1_26_1 ( const1 ) ; +module sb_0__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25334,7 +26139,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_26_1 const1_0_ ( +sb_0__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -25349,12 +26154,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_25_1 ( const1 ) ; +module sb_0__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25365,7 +26170,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_25_1 const1_0_ ( +sb_0__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -25380,12 +26185,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_24_1 ( const1 ) ; +module sb_0__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25396,7 +26201,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24_1 const1_0_ ( +sb_0__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -25411,12 +26216,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23_1 ( const1 ) ; +module sb_0__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25427,7 +26232,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23_1 const1_0_ ( +sb_0__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -25442,12 +26247,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22_1 ( const1 ) ; +module sb_0__1__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25458,7 +26263,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22_1 const1_0_ ( +sb_0__1__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -25473,7 +26278,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25492,8 +26297,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25511,8 +26316,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25530,12 +26335,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module const1_21_1 ( const1 ) ; +module sb_0__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25550,7 +26355,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_21_1 const1_0_ ( +sb_0__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -25577,12 +26382,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_20_1 ( const1 ) ; +module sb_0__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25597,7 +26402,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_20_1 const1_0_ ( +sb_0__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -25624,12 +26429,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_19_1 ( const1 ) ; +module sb_0__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25644,7 +26449,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_19_1 const1_0_ ( +sb_0__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -25671,8 +26476,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25690,8 +26495,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25709,8 +26514,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25728,8 +26533,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25747,8 +26552,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25766,7 +26571,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25785,8 +26590,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25804,12 +26609,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module const1_18_2 ( const1 ) ; +module sb_0__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25821,7 +26626,42 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18_2 const1_0_ ( +sb_0__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -25839,12 +26679,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17_2 ( const1 ) ; +module sb_0__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25856,7 +26696,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17_2 const1_0_ ( +sb_0__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -25874,12 +26714,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_16_2 ( const1 ) ; +module sb_0__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25891,42 +26731,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_16_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_15_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_15_2 const1_0_ ( +sb_0__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -25944,12 +26749,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_14_2 ( const1 ) ; +module sb_0__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25961,7 +26766,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_14_2 const1_0_ ( +sb_0__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -25979,12 +26784,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_13_2 ( const1 ) ; +module sb_0__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25996,7 +26801,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_13_2 const1_0_ ( +sb_0__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -26014,12 +26819,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12_2 ( const1 ) ; +module sb_0__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26031,7 +26836,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_12_2 const1_0_ ( +sb_0__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -26049,8 +26854,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26068,8 +26873,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26087,8 +26892,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26106,8 +26911,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26125,7 +26930,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26144,12 +26949,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module const1_11_2 ( const1 ) ; +module sb_0__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26162,7 +26967,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_11_2 const1_0_ ( +sb_0__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -26183,12 +26988,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10_2 ( const1 ) ; +module sb_0__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26201,7 +27006,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_10_2 const1_0_ ( +sb_0__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -26222,12 +27027,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9_2 ( const1 ) ; +module sb_0__1__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26240,7 +27045,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_9_2 const1_0_ ( +sb_0__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -26261,12 +27066,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8_2 ( const1 ) ; +module sb_0__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26279,7 +27084,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_8_2 const1_0_ ( +sb_0__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -26300,12 +27105,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_7_2 ( const1 ) ; +module sb_0__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26318,7 +27123,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_7_2 const1_0_ ( +sb_0__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -26339,8 +27144,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26358,8 +27163,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26377,8 +27182,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26396,8 +27201,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26415,7 +27220,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26434,8 +27239,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26453,8 +27258,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26472,12 +27277,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module const1_6_2 ( const1 ) ; +module sb_0__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26491,7 +27296,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_6_2 const1_0_ ( +sb_0__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26515,12 +27320,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5_2 ( const1 ) ; +module sb_0__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26534,7 +27339,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_5_2 const1_0_ ( +sb_0__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26558,12 +27363,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4_2 ( const1 ) ; +module sb_0__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26577,7 +27382,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_4_2 const1_0_ ( +sb_0__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26601,12 +27406,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_3_2 ( const1 ) ; +module sb_0__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26620,7 +27425,52 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_3_2 const1_0_ ( +sb_0__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26644,12 +27494,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2_2 ( const1 ) ; +module sb_0__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26663,7 +27513,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_2_2 const1_0_ ( +sb_0__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26687,12 +27537,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_1_2 ( const1 ) ; +module sb_0__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26706,50 +27556,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_0_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_0_2 const1_0_ ( +sb_0__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -26779,7 +27586,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -26799,6 +27606,7 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -26899,471 +27707,547 @@ wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_3 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -27382,8 +28266,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27401,8 +28285,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27420,8 +28304,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27439,12 +28323,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module const1_31 ( const1 ) ; +module sb_0__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -27456,7 +28340,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_31 const1_0_ ( +sb_0__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -27474,12 +28358,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18_1 ( const1 ) ; +module sb_0__0__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -27491,7 +28375,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18_1 const1_0_ ( +sb_0__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -27509,12 +28393,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17_1 ( const1 ) ; +module sb_0__0__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -27526,42 +28410,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_16_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_16_1 const1_0_ ( +sb_0__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -27579,8 +28428,39 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27593,13 +28473,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27615,8 +28495,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27632,8 +28512,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27649,8 +28529,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27666,8 +28546,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27683,8 +28563,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27700,8 +28580,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27717,8 +28597,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27734,8 +28614,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27751,8 +28631,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27768,8 +28648,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27785,8 +28665,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27802,7 +28682,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -27819,8 +28699,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27836,8 +28716,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27853,12 +28733,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module const1_15_1 ( const1 ) ; +module sb_0__0__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -27868,7 +28748,88 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15_1 const1_0_ ( +sb_0__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -27880,12 +28841,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14_1 ( const1 ) ; +module sb_0__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -27895,34 +28856,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_13_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13_1 const1_0_ ( +sb_0__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -27934,12 +28868,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12_1 ( const1 ) ; +module sb_0__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -27949,7 +28883,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12_1 const1_0_ ( +sb_0__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -27961,12 +28895,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11_1 ( const1 ) ; +module sb_0__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -27976,7 +28910,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_11_1 const1_0_ ( +sb_0__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -27988,12 +28922,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_10_1 ( const1 ) ; +module sb_0__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28003,7 +28937,61 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_10_1 const1_0_ ( +sb_0__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28015,12 +29003,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_9_1 ( const1 ) ; +module sb_0__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28030,7 +29018,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_9_1 const1_0_ ( +sb_0__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28042,12 +29030,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_8_1 ( const1 ) ; +module sb_0__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28057,7 +29045,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_8_1 const1_0_ ( +sb_0__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28069,12 +29057,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_7_1 ( const1 ) ; +module sb_0__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28084,7 +29072,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_7_1 const1_0_ ( +sb_0__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28096,12 +29084,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6_1 ( const1 ) ; +module sb_0__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28111,7 +29099,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_6_1 const1_0_ ( +sb_0__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28123,12 +29111,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_5_1 ( const1 ) ; +module sb_0__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28138,7 +29126,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_5_1 const1_0_ ( +sb_0__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28150,12 +29138,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_4_1 ( const1 ) ; +module sb_0__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -28165,115 +29153,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_4_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_3_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_3_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_2_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_2_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_0_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_0_1 const1_0_ ( +sb_0__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -28365,309 +29245,410 @@ wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , .X ( chanx_right_out[18] ) ) ; endmodule -module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_direct_interc_17 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_16 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_15 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_14 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_13 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_12 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_11 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_10 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_9 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_8 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28678,15 +29659,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28697,13 +29676,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28714,85 +29693,90 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module grid_clb_const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1 const1_0_ ( +grid_clb_const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_30 ( const1 ) ; +module grid_clb_const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_30 const1_0_ ( +grid_clb_const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , + .X ( p_abuf0 ) ) ; endmodule -module const1_29 ( const1 ) ; +module grid_clb_const1_29 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_29 const1_0_ ( +grid_clb_const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , p_abuf2 ) ; input [0:0] Test_en ; @@ -28808,16 +29792,16 @@ output p_abuf2 ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -28832,8 +29816,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28844,36 +29828,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_28 ( const1 ) ; +module grid_clb_const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_28 const1_0_ ( +grid_clb_const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28914,12 +29898,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -28955,7 +29939,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -29009,8 +29993,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -29042,14 +30026,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -29059,7 +30043,7 @@ frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -29073,11 +30057,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -29098,14 +30083,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29113,7 +30098,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -29122,40 +30107,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , - p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29173,8 +30158,7 @@ output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; -input p1 ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29191,103 +30175,103 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign p_abuf1 = p_abuf2 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( fabric_regout[0] ) , .p_abuf2 ( p_abuf2 ) ) ; -mux_tree_size2_21 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; -mux_tree_size2_22 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; -mux_tree_size2_23 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , - p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p_abuf4 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29303,10 +30287,11 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p1 ; -input p2 ; +output p_abuf3 ; +output p_abuf4 ; +input p0 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , @@ -29314,45 +30299,51 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_d .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc_8 direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_3_ ( + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_direct_interc_7 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29363,13 +30354,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29380,13 +30371,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29397,81 +30388,89 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_27 ( const1 ) ; +module grid_clb_const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_27 const1_0_ ( +grid_clb_const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_26 ( const1 ) ; +module grid_clb_const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_26 const1_0_ ( +grid_clb_const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module const1_25 ( const1 ) ; +module grid_clb_const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_25 const1_0_ ( +grid_clb_const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -29486,7 +30485,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -29501,8 +30500,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29513,36 +30512,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_24 ( const1 ) ; +module grid_clb_const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_24 const1_0_ ( +grid_clb_const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29583,12 +30582,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29621,10 +30620,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -29678,8 +30677,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -29709,16 +30708,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -29728,7 +30727,7 @@ frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -29742,11 +30741,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -29767,14 +30767,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29782,7 +30782,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -29791,39 +30791,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_30 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29836,7 +30837,10 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29853,100 +30857,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_18 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_19 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_20 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29959,53 +30963,69 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_direct_interc_7 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_direct_interc_6 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30016,13 +31036,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30033,13 +31053,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30050,81 +31070,87 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_23 ( const1 ) ; +module grid_clb_const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_23 const1_0_ ( +grid_clb_const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_22 ( const1 ) ; +module grid_clb_const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_22 const1_0_ ( +grid_clb_const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module const1_21 ( const1 ) ; +module grid_clb_const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_21 const1_0_ ( +grid_clb_const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30139,7 +31165,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30154,8 +31180,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30166,36 +31192,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_20 ( const1 ) ; +module grid_clb_const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_20 const1_0_ ( +grid_clb_const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30236,12 +31262,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30270,670 +31296,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; - -frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_29 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , - p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input p0 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_15 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_17 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input p0 ; -input p2 ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_19 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_19 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_18 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_18 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_17 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -output [0:16] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( @@ -30987,8 +31357,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -31027,7 +31397,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -31037,7 +31407,7 @@ frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -31051,11 +31421,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -31076,14 +31447,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -31091,7 +31462,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -31100,39 +31471,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_28 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31145,7 +31517,9 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -31162,100 +31536,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_12 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_13 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_14 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31268,53 +31642,62 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p3 ( p3 ) ) ; +grid_clb_direct_interc_5 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc_6 direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( + .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31325,13 +31708,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31342,13 +31725,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31359,81 +31742,89 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_15 ( const1 ) ; +module grid_clb_const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_15 const1_0_ ( +grid_clb_const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_14 ( const1 ) ; +module grid_clb_const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_14 const1_0_ ( +grid_clb_const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module const1_13 ( const1 ) ; +module grid_clb_const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_13 const1_0_ ( +grid_clb_const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -31448,7 +31839,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -31463,8 +31854,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31475,36 +31866,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_12 ( const1 ) ; +module grid_clb_const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_27 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_12 const1_0_ ( +grid_clb_const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31544,13 +31935,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -31640,8 +32031,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -31671,16 +32062,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -31690,7 +32081,7 @@ frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -31704,11 +32095,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -31729,14 +32121,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -31744,7 +32136,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -31753,39 +32145,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_27 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31798,7 +32191,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -31815,100 +32212,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_9 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_10 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_11 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31921,53 +32319,64 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc_4 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31978,13 +32387,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -31995,13 +32404,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -32012,81 +32421,89 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_11 ( const1 ) ; +module grid_clb_const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_11 const1_0_ ( +grid_clb_const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_10 ( const1 ) ; +module grid_clb_const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +output p_abuf0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_10 const1_0_ ( +grid_clb_const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module const1_9 ( const1 ) ; +module grid_clb_const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_9 const1_0_ ( +grid_clb_const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -32101,7 +32518,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -32116,8 +32533,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -32128,36 +32545,711 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8 ( const1 ) ; +module grid_clb_const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_8 const1_0_ ( +grid_clb_const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_sc_out ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_sc_out[0] ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_sc_out ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_sc_in ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_sc_in ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_sc_out ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc_3 direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module grid_clb_direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -32198,12 +33290,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -32230,7 +33322,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; @@ -32293,8 +33385,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -32330,10 +33422,10 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -32343,7 +33435,7 @@ frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -32357,11 +33449,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -32382,14 +33475,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -32397,7 +33490,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -32406,40 +33499,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_26 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p1 , - p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32452,8 +33545,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -32470,100 +33566,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_6 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_7 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_8 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; -mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p1 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -32576,155 +33673,125 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc_2 direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_5 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module grid_clb_direct_interc_1 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_size2_4 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; +module grid_clb_direct_interc_0 ( in , out ) ; +input [0:0] in ; output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_5 ( const1 ) ; +module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -32733,7 +33800,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_5 const1_0_ ( +grid_clb_const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -32742,7 +33809,57 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( +module grid_clb_const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_const1_5 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +grid_clb_const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -32757,7 +33874,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -32772,8 +33889,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -32784,17 +33901,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_4 ( const1 ) ; +module grid_clb_const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -32803,7 +33920,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_4 const1_0_ ( +grid_clb_const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -32812,8 +33929,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -32854,12 +33971,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -32888,7 +34005,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; @@ -32949,8 +34066,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -32986,10 +34103,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -32999,7 +34116,7 @@ frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -33013,11 +34130,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -33038,7 +34156,7 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -33053,7 +34171,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -33062,7 +34180,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_25 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] @@ -33070,32 +34188,32 @@ mux_tree_size2_25 mux_frac_logic_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , - p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33108,8 +34226,10 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -33126,100 +34246,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_3 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_4 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; -mux_tree_size2_5 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; -mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33232,54 +34352,57 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_direct_interc_1 direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( + .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33290,13 +34413,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33307,13 +34430,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33324,84 +34447,88 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_3 ( const1 ) ; +module grid_clb_const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_3 const1_0_ ( +grid_clb_const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module const1_2 ( const1 ) ; +module grid_clb_const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_2 const1_0_ ( +grid_clb_const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule -module const1_1 ( const1 ) ; +module grid_clb_const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_1 const1_0_ ( +grid_clb_const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -33416,7 +34543,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -33431,7 +34558,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module direct_interc ( in , out ) ; +module grid_clb_direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -33439,8 +34566,8 @@ assign out[0] = in[0] ; endmodule -module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33451,36 +34578,36 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_0 ( const1 ) ; +module grid_clb_const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_0 const1_0_ ( +grid_clb_const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33521,12 +34648,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -33562,7 +34689,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -33616,8 +34743,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -33649,14 +34776,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -33666,7 +34793,7 @@ frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -33680,11 +34807,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -33705,14 +34833,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -33720,7 +34848,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -33729,39 +34857,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_24 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33774,7 +34903,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -33791,100 +34924,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_0 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_1 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_2 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , + p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33897,59 +35031,64 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule -module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , - clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , - clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , - clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf4 , - p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , - p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , - p4 ) ; +module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , + clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , + p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , p_abuf18 , + p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , p_abuf30 , + p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -33979,24 +35118,27 @@ output [0:0] clb_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf3 ; -output p_abuf4 ; output p_abuf5 ; output p_abuf6 ; -output p_abuf7 ; output p_abuf8 ; -output p_abuf9 ; output p_abuf10 ; -output p_abuf11 ; output p_abuf12 ; -output p_abuf13 ; output p_abuf14 ; -output p_abuf15 ; output p_abuf16 ; +output p_abuf18 ; +output p_abuf20 ; +output p_abuf22 ; +output p_abuf24 ; +output p_abuf26 ; +output p_abuf28 ; +output p_abuf30 ; +output p_abuf31 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; +input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -34008,11 +35150,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; @@ -34022,65 +35162,69 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; -logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { p_abuf16 , p_abuf3 } ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , + .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { p_abuf4 , clb_O[2] } ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p0 ( p0 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .p_abuf0 ( p_abuf6 ) , .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { p_abuf6 , p_abuf7 } ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p1 ( p2 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , + .p0 ( p0 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .p_abuf0 ( p_abuf14 ) , .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , + .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .p_abuf0 ( p_abuf18 ) , .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , + .p2 ( p3 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , @@ -34091,20 +35235,21 @@ logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p0 ( p1 ) , .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .p_abuf0 ( p_abuf22 ) , .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { p_abuf14 , p_abuf15 } ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .p_abuf0 ( p_abuf26 ) , .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , + .p0 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , @@ -34114,287 +35259,230 @@ logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , + .p0 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf5 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf16 } ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( clb_O[2] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc_9 direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_4 } ) ) ; +grid_clb_direct_interc_10 direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf7 } ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf6 } ) ) ; -direct_interc direct_interc_6_ ( + .out ( { SYNOPSYS_UNCONNECTED_6 } ) ) ; +grid_clb_direct_interc_11 direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( clb_O[6] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; -direct_interc direct_interc_8_ ( + .out ( { SYNOPSYS_UNCONNECTED_8 } ) ) ; +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; -direct_interc direct_interc_9_ ( + .out ( { p_abuf11 } ) ) ; +grid_clb_direct_interc_12 direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( clb_O[9] ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( clb_O[10] ) ) ; -direct_interc direct_interc_11_ ( + .out ( { SYNOPSYS_UNCONNECTED_11 } ) ) ; +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( clb_O[11] ) ) ; -direct_interc direct_interc_12_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( { p_abuf15 } ) ) ; -direct_interc direct_interc_13_ ( +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( { p_abuf21 } ) ) ; +grid_clb_direct_interc_13 direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( { p_abuf14 } ) ) ; -direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , - .out ( clb_O[14] ) ) ; -direct_interc direct_interc_15_ ( + .out ( { SYNOPSYS_UNCONNECTED_15 } ) ) ; +grid_clb_direct_interc_14 direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( clb_O[15] ) ) ; -direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_17_ ( + .out ( { SYNOPSYS_UNCONNECTED_17 } ) ) ; +grid_clb_direct_interc_15 direct_interc_11_ ( .in ( { SYNOPSYS_UNCONNECTED_18 } ) , - .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , - .out ( clb_I0[2] ) ) ; -direct_interc direct_interc_19_ ( + .out ( { SYNOPSYS_UNCONNECTED_19 } ) ) ; +grid_clb_direct_interc direct_interc_12_ ( .in ( { SYNOPSYS_UNCONNECTED_20 } ) , - .out ( clb_I0[1] ) ) ; -direct_interc direct_interc_20_ ( + .out ( { p_abuf29 } ) ) ; +grid_clb_direct_interc_16 direct_interc_13_ ( .in ( { SYNOPSYS_UNCONNECTED_21 } ) , - .out ( clb_I0[0] ) ) ; -direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , - .out ( clb_I0i ) ) ; -direct_interc direct_interc_22_ ( + .out ( { SYNOPSYS_UNCONNECTED_22 } ) ) ; +grid_clb_direct_interc_17 direct_interc_14_ ( .in ( { SYNOPSYS_UNCONNECTED_23 } ) , - .out ( clb_regin ) ) ; -direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , - .out ( clb_sc_in ) ) ; -direct_interc direct_interc_24_ ( + .out ( { SYNOPSYS_UNCONNECTED_24 } ) ) ; +grid_clb_direct_interc direct_interc_15_ ( .in ( { SYNOPSYS_UNCONNECTED_25 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_25_ ( + .out ( { p_abuf30 } ) ) ; +grid_clb_direct_interc direct_interc_16_ ( .in ( { SYNOPSYS_UNCONNECTED_26 } ) , - .out ( clb_I1[2] ) ) ; -direct_interc direct_interc_26_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_17_ ( .in ( { SYNOPSYS_UNCONNECTED_27 } ) , - .out ( clb_I1[1] ) ) ; -direct_interc direct_interc_27_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_18_ ( .in ( { SYNOPSYS_UNCONNECTED_28 } ) , - .out ( clb_I1[0] ) ) ; -direct_interc direct_interc_28_ ( + .out ( clb_I0[2] ) ) ; +grid_clb_direct_interc direct_interc_19_ ( .in ( { SYNOPSYS_UNCONNECTED_29 } ) , - .out ( clb_I1i ) ) ; -direct_interc direct_interc_29_ ( + .out ( clb_I0[1] ) ) ; +grid_clb_direct_interc direct_interc_20_ ( .in ( { SYNOPSYS_UNCONNECTED_30 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -direct_interc direct_interc_30_ ( + .out ( clb_I0[0] ) ) ; +grid_clb_direct_interc direct_interc_21_ ( .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -direct_interc direct_interc_31_ ( + .out ( clb_I0i ) ) ; +grid_clb_direct_interc direct_interc_22_ ( .in ( { SYNOPSYS_UNCONNECTED_32 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_32_ ( + .out ( clb_regin ) ) ; +grid_clb_direct_interc direct_interc_23_ ( .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( clb_I2[2] ) ) ; -direct_interc direct_interc_33_ ( + .out ( clb_sc_in ) ) ; +grid_clb_direct_interc direct_interc_24_ ( .in ( { SYNOPSYS_UNCONNECTED_34 } ) , - .out ( clb_I2[1] ) ) ; -direct_interc direct_interc_34_ ( + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_25_ ( .in ( { SYNOPSYS_UNCONNECTED_35 } ) , - .out ( clb_I2[0] ) ) ; -direct_interc direct_interc_35_ ( + .out ( clb_I1[2] ) ) ; +grid_clb_direct_interc direct_interc_26_ ( .in ( { SYNOPSYS_UNCONNECTED_36 } ) , - .out ( clb_I2i ) ) ; -direct_interc direct_interc_36_ ( + .out ( clb_I1[1] ) ) ; +grid_clb_direct_interc direct_interc_27_ ( .in ( { SYNOPSYS_UNCONNECTED_37 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -direct_interc direct_interc_37_ ( + .out ( clb_I1[0] ) ) ; +grid_clb_direct_interc direct_interc_28_ ( .in ( { SYNOPSYS_UNCONNECTED_38 } ) , - .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -direct_interc direct_interc_38_ ( + .out ( clb_I1i ) ) ; +grid_clb_direct_interc direct_interc_29_ ( .in ( { SYNOPSYS_UNCONNECTED_39 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_39_ ( + .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_30_ ( .in ( { SYNOPSYS_UNCONNECTED_40 } ) , - .out ( clb_I3[2] ) ) ; -direct_interc direct_interc_40_ ( + .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_31_ ( .in ( { SYNOPSYS_UNCONNECTED_41 } ) , - .out ( clb_I3[1] ) ) ; -direct_interc direct_interc_41_ ( + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_32_ ( .in ( { SYNOPSYS_UNCONNECTED_42 } ) , - .out ( clb_I3[0] ) ) ; -direct_interc direct_interc_42_ ( + .out ( clb_I2[2] ) ) ; +grid_clb_direct_interc direct_interc_33_ ( .in ( { SYNOPSYS_UNCONNECTED_43 } ) , - .out ( clb_I3i ) ) ; -direct_interc direct_interc_43_ ( + .out ( clb_I2[1] ) ) ; +grid_clb_direct_interc direct_interc_34_ ( .in ( { SYNOPSYS_UNCONNECTED_44 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -direct_interc direct_interc_44_ ( + .out ( clb_I2[0] ) ) ; +grid_clb_direct_interc direct_interc_35_ ( .in ( { SYNOPSYS_UNCONNECTED_45 } ) , - .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -direct_interc direct_interc_45_ ( + .out ( clb_I2i ) ) ; +grid_clb_direct_interc direct_interc_36_ ( .in ( { SYNOPSYS_UNCONNECTED_46 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_46_ ( + .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_37_ ( .in ( { SYNOPSYS_UNCONNECTED_47 } ) , - .out ( clb_I4[2] ) ) ; -direct_interc direct_interc_47_ ( + .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_38_ ( .in ( { SYNOPSYS_UNCONNECTED_48 } ) , - .out ( clb_I4[1] ) ) ; -direct_interc direct_interc_48_ ( + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_39_ ( .in ( { SYNOPSYS_UNCONNECTED_49 } ) , - .out ( clb_I4[0] ) ) ; -direct_interc direct_interc_49_ ( + .out ( clb_I3[2] ) ) ; +grid_clb_direct_interc direct_interc_40_ ( .in ( { SYNOPSYS_UNCONNECTED_50 } ) , - .out ( clb_I4i ) ) ; -direct_interc direct_interc_50_ ( + .out ( clb_I3[1] ) ) ; +grid_clb_direct_interc direct_interc_41_ ( .in ( { SYNOPSYS_UNCONNECTED_51 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -direct_interc direct_interc_51_ ( + .out ( clb_I3[0] ) ) ; +grid_clb_direct_interc direct_interc_42_ ( .in ( { SYNOPSYS_UNCONNECTED_52 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -direct_interc direct_interc_52_ ( + .out ( clb_I3i ) ) ; +grid_clb_direct_interc direct_interc_43_ ( .in ( { SYNOPSYS_UNCONNECTED_53 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_53_ ( + .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_44_ ( .in ( { SYNOPSYS_UNCONNECTED_54 } ) , - .out ( clb_I5[2] ) ) ; -direct_interc direct_interc_54_ ( + .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_45_ ( .in ( { SYNOPSYS_UNCONNECTED_55 } ) , - .out ( clb_I5[1] ) ) ; -direct_interc direct_interc_55_ ( + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_46_ ( .in ( { SYNOPSYS_UNCONNECTED_56 } ) , - .out ( clb_I5[0] ) ) ; -direct_interc direct_interc_56_ ( + .out ( clb_I4[2] ) ) ; +grid_clb_direct_interc direct_interc_47_ ( .in ( { SYNOPSYS_UNCONNECTED_57 } ) , - .out ( clb_I5i ) ) ; -direct_interc direct_interc_57_ ( + .out ( clb_I4[1] ) ) ; +grid_clb_direct_interc direct_interc_48_ ( .in ( { SYNOPSYS_UNCONNECTED_58 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -direct_interc direct_interc_58_ ( + .out ( clb_I4[0] ) ) ; +grid_clb_direct_interc direct_interc_49_ ( .in ( { SYNOPSYS_UNCONNECTED_59 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -direct_interc direct_interc_59_ ( + .out ( clb_I4i ) ) ; +grid_clb_direct_interc direct_interc_50_ ( .in ( { SYNOPSYS_UNCONNECTED_60 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_60_ ( + .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_51_ ( .in ( { SYNOPSYS_UNCONNECTED_61 } ) , - .out ( clb_I6[2] ) ) ; -direct_interc direct_interc_61_ ( + .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_52_ ( .in ( { SYNOPSYS_UNCONNECTED_62 } ) , - .out ( clb_I6[1] ) ) ; -direct_interc direct_interc_62_ ( + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_53_ ( .in ( { SYNOPSYS_UNCONNECTED_63 } ) , - .out ( clb_I6[0] ) ) ; -direct_interc direct_interc_63_ ( + .out ( clb_I5[2] ) ) ; +grid_clb_direct_interc direct_interc_54_ ( .in ( { SYNOPSYS_UNCONNECTED_64 } ) , - .out ( clb_I6i ) ) ; -direct_interc direct_interc_64_ ( + .out ( clb_I5[1] ) ) ; +grid_clb_direct_interc direct_interc_55_ ( .in ( { SYNOPSYS_UNCONNECTED_65 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -direct_interc direct_interc_65_ ( + .out ( clb_I5[0] ) ) ; +grid_clb_direct_interc direct_interc_56_ ( .in ( { SYNOPSYS_UNCONNECTED_66 } ) , - .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -direct_interc direct_interc_66_ ( + .out ( clb_I5i ) ) ; +grid_clb_direct_interc direct_interc_57_ ( .in ( { SYNOPSYS_UNCONNECTED_67 } ) , - .out ( clb_clk ) ) ; -direct_interc direct_interc_67_ ( + .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_58_ ( .in ( { SYNOPSYS_UNCONNECTED_68 } ) , - .out ( clb_I7[2] ) ) ; -direct_interc direct_interc_68_ ( + .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_59_ ( .in ( { SYNOPSYS_UNCONNECTED_69 } ) , - .out ( clb_I7[1] ) ) ; -direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_70 } ) , - .out ( clb_I7[0] ) ) ; -direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_71 } ) , - .out ( clb_I7i ) ) ; -direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_72 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_73 } ) , - .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_74 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , - .X ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , - .X ( p_abuf10 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , - .X ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , - .X ( clb_O[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , - .X ( clb_O[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , - .X ( p_abuf11 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , - .X ( clb_O[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , - .X ( p_abuf12 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , - .X ( p_abuf13 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , - .X ( clb_O[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , - .X ( clb_O[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , - .X ( clb_O[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , - .X ( p_abuf5 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , - .X ( clb_O[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , - .X ( p_abuf8 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , - .X ( p_abuf9 ) ) ; +grid_clb_direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_70 } ) , + .out ( clb_I6[2] ) ) ; +grid_clb_direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_71 } ) , + .out ( clb_I6[1] ) ) ; +grid_clb_direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_72 } ) , + .out ( clb_I6[0] ) ) ; +grid_clb_direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_73 } ) , + .out ( clb_I6i ) ) ; +grid_clb_direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_74 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_75 } ) , + .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_76 } ) , + .out ( clb_clk ) ) ; +grid_clb_direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_77 } ) , + .out ( clb_I7[2] ) ) ; +grid_clb_direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_78 } ) , + .out ( clb_I7[1] ) ) ; +grid_clb_direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_79 } ) , + .out ( clb_I7[0] ) ) ; +grid_clb_direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_80 } ) , + .out ( clb_I7i ) ) ; +grid_clb_direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_81 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; +grid_clb_direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_82 } ) , + .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_83 } ) , + .out ( clb_clk ) ) ; endmodule @@ -34442,7 +35530,8 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_upper , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -34521,24 +35610,26 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf1 ; -wire p_abuf14 ; wire p_abuf2 ; -wire p_abuf5 ; -wire p_abuf4 ; -wire ropt_net_143 ; -wire ropt_net_148 ; +wire ropt_net_150 ; +wire ropt_net_141 ; +wire ropt_net_139 ; wire ropt_net_144 ; -wire p_abuf13 ; -wire p_abuf12 ; -wire ropt_net_131 ; -wire ropt_net_130 ; -wire ropt_net_133 ; +wire ropt_net_140 ; +wire p_abuf15 ; +wire ropt_net_147 ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; -logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .clb_I0 ( { top_width_0_height_0__pin_0_[0] , top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , @@ -34571,161 +35662,142 @@ logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , - top_width_0_height_0__pin_37_upper[0] , - top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , - aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , - aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , - right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , - ropt_net_131 , ropt_net_130 } ) , - .clb_regout ( { ropt_net_134 } ) , - .clb_sc_out ( { aps_rename_153_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_133 ) , - .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , - .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , - .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , - .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , - .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , - .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , - .p4 ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , - .X ( aps_rename_130_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , - .X ( aps_rename_131_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , - .X ( aps_rename_133_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , - .X ( aps_rename_134_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , + .clb_O ( { ropt_net_145 , aps_rename_136_ , + top_width_0_height_0__pin_36_lower[0] , + top_width_0_height_0__pin_37_lower[0] , + top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , + top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , + aps_rename_144_ , aps_rename_145_ , + right_width_0_height_0__pin_44_lower[0] , + right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , + .clb_regout ( { ropt_net_153 } ) , + .clb_sc_out ( { aps_rename_155_ } ) , + .ccff_tail ( { ropt_net_149 } ) , + .p_abuf0 ( ropt_net_147 ) , .p_abuf3 ( ropt_net_150 ) , + .p_abuf5 ( p_abuf2 ) , + .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf10 ( ropt_net_141 ) , + .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , + .p_abuf14 ( ropt_net_139 ) , + .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf18 ( ropt_net_144 ) , + .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , + .p_abuf26 ( ropt_net_140 ) , + .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf30 ( p_abuf15 ) , + .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , + .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , + .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , - .X ( aps_rename_136_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , - .X ( aps_rename_138_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , - .X ( aps_rename_140_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , - .X ( aps_rename_142_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , - .X ( aps_rename_144_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , - .X ( aps_rename_146_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , - .X ( aps_rename_148_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , - .X ( aps_rename_149_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , - .X ( aps_rename_150_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , - .X ( aps_rename_151_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , - .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , - .X ( top_width_0_height_0__pin_36_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , - .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , - .X ( BUF_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , - .X ( BUF_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , - .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1134 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_5138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , + .X ( aps_rename_154_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , + .X ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , + .X ( clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , + .X ( prog_clk__FEEDTHRU_3[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , + .X ( ropt_net_162 ) ) ; endmodule @@ -34920,7 +35992,6 @@ wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_5_out ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; @@ -34959,7 +36030,6 @@ wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_1_ccff_tail ; wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; @@ -34995,7 +36065,6 @@ wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; @@ -35141,11 +36210,45 @@ wire [0:19] sb_2__1__0_chany_top_out ; wire [0:0] sb_2__2__0_ccff_tail ; wire [0:19] sb_2__2__0_chanx_left_out ; wire [0:19] sb_2__2__0_chany_bottom_out ; +wire [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:0] prog_clk__FEEDTHRU_2 ; +wire [0:0] prog_clk__FEEDTHRU_3 ; +wire [0:0] prog_clk__FEEDTHRU_4 ; +wire [0:0] prog_clk__FEEDTHRU_5 ; +wire [0:0] prog_clk__FEEDTHRU_6 ; +wire [0:0] prog_clk__FEEDTHRU_7 ; +wire [0:0] prog_clk__FEEDTHRU_8 ; +wire [0:0] prog_clk__FEEDTHRU_9 ; +wire [0:0] prog_clk__FEEDTHRU_10 ; +wire [0:0] prog_clk__FEEDTHRU_11 ; +wire [0:0] prog_clk__FEEDTHRU_12 ; +wire [0:0] prog_clk__FEEDTHRU_13 ; +wire [0:0] prog_clk__FEEDTHRU_14 ; +wire [0:0] prog_clk__FEEDTHRU_15 ; +wire [0:0] prog_clk__FEEDTHRU_16 ; +wire [0:0] prog_clk__FEEDTHRU_17 ; +wire [0:0] prog_clk__FEEDTHRU_18 ; +wire [0:0] prog_clk__FEEDTHRU_19 ; +wire [0:0] prog_clk__FEEDTHRU_20 ; +wire [0:0] Test_en__FEEDTHRU_1 ; +wire [0:0] Test_en__FEEDTHRU_2 ; +wire [0:0] Test_en__FEEDTHRU_3 ; +wire [0:0] Test_en__FEEDTHRU_4 ; +wire [0:0] Test_en__FEEDTHRU_5 ; +wire [0:0] Test_en__FEEDTHRU_6 ; +wire [0:0] clk__FEEDTHRU_1 ; +wire [0:0] clk__FEEDTHRU_2 ; +wire [0:0] clk__FEEDTHRU_3 ; +wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , +grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -35163,7 +36266,7 @@ grid_clb grid_clb_1__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , @@ -35214,14 +36317,18 @@ grid_clb grid_clb_1__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1517 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -35238,8 +36345,8 @@ grid_clb grid_clb_1__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -35291,13 +36398,18 @@ grid_clb grid_clb_1__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_57 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_2729 } ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -35315,7 +36427,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -35366,14 +36478,19 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_911 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_1315 } ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -35390,8 +36507,8 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -35443,12 +36560,16 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; +sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -35462,8 +36583,7 @@ sb_0__0_ sb_0__0_ ( .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -35481,9 +36601,9 @@ sb_0__1_ sb_0__1_ ( .chany_top_out ( sb_0__1__0_chany_top_out ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; -sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -35500,10 +36620,9 @@ sb_0__2_ sb_0__2_ ( .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; -sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; +sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , @@ -35532,10 +36651,18 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -35577,9 +36704,14 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -35614,12 +36746,14 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -35641,8 +36775,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -35676,9 +36809,10 @@ sb_2__1_ sb_2__1_ ( .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; -sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -35703,10 +36837,10 @@ sb_2__2_ sb_2__2_ ( .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .prog_clk ( { ctsbuf_net_3032 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -35740,10 +36874,12 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) ) ; + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_35 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -35777,10 +36913,11 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) ) ; -cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1416 } ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -35802,12 +36939,11 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , - .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) ) ; -cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -35829,12 +36965,11 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , - .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , - .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) ) ; -cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -35864,10 +36999,10 @@ cbx_1__2_ cbx_1__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -35897,10 +37032,9 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; +cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -35913,9 +37047,9 @@ cby_0__1_ cby_0__1_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; -cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -35928,9 +37062,9 @@ cby_0__1_ cby_0__2_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; +cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -35952,9 +37086,12 @@ cby_1__1_ cby_1__1_ ( .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; -cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -35976,9 +37113,12 @@ cby_1__1_ cby_1__2_ ( .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; -cby_2__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -36007,9 +37147,9 @@ cby_2__1_ cby_2__1_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_46 } ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -36038,59 +37178,50 @@ cby_2__1_ cby_2__2_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; -direct_interc_0_1 direct_interc_0_ ( + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; +direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; -direct_interc_1_1 direct_interc_1_ ( +direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , .out ( direct_interc_2_out ) ) ; direct_interc_3 direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , - .out ( { SYNOPSYS_UNCONNECTED_32 } ) ) ; + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , + .out ( { SYNOPSYS_UNCONNECTED_54 } ) ) ; direct_interc_4 direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , - .out ( { SYNOPSYS_UNCONNECTED_34 } ) ) ; -direct_interc_5 direct_interc_5_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_5_out ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_13 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_24 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , + .out ( { SYNOPSYS_UNCONNECTED_56 } ) ) ; +direct_interc direct_interc_5_ ( + .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .out ( { SYNOPSYS_UNCONNECTED_57 } ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , .Y ( ctsbuf_net_57 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_68 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_79 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_810 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_911 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1012 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1113 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( + .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , + .Y ( ctsbuf_net_1214 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( + .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , .Y ( ctsbuf_net_1517 ) ) ; -sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( - .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( - .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( - .A ( SYNOPSYS_UNCONNECTED_39 ) , .Y ( SYNOPSYS_UNCONNECTED_40 ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( - .A ( SYNOPSYS_UNCONNECTED_41 ) , .Y ( SYNOPSYS_UNCONNECTED_42 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1618 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1719 ) ) ; +sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , + .Y ( ctsbuf_net_2729 ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( + .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , + .Y ( ctsbuf_net_3032 ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( + .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , + .Y ( ctsbuf_net_3436 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_3537 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds index 9da9fb3..f1f5d0c 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:535427e1e95a2d00f9d3401478d5ce61f7bcb2e4608b0b9af9f00a7965479f82 -size 10821632 +oid sha256:b89f1ad33da0b82f8dd361e1e49734a9327449f1e4dd3d5349393798782ab4e9 +size 11003904 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v index 8a140ff..0d4b698 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.lvs.v @@ -4,14 +4,6 @@ // // // -module direct_interc_5 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - module direct_interc_2 ( in , out , VDD , VSS ) ; input [0:0] in ; output [0:0] out ; @@ -54,7 +46,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) , endmodule -module direct_interc_4 ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -62,8 +54,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -75,33 +67,53 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +wire aps_rename_1_ ; +supply0 VSS ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_7 ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -112,28 +124,31 @@ output [0:0] iopad_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule -module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -144,29 +159,27 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -direct_interc_4 direct_interc_0_ ( + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -178,8 +191,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -192,11 +203,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -208,8 +221,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -222,11 +233,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -238,8 +251,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -252,11 +263,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -268,8 +281,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -282,11 +293,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -298,8 +311,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -312,11 +323,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -328,8 +341,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -342,11 +353,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -358,8 +371,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -372,11 +383,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -388,8 +401,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -402,18 +413,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -425,7 +439,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -440,9 +454,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -458,15 +472,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -478,7 +493,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -493,9 +508,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -511,15 +526,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -531,7 +547,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -546,9 +562,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -564,15 +580,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -584,7 +601,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -599,9 +616,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -617,15 +634,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -637,7 +655,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -652,9 +670,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -670,15 +688,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -690,7 +709,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -705,9 +724,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -723,15 +742,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -743,7 +763,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -758,9 +778,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -776,15 +796,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -796,7 +817,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -811,9 +832,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -829,8 +850,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -842,8 +863,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -856,11 +875,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -872,8 +893,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -886,11 +905,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -902,8 +923,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -916,11 +935,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -932,8 +953,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -946,11 +965,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -962,8 +983,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -976,11 +995,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -992,8 +1013,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1006,11 +1025,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1022,8 +1043,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1036,11 +1055,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1052,8 +1073,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1066,11 +1085,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1082,8 +1103,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1096,18 +1115,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1121,7 +1143,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1143,9 +1165,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1161,15 +1183,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1183,7 +1206,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1205,9 +1228,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1223,15 +1246,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1245,7 +1269,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1267,9 +1291,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1285,15 +1309,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1307,7 +1332,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1329,9 +1354,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1347,15 +1372,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1369,7 +1395,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1391,9 +1417,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1409,15 +1435,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1431,7 +1458,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1453,9 +1480,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1471,15 +1498,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1493,7 +1521,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1515,9 +1543,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1533,15 +1561,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1555,7 +1584,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1577,9 +1606,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1595,15 +1624,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1617,7 +1647,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1639,9 +1669,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1667,7 +1697,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS ) ; + VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1700,6 +1730,7 @@ output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1754,321 +1785,392 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1553 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1554 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1555 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1556 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1557 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1499 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1558 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1559 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1560 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1502 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1561 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1562 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1563 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1564 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1565 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1566 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1567 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( @@ -2077,530 +2179,385 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x289800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x41400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x87400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( @@ -2615,41 +2572,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2673,13 +2630,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2703,13 +2660,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2733,13 +2690,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2763,13 +2720,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2793,13 +2750,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2823,13 +2780,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2853,13 +2810,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2883,13 +2840,337 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2938,8 +3219,8 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2992,331 +3273,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3340,15 +3298,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3372,13 +3330,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3402,13 +3360,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3432,13 +3390,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3462,13 +3420,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3492,13 +3450,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3522,13 +3480,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3552,13 +3510,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3620,8 +3578,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3683,8 +3641,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3746,8 +3704,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3809,8 +3767,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3872,8 +3830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3935,8 +3893,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3998,8 +3956,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4067,7 +4025,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , + prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -4093,6 +4054,10 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -4144,7 +4109,9 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , @@ -4152,8 +4119,8 @@ mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , @@ -4161,8 +4128,8 @@ mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , @@ -4170,8 +4137,8 @@ mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , @@ -4179,8 +4146,8 @@ mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , @@ -4188,8 +4155,8 @@ mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , @@ -4197,8 +4164,8 @@ mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , @@ -4206,8 +4173,8 @@ mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , @@ -4215,461 +4182,506 @@ mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1537 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1538 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1539 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1540 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1541 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1542 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1484 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1543 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1544 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1545 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1546 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1547 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1548 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1549 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1550 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1551 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4677,245 +4689,255 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x59800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -4931,40 +4953,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module direct_interc_3 ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -4972,8 +4994,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4988,13 +5010,15 @@ supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -5012,20 +5036,20 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_6 ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; @@ -5046,13 +5070,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -5060,9 +5085,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -5078,7 +5104,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -5086,17 +5112,17 @@ logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_3 direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc_3 direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5125,8 +5151,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5148,9 +5174,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -5185,6 +5208,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -5193,7 +5219,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS ) ; + right_width_0_height_0__pin_1_lower , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -5210,238 +5236,266 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1521 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1522 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1523 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1524 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1466 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1525 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1526 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1527 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1528 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1529 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1530 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1531 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1532 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1533 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1534 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1535 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -5456,110 +5510,84 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y27200 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y54400 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( @@ -5568,15 +5596,13 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5586,11 +5612,23 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5602,30 +5640,36 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( @@ -5640,29 +5684,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5670,39 +5716,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5718,29 +5762,35 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5754,75 +5804,79 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5844,9 +5898,7 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5854,16 +5906,12 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( @@ -5878,26 +5926,30 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( @@ -5920,24 +5972,22 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( @@ -5952,29 +6002,35 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -5992,31 +6048,27 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6032,25 +6084,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6072,32 +6132,24 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( @@ -6112,28 +6164,32 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( @@ -6150,32 +6206,26 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( @@ -6184,39 +6234,41 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6224,137 +6276,141 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -6370,40 +6426,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module direct_interc_2 ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -6411,8 +6467,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6427,15 +6483,15 @@ supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -6451,16 +6507,16 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_5 ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; @@ -6480,13 +6536,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -6494,9 +6551,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -6512,7 +6570,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -6520,17 +6578,14 @@ logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_2 direct_interc_0_ ( +cbx_1__2__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6559,8 +6614,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6589,8 +6644,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6619,8 +6674,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6649,8 +6704,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6679,8 +6734,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6704,13 +6759,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6739,8 +6794,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6769,8 +6824,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6823,8 +6878,278 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6866,15 +7191,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6927,269 +7252,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7213,13 +7277,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7248,8 +7312,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7278,8 +7342,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7308,8 +7372,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7338,8 +7402,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7368,8 +7432,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7398,8 +7462,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7423,13 +7487,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7453,13 +7517,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7521,8 +7585,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7584,8 +7648,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7647,8 +7711,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7710,8 +7774,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7773,8 +7837,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7836,8 +7900,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7899,8 +7963,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7918,13 +7982,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7955,15 +8015,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -8074,7 +8134,7 @@ output SC_OUT_BOT ; input VDD ; input VSS ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -8130,7 +8190,7 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -8138,8 +8198,8 @@ mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , @@ -8147,8 +8207,8 @@ mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , @@ -8156,8 +8216,8 @@ mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , @@ -8165,8 +8225,8 @@ mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , @@ -8174,8 +8234,8 @@ mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , @@ -8183,8 +8243,8 @@ mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , @@ -8192,8 +8252,8 @@ mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , @@ -8201,8 +8261,8 @@ mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -8210,643 +8270,1034 @@ mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1503 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1504 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1505 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1506 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1507 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1508 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1509 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1510 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1511 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1512 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1513 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1514 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1460 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1515 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1516 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1517 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1518 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1519 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 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) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_2!x418600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_1!x708400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8870,13 +9321,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8900,13 +9351,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8930,13 +9381,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8960,13 +9411,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8990,13 +9441,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9020,13 +9471,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9050,13 +9501,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9080,12 +9531,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9138,7 +9590,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9191,167 +9644,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9393,14 +9687,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9453,8 +9748,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -9507,249 +9802,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -9765,54 +9820,45 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -9828,54 +9874,45 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; @@ -9891,1256 +9928,49 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , - chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , - bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , - bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , - bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , - bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , - bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:19] chanx_left_in ; -input [0:19] chanx_right_in ; -input [0:0] ccff_head ; -output [0:19] chanx_left_out ; -output [0:19] chanx_right_out ; -output [0:0] bottom_grid_pin_0_ ; -output [0:0] bottom_grid_pin_1_ ; -output [0:0] bottom_grid_pin_2_ ; -output [0:0] bottom_grid_pin_3_ ; -output [0:0] bottom_grid_pin_4_ ; -output [0:0] bottom_grid_pin_5_ ; -output [0:0] bottom_grid_pin_6_ ; -output [0:0] bottom_grid_pin_7_ ; -output [0:0] bottom_grid_pin_8_ ; -output [0:0] bottom_grid_pin_9_ ; -output [0:0] bottom_grid_pin_10_ ; -output [0:0] bottom_grid_pin_11_ ; -output [0:0] bottom_grid_pin_12_ ; -output [0:0] bottom_grid_pin_13_ ; -output [0:0] bottom_grid_pin_14_ ; -output [0:0] bottom_grid_pin_15_ ; -output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; -input SC_IN_TOP ; -input SC_IN_BOT ; -output SC_OUT_TOP ; -output SC_OUT_BOT ; -input VDD ; -input VSS ; - -wire [0:3] mux_tree_tapbuf_size10_0_sram ; -wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_1_sram ; -wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_2_sram ; -wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_3_sram ; -wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_4_sram ; -wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_5_sram ; -wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_6_sram ; -wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size10_7_sram ; -wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; -wire [0:3] mux_tree_tapbuf_size8_0_sram ; -wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_1_sram ; -wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_2_sram ; -wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_3_sram ; -wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_4_sram ; -wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_5_sram ; -wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_6_sram ; -wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; -wire [0:3] mux_tree_tapbuf_size8_7_sram ; -wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; -wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; -wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign SC_IN_TOP = SC_IN_BOT ; - -mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , - chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , - chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size10_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , - chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size10_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , - chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size10_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , - chanx_right_in[15] } ) , - .sram ( mux_tree_tapbuf_size10_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , - chanx_right_in[16] } ) , - .sram ( mux_tree_tapbuf_size10_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , - chanx_right_in[19] } ) , - .sram ( mux_tree_tapbuf_size10_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size10_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , - chanx_left_in[13] , chanx_right_in[13] } ) , - .sram ( mux_tree_tapbuf_size8_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , - chanx_left_in[14] , chanx_right_in[14] } ) , - .sram ( mux_tree_tapbuf_size8_5_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( - .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , - chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , - chanx_left_in[17] , chanx_right_in[17] } ) , - .sram ( mux_tree_tapbuf_size8_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( - .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , - chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , - chanx_left_in[18] , chanx_right_in[18] } ) , - .sram ( mux_tree_tapbuf_size8_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_0_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_1_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_2_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_3_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_4_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_5_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_6_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .mem_out ( mux_tree_tapbuf_size8_7_sram ) , - .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11148,123 +9978,29 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11272,122 +10008,29 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , - .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11395,122 +10038,29 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , - .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11518,122 +10068,29 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -output p_abuf1 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; -output p_abuf1 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11641,122 +10098,29 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , - .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module direct_interc_1 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; -output [0:0] mem_out ; -output [0:0] mem_outb ; +output [0:3] mem_out ; +output [0:3] mem_outb ; input VDD ; input VSS ; @@ -11764,109 +10128,24 @@ supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , - .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; -input SOC_IN ; -output SOC_OUT ; -output SOC_DIR ; -output FPGA_IN ; -input FPGA_OUT ; -input FPGA_DIR ; -output p_abuf0 ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -assign SOC_OUT = FPGA_OUT ; - -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , - gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , - gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] iopad_outpad ; -input [0:0] ccff_head ; -output [0:0] iopad_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -wire [0:0] EMBEDDED_IO_0_en ; -supply1 VDD ; -supply0 VSS ; - -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , - .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , - .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; -input [0:0] prog_clk ; -input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; -output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; -input [0:0] io_outpad ; -input [0:0] ccff_head ; -output [0:0] io_inpad ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -output p_abuf0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( - .prog_clk ( prog_clk ) , - .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , - .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , - .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( io_outpad ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11890,13 +10169,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11920,133 +10199,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12108,8 +10267,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12171,8 +10330,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12234,8 +10393,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12297,8 +10456,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12360,8 +10519,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12419,6 +10578,2658 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , + chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , + bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ , + bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ , + bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , + bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , + bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , + prog_clk__FEEDTHRU_1 ) ; +input [0:0] prog_clk ; +input [0:19] chanx_left_in ; +input [0:19] chanx_right_in ; +input [0:0] ccff_head ; +output [0:19] chanx_left_out ; +output [0:19] chanx_right_out ; +output [0:0] bottom_grid_pin_0_ ; +output [0:0] bottom_grid_pin_1_ ; +output [0:0] bottom_grid_pin_2_ ; +output [0:0] bottom_grid_pin_3_ ; +output [0:0] bottom_grid_pin_4_ ; +output [0:0] bottom_grid_pin_5_ ; +output [0:0] bottom_grid_pin_6_ ; +output [0:0] bottom_grid_pin_7_ ; +output [0:0] bottom_grid_pin_8_ ; +output [0:0] bottom_grid_pin_9_ ; +output [0:0] bottom_grid_pin_10_ ; +output [0:0] bottom_grid_pin_11_ ; +output [0:0] bottom_grid_pin_12_ ; +output [0:0] bottom_grid_pin_13_ ; +output [0:0] bottom_grid_pin_14_ ; +output [0:0] bottom_grid_pin_15_ ; +output [0:0] ccff_tail ; +input SC_IN_TOP ; +input SC_IN_BOT ; +output SC_OUT_TOP ; +output SC_OUT_BOT ; +input VDD ; +input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; + +wire [0:3] mux_tree_tapbuf_size10_0_sram ; +wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_1_sram ; +wire [0:3] mux_tree_tapbuf_size10_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_2_sram ; +wire [0:3] mux_tree_tapbuf_size10_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_3_sram ; +wire [0:3] mux_tree_tapbuf_size10_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_4_sram ; +wire [0:3] mux_tree_tapbuf_size10_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_5_sram ; +wire [0:3] mux_tree_tapbuf_size10_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_6_sram ; +wire [0:3] mux_tree_tapbuf_size10_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size10_7_sram ; +wire [0:3] mux_tree_tapbuf_size10_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ; +wire [0:3] mux_tree_tapbuf_size8_0_sram ; +wire [0:3] mux_tree_tapbuf_size8_0_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_1_sram ; +wire [0:3] mux_tree_tapbuf_size8_1_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_2_sram ; +wire [0:3] mux_tree_tapbuf_size8_2_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_3_sram ; +wire [0:3] mux_tree_tapbuf_size8_3_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_4_sram ; +wire [0:3] mux_tree_tapbuf_size8_4_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_5_sram ; +wire [0:3] mux_tree_tapbuf_size8_5_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_6_sram ; +wire [0:3] mux_tree_tapbuf_size8_6_sram_inv ; +wire [0:3] mux_tree_tapbuf_size8_7_sram ; +wire [0:3] mux_tree_tapbuf_size8_7_sram_inv ; +wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_3_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_4_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; +wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign SC_IN_TOP = SC_IN_BOT ; + +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , + .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , + chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , + chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size10_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , + .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , + chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size10_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , + .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , + chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size10_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , + .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , + chanx_right_in[15] } ) , + .sram ( mux_tree_tapbuf_size10_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , + .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , + chanx_right_in[16] } ) , + .sram ( mux_tree_tapbuf_size10_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , + .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , + chanx_right_in[19] } ) , + .sram ( mux_tree_tapbuf_size10_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , + .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size10_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_0_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_1_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , + .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_2_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_3_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , + .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , + chanx_left_in[13] , chanx_right_in[13] } ) , + .sram ( mux_tree_tapbuf_size8_4_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , + .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , + chanx_left_in[14] , chanx_right_in[14] } ) , + .sram ( mux_tree_tapbuf_size8_5_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , + .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , + chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , + chanx_left_in[17] , chanx_right_in[17] } ) , + .sram ( mux_tree_tapbuf_size8_6_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , + .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , + chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , + chanx_left_in[18] , chanx_right_in[18] } ) , + .sram ( mux_tree_tapbuf_size8_7_sram ) , + .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , + .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_0_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_1_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_2_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_3_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_4_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_5_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_6_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .mem_out ( mux_tree_tapbuf_size8_7_sram ) , + .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1485 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1486 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1487 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1488 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1489 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1490 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1491 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1492 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1493 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1494 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1495 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1496 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1497 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1499 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1500 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1501 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb14_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , + .X ( net_aps_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb11_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , + .X ( net_aps_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb8_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , + .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb5_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , + .X ( net_aps_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__direct_interc ( in , out ) ; +input [0:0] in ; +output [0:0] out ; + +assign out[0] = in[0] ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:0] mem_out ; +output [0:0] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb2_mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , + .X ( net_aps_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; +input SOC_IN ; +output SOC_OUT ; +output SOC_DIR ; +output FPGA_IN ; +input FPGA_OUT ; +input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +assign SOC_OUT = FPGA_OUT ; + +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] iopad_outpad ; +input [0:0] ccff_head ; +output [0:0] iopad_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +wire [0:0] EMBEDDED_IO_0_en ; +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , + .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , + .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , + .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; +input [0:0] prog_clk ; +input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; +output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; +input [0:0] io_outpad ; +input [0:0] ccff_head ; +output [0:0] io_inpad ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; + +supply1 VDD ; +supply0 VSS ; + +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( + .prog_clk ( prog_clk ) , + .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , + .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , + .iopad_inpad ( io_inpad ) , + .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( io_outpad ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -12434,7 +13245,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -12475,13 +13286,15 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -12503,8 +13316,9 @@ supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -12512,8 +13326,8 @@ mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( + .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , @@ -12521,8 +13335,8 @@ mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , @@ -12530,8 +13344,8 @@ mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , @@ -12539,8 +13353,8 @@ mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , @@ -12548,8 +13362,8 @@ mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , @@ -12557,364 +13371,399 @@ mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1429 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1477 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1480 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1481 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1482 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1483 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , - .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -12925,707 +13774,925 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x124200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 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\xofiller!sky130_fd_sc_hd__fill_1!x36800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13648,7 +14715,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13672,8 +14739,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13696,8 +14763,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13728,8 +14795,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13760,8 +14827,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13792,7 +14859,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13812,14 +14879,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13842,8 +14907,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13866,8 +14931,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13890,8 +14955,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13914,8 +14979,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13938,8 +15003,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13962,8 +15027,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13986,8 +15051,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14010,8 +15075,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14034,8 +15099,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14058,8 +15123,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14082,8 +15147,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14106,8 +15171,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14130,8 +15195,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14154,8 +15219,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14178,8 +15243,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14202,8 +15267,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14226,8 +15291,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14250,8 +15315,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14274,8 +15339,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14298,8 +15363,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14322,8 +15387,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14346,8 +15411,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14370,8 +15435,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14397,8 +15462,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14424,8 +15489,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14451,8 +15516,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14478,8 +15543,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14505,8 +15570,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14532,8 +15597,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14559,8 +15624,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14586,8 +15651,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14613,35 +15678,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14667,8 +15705,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14694,8 +15732,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14721,8 +15759,197 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14744,8 +15971,8 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14771,8 +15998,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14794,219 +16075,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15033,8 +16102,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15060,8 +16129,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15087,8 +16156,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15114,7 +16183,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15154,8 +16224,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15195,8 +16265,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15236,8 +16306,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15254,9 +16324,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -15274,10 +16341,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15304,8 +16376,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15331,8 +16403,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15358,8 +16430,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15385,8 +16457,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15430,8 +16502,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15475,8 +16547,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15520,8 +16592,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15535,13 +16607,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -15558,10 +16626,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -15717,1480 +16785,1795 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1433 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1434 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1435 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1436 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1437 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1438 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1439 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1440 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1441 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1442 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1443 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1444 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1445 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1446 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1447 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1448 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1449 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1450 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1451 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1452 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1453 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1454 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1455 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1456 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1457 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1458 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1459 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1460 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1461 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1462 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1463 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1464 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1465 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y81600 ( 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\xofiller!sky130_fd_sc_hd__fill_2!x299000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x680800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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- .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y163200 ( 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+ .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x87400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x92000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( 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VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y462400 ( 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\xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x82800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x55200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x87400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y625600 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x59800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( 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-sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x82800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -17204,52 +18587,384 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17268,15 +18983,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17294,13 +19011,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17318,13 +19035,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17342,13 +19059,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17366,13 +19083,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17390,13 +19107,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17422,8 +19139,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17449,8 +19166,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17476,8 +19220,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17503,35 +19247,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17551,13 +19268,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17576,13 +19293,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17600,13 +19317,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17624,13 +19341,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17648,13 +19365,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17672,44 +19389,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17740,8 +19426,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17772,8 +19458,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17804,8 +19490,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -17836,7 +19522,120 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -17858,94 +19657,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -17980,8 +19698,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18016,8 +19734,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18052,7 +19770,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18068,9 +19787,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18084,10 +19800,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18112,12 +19831,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18175,7 +19895,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18197,67 +19971,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18301,8 +20021,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18346,8 +20066,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18365,9 +20085,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -18388,10 +20105,148 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18413,13 +20268,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18440,148 +20295,113 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18630,8 +20450,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18674,14 +20494,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18730,8 +20550,54 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -18780,158 +20646,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18955,13 +20671,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18985,13 +20701,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19071,8 +20787,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19152,7 +20868,37 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19177,13 +20923,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19207,43 +20953,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19296,7 +21066,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19349,62 +21120,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19428,13 +21145,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19458,13 +21175,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19521,15 +21238,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19604,7 +21319,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS ) ; + chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , + Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -19642,6 +21358,8 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -19744,7 +21462,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size10_12 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , @@ -19752,29 +21470,30 @@ mux_tree_tapbuf_size10_12 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , @@ -19782,42 +21501,44 @@ mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_1 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -19827,8 +21548,8 @@ mux_tree_tapbuf_size14_1 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -19838,159 +21559,168 @@ mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_10 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , @@ -19998,218 +21728,217 @@ mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_9 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_9 mux_left_track_25 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1392 ( .VNB ( VSS ) , @@ -20232,243 +21961,384 @@ sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1402 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1403 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1404 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1405 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1406 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1407 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1408 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1409 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1410 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1411 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1412 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1413 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1414 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1415 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1416 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1417 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1418 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1419 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1420 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1421 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1422 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1423 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1424 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1425 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1426 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1427 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1428 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x138000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -20476,651 +22346,881 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x101200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( +sky130_fd_sc_hd__fill_8 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) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x809600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x69000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( 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\xofiller!sky130_fd_sc_hd__fill_4!x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y435200 ( +sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x161000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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\xofiller!sky130_fd_sc_hd__fill_2!x542800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x78200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x96600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( +sky130_fd_sc_hd__fill_4 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, .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y625600 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x230000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x225400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -21128,184 +23228,402 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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+sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x828000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y924800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y924800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21332,8 +23650,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21359,8 +23677,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21386,8 +23704,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21413,7 +23731,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21448,8 +23767,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21484,8 +23803,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21520,8 +23839,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -21537,9 +23856,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21553,11 +23869,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21575,15 +23894,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21606,8 +23925,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21630,8 +23949,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21654,8 +23973,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21678,8 +23997,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21702,8 +24021,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21726,8 +24045,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21750,8 +24069,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21774,8 +24093,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21798,8 +24117,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21822,8 +24141,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21846,7 +24165,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21870,8 +24189,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21894,8 +24213,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21918,8 +24237,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21942,8 +24261,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21966,8 +24285,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21990,8 +24309,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22014,8 +24333,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22038,8 +24357,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22053,74 +24372,20 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22142,8 +24407,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22163,14 +24428,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22196,8 +24461,216 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22223,8 +24696,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22250,8 +24723,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22277,8 +24750,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22304,8 +24777,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22331,8 +24804,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22358,8 +24831,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22385,8 +24858,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22412,170 +24885,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22598,7 +24909,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22622,8 +24933,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22654,7 +24965,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22685,7 +24997,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22712,8 +25024,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22739,7 +25051,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22779,8 +25092,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22820,7 +25133,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22847,8 +25160,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22874,7 +25187,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22918,8 +25232,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22937,6 +25251,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -22957,9 +25274,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -23088,380 +25402,428 @@ wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_8 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1365 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1366 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1367 ( .VNB ( VSS ) , @@ -23494,74 +25856,118 @@ sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1380 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1381 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1382 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1383 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1384 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1385 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1386 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1387 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1388 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1389 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -23576,45 +25982,51 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -23622,1058 +26034,1512 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y27200 ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y54400 ( - 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) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x280600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y163200 ( 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x280600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 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) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_8!x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x400200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y462400 ( +sky130_fd_sc_hd__fill_4 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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, .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y571200 ( +sky130_fd_sc_hd__fill_1 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y652800 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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-sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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- .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24695,14 +27561,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24746,7 +27613,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24765,13 +27632,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24785,19 +27652,19 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24816,13 +27683,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24840,13 +27707,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24864,13 +27731,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24888,13 +27755,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24912,13 +27779,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24936,12 +27803,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -24966,14 +27834,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25004,8 +27872,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25036,8 +27904,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25068,8 +27936,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25100,8 +27968,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25132,7 +28000,61 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25154,67 +28076,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25249,8 +28117,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25285,7 +28153,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25320,7 +28189,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25342,12 +28211,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25387,7 +28257,169 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25409,13 +28441,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25436,225 +28468,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25703,8 +28523,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25753,8 +28573,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25803,8 +28623,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25819,7 +28639,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; @@ -25845,16 +28664,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25903,7 +28719,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25952,8 +28769,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -26002,7 +28819,87 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26027,43 +28924,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26116,7 +28983,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26169,8 +29037,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26194,13 +29062,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26224,13 +29092,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26310,7 +29178,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26390,7 +29259,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26415,72 +29344,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26538,61 +29408,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26650,8 +29467,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26675,13 +29551,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26758,7 +29634,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -26800,6 +29678,8 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -26889,7 +29769,7 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_11 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -26898,14 +29778,14 @@ mux_tree_tapbuf_size10_11 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -26913,8 +29793,8 @@ mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -26922,8 +29802,8 @@ mux_tree_tapbuf_size9_0 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -26931,26 +29811,29 @@ mux_tree_tapbuf_size9_1 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -26961,8 +29844,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -26972,20 +29855,22 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , @@ -26993,295 +29878,355 @@ mux_tree_tapbuf_size8_2 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_8 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1335 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1337 ( .VNB ( VSS ) , @@ -27316,1182 +30261,2193 @@ sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1058000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x138000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x786600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x78200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x938400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y299200 ( 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\xofiller!sky130_fd_sc_hd__fill_4!x331200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x966000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x782000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1012000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1048800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1067200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1058000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1076400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x358800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x151800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1168400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_2!x846400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1048800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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-sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x970600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1113200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x303600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x280600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1099400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y571200 ( 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\xofiller!sky130_fd_sc_hd__fill_2!x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1094800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1154600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1163800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x101200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1035000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x772800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1062600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1099400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1136200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1173000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1209800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x308200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x1002800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y761600 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x1090200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x924600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x961400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x998200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -28513,96 +32469,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -28651,8 +32524,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -28701,8 +32574,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -28751,7 +32624,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -28766,13 +32640,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28793,15 +32663,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28825,13 +32695,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28855,13 +32725,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28885,13 +32755,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28915,13 +32785,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28945,13 +32815,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28975,13 +32845,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29005,13 +32875,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29035,13 +32905,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29065,13 +32935,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29095,13 +32965,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29125,13 +32995,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29155,13 +33025,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29223,8 +33093,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29286,8 +33156,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29349,8 +33219,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29412,8 +33282,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29475,8 +33345,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29538,8 +33408,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29601,8 +33471,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29664,8 +33534,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29727,8 +33597,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29790,8 +33660,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29853,7 +33723,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29915,8 +33786,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29943,13 +33814,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29976,13 +33847,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30009,13 +33880,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30042,13 +33913,193 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -30137,94 +34188,8 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -30252,9 +34217,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -30310,100 +34272,14 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30427,13 +34303,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30457,13 +34333,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30487,13 +34363,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30517,13 +34393,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30547,13 +34423,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30577,13 +34453,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30607,13 +34483,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30637,13 +34513,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30714,8 +34590,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30786,8 +34662,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30858,8 +34734,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30930,8 +34806,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -31002,8 +34878,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -31074,7 +34950,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -31145,8 +35022,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -31233,7 +35110,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; + chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , + prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -31279,6 +35159,11 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -31366,7 +35251,7 @@ wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -31375,8 +35260,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -31385,8 +35270,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -31395,8 +35280,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -31405,8 +35290,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -31415,8 +35300,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -31425,8 +35310,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -31435,8 +35320,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -31445,56 +35330,62 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -31503,10 +35394,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -31517,8 +35408,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -31527,10 +35418,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -31539,34 +35430,37 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , @@ -31574,8 +35468,8 @@ mux_tree_tapbuf_size10 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , @@ -31583,8 +35477,8 @@ mux_tree_tapbuf_size10_9 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , @@ -31592,8 +35486,8 @@ mux_tree_tapbuf_size10_10 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , @@ -31601,8 +35495,8 @@ mux_tree_tapbuf_size10_8 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , @@ -31610,8 +35504,8 @@ mux_tree_tapbuf_size10_6 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , @@ -31619,8 +35513,8 @@ mux_tree_tapbuf_size10_7 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , @@ -31628,8 +35522,8 @@ mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , @@ -31637,8 +35531,8 @@ mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , @@ -31646,8 +35540,8 @@ mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , @@ -31655,8 +35549,8 @@ mux_tree_tapbuf_size10_5 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , @@ -31664,8 +35558,8 @@ mux_tree_tapbuf_size10_3 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -31673,135 +35567,199 @@ mux_tree_tapbuf_size10_4 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1302 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1304 ( .VNB ( VSS ) , @@ -31828,543 +35786,986 @@ sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_4!x349600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x87400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x124200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_2!x874000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y217600 ( 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\xofiller!sky130_fd_sc_hd__fill_2!x1016600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x78200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1127000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1145400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1196000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1154600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x46000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x915400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1131600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y299200 ( + .VPWR ( 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\xofiller!sky130_fd_sc_hd__fill_1!x184000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x570400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x133400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x542800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1071800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x984400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -32372,376 +36773,1033 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x791200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x611800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x924600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x933800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1136200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x386400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x759000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x961400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x979800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1039600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1062600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1076400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x860200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1053400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x69000y734400 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x892400y734400 ( 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VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1113200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x119600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x312800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( 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\xofiller!sky130_fd_sc_hd__fill_1!x920000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1145400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y843200 ( 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) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1122400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1191400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1150000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y870400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1021200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1058000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1094800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x993600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1140800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x864800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32763,42 +37821,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -32838,7 +37867,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -32878,7 +37908,34 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -32900,40 +37957,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -32947,9 +37977,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -32966,14 +38000,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -32987,9 +38022,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -33006,15 +38045,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33038,13 +38077,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33068,13 +38107,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -33141,7 +38180,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -33164,9 +38204,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -33205,10 +38242,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -33227,13 +38267,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33259,7 +38299,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -33278,13 +38318,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33302,13 +38342,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33326,13 +38366,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33350,13 +38390,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33374,13 +38414,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33398,13 +38438,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33422,12 +38462,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33458,7 +38499,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33489,7 +38531,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33520,8 +38563,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33552,8 +38595,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33584,8 +38627,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33616,8 +38659,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -33648,7 +38691,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -33670,40 +38740,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -33738,7 +38781,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -33773,7 +38817,169 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -33795,13 +39001,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33822,13 +39028,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -33849,175 +39055,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34066,7 +39110,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34115,8 +39160,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34165,7 +39210,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34214,7 +39260,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34263,7 +39310,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34312,7 +39360,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34361,7 +39410,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34410,7 +39460,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -34459,7 +39510,67 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -34484,72 +39595,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -34602,7 +39654,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -34655,7 +39708,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -34719,7 +39773,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -34755,6 +39813,16 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -34843,8 +39911,11 @@ supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , @@ -34852,307 +39923,324 @@ mux_tree_tapbuf_size8 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_6 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -35161,71 +40249,141 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1255 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1263 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1272 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1274 ( .VNB ( VSS ) , @@ -35234,1232 +40392,1812 @@ sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x271400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x855600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x202400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x119600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x791200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x230000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x593400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x96600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x975200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1012000y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x55200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x92000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1108600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1140800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1177600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1214400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x998200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1016600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x667000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1108600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1145400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x161000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x588800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1067200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 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.VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x993600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1030400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y380800 ( 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; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 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, .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x717600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1062600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x763600y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x929200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x975200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1030400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x142600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x970600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x998200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1127000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1145400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1154600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1025800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1021200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1104000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y625600 ( +sky130_fd_sc_hd__fill_8 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1081000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1007400y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x648600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x722200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x791200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x828000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x855600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x938400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x947600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x993600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1002800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1094800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x653200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x897000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x906200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x952200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1071800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1131600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1150000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x800400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1085600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1168400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -36467,85 +42205,327 @@ sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1016600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1044200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x956800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x975200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x984400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x156400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x966000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1002800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1076400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1113200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1150000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1186800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x841800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36563,15 +42543,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36594,8 +42576,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36618,8 +42600,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36642,7 +42624,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -36666,8 +42648,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36690,8 +42672,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36714,8 +42696,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36738,8 +42720,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36762,8 +42744,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36786,8 +42768,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36810,8 +42792,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36834,8 +42816,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36858,8 +42840,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36882,8 +42864,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36906,8 +42888,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36930,8 +42912,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36954,8 +42936,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -36978,8 +42960,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37005,8 +42987,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37032,8 +43014,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37059,8 +43041,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37086,8 +43068,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37097,304 +43079,6 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; @@ -37402,18 +43086,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37439,8 +43118,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37466,8 +43172,278 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -37490,7 +43466,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -37514,8 +43490,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37546,7 +43522,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -37577,7 +43554,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -37604,8 +43581,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -37631,7 +43608,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -37671,8 +43649,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -37712,7 +43690,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -37739,8 +43717,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -37766,7 +43744,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -37810,8 +43789,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -37962,497 +43941,582 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1256 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1257 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1258 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1259 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1260 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1261 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1262 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1263 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1264 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1265 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1266 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1267 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1268 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1269 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1270 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1218 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1271 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1226 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1235 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x64400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -38460,85 +44524,141 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x547400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y136000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x142600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x179400y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x179400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x308200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x805000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -38546,243 +44666,293 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x768200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x496800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x119600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x193200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x156400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x248400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x303600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x322000y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x138000y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x216200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x280600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x874000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -38790,104 +44960,138 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x533600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x818800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x892400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( @@ -38898,131 +45102,149 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_8!x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x644000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x105800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x142600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x266800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x473800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39030,90 +45252,92 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x188600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x326600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x128800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x165600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x230000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( @@ -39130,27 +45354,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39166,35 +45402,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x257600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x869400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39210,37 +45456,43 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x427800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x598000y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39264,35 +45516,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39308,44 +45558,46 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x575000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( @@ -39368,38 +45620,44 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( @@ -39414,37 +45672,51 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x685400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -39468,42 +45740,394 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -39527,8 +46151,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39551,8 +46175,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39575,8 +46199,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39599,8 +46223,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39623,8 +46247,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39647,8 +46271,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39674,8 +46298,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39701,8 +46325,54 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39728,8 +46398,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39755,62 +46425,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39829,13 +46445,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -39859,8 +46475,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39883,8 +46499,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39907,8 +46523,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -39931,7 +46547,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39962,7 +46579,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -39993,7 +46611,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -40024,7 +46643,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -40055,7 +46675,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -40086,7 +46707,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -40113,8 +46734,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40140,8 +46761,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40167,7 +46788,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40216,7 +46838,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40265,7 +46888,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40314,8 +46938,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40341,8 +46965,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40368,8 +46992,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40395,8 +47019,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40422,8 +47046,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40449,7 +47073,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -40476,8 +47100,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40503,7 +47127,44 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40538,8 +47199,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40574,44 +47235,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40646,7 +47271,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40681,7 +47307,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40716,7 +47343,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40751,8 +47379,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40778,8 +47406,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40805,8 +47433,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40832,8 +47460,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40859,7 +47487,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -40886,7 +47514,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40926,7 +47555,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -40966,7 +47596,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41006,7 +47637,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41046,7 +47678,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41086,8 +47719,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41113,8 +47746,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41140,8 +47773,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41167,8 +47800,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41194,7 +47827,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -41221,8 +47854,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41248,8 +47881,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41275,7 +47908,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41319,7 +47953,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41363,7 +47998,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41407,7 +48043,55 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41451,7 +48135,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41495,51 +48180,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -41589,7 +48231,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS ) ; + chany_bottom_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -41611,6 +48253,7 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -41713,263 +48356,278 @@ wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_3 mux_top_track_32 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , @@ -41977,314 +48635,413 @@ mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1165 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1166 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1167 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1168 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1240 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1169 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1241 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1170 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1171 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1172 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1173 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1174 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1175 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1176 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1177 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1178 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1179 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1180 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1181 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1253 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1182 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1254 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1183 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1184 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1185 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1186 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1187 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( @@ -42293,263 +49050,341 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y0 ( + .VGND ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x657800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x105800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x165600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x625600y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x469200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x690000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x142600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x174800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y217600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x754400y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x676200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x685400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x151800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x473800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y244800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -42557,339 +49392,409 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x611800y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x621000y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x731400y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x786600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x220800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x266800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y326400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x464600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x524400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x542800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x386400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x64400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y353600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x782000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x455400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x225400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x101200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x478400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x345000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x289800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x354200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x418600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x170200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x271400y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y435200 ( 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\xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x115000y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x207000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x193200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x243800y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x230000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x322000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x625600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x174800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x197800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x243800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x437000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x363400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x883200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -42897,517 +49802,717 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x179400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x188600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x910800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_2!x386400y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x473800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x570400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x657800y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y571200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x878600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x55200y598400 ( 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; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x492200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x492200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x749800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x377200y680000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 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) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x506000y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x731400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 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+ .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x437000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x630200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x639400y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x598000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y734400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x73600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x96600y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x165600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x197800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x234600y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x423200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x386400y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x621000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x593400y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x722200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x731400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y761600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x133400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x211600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x271400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y788800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x561200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x768200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x579600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x179400y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x197800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x294400y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y816000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x754400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x414000y816000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y816000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y816000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y843200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y843200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x138000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x230000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y843200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y843200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x460000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x36800y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x170200y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y870400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x262200y870400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y870400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x188600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x381800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y897600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x207000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x59800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x69000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x400200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x335800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x506000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x524400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x368000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x616400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x713000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y924800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x381800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y924800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x892400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x506000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x602600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x621000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -43417,46 +50522,152 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y952000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x285200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x418600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y952000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y952000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x161000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x197800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -43483,8 +50694,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43510,8 +50721,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43537,8 +50748,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43564,7 +50775,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -43599,7 +50811,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -43634,42 +50847,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -43704,8 +50883,40 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43725,13 +50936,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43754,8 +50965,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43778,8 +50989,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43802,8 +51013,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43826,8 +51037,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43850,8 +51061,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43874,8 +51085,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43898,8 +51109,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43922,8 +51133,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43946,8 +51157,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43970,8 +51181,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -43994,8 +51205,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -44018,7 +51229,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -44042,8 +51253,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -44066,8 +51277,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -44090,8 +51301,89 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44117,33 +51409,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44169,7 +51436,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44195,7 +51463,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44221,7 +51490,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44247,7 +51571,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44273,7 +51598,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44299,7 +51625,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44325,7 +51652,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44351,7 +51679,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44377,115 +51706,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -44595,427 +51817,511 @@ wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; supply1 VDD ; supply0 VSS ; -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1128 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1129 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1130 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1131 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1132 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1133 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1134 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1135 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1136 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1137 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1138 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1139 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1140 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1141 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1233 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1142 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1234 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1143 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1144 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1145 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1146 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1147 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1148 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1149 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1150 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1151 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1152 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1153 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1154 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1155 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1156 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1157 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1158 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1159 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1160 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1161 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1162 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1163 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45031,46 +52337,46 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x303600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x340400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y54400 ( @@ -45085,41 +52391,53 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45139,89 +52457,95 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y81600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y81600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y81600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x188600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x225400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x262200y108800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x299000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x846400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x920000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45245,35 +52569,37 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y136000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x533600y136000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x671600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y136000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45289,27 +52615,49 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x285200y163200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x731400y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x768200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x814200y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45333,30 +52681,40 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x501400y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x814200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y190400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y190400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y217600 ( @@ -45371,22 +52729,48 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x257600y217600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y217600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y217600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x694600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y244800 ( @@ -45399,36 +52783,52 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x239200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x331200y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x340400y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y244800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x897000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y244800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x542800y244800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x694600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y272000 ( @@ -45443,35 +52843,43 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x703800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x713000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y272000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x892400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x717600y272000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y272000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45483,31 +52891,51 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x184000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x276000y299200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x349600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y299200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x851000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y299200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y299200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45517,37 +52945,47 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x239200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x483000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x570400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x611800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x607200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x699200y326400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x717600y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x864800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x726800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y326400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x901600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y326400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x938400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45567,25 +53005,31 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x556600y353600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x602600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45597,33 +53041,39 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x285200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x303600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x391000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x395600y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x432400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x414000y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x469200y380800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x828000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x565800y380800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x777400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x809600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45635,40 +53085,46 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x345000y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x381800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x492200y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x616400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x538200y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x634800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x676200y408000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x713000y408000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x749800y408000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x786600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x823400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y408000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x832600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y435200 ( @@ -45679,28 +53135,26 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x542800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x450800y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x579600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y435200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y435200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x841800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y462400 ( @@ -45713,37 +53167,33 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x335800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x331200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y462400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45753,45 +53203,45 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x372600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x381800y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y489600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x524400y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x533600y489600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x680800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x717600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x745200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x740600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45803,103 +53253,127 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x202400y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x253000y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x335800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x368000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x418600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x409400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x519800y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x800400y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y516800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x73600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x82800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x253000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x299000y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x317400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x400200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x450800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x487600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x561200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x552000y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x598000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x588800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x625600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x708400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y571200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x570400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x234600y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x662400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x271400y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x308200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x446200y571200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y571200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -45909,95 +53383,91 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x253000y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x363400y598400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x529000y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x565800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x432400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x538200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y598400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x694600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x713000y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x703800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x722200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x754400y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x763600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y598400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y598400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x92000y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x101200y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x193200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x193200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x239200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x289800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x326600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x437000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x547400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x575000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y625600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x657800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x694600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x740600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x395600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x515200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y625600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x634800y625600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x671600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x708400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x745200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x782000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y625600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -46005,37 +53475,43 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x128800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x174800y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x211600y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x248400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x340400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x349600y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y652800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x450800y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y652800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x478400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x616400y652800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y652800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x708400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -46049,44 +53525,80 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y680000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x561200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x611800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x312800y680000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x464600y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x584200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y680000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x837200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y707200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x128800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x147200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y707200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x345000y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x363400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y707200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y707200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x450800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x469200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x662400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x878600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y734400 ( @@ -46095,27 +53607,101 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x147200y734400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x174800y734400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x156400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x248400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x584200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x285200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x322000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y734400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x358800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x404800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x634800y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x653200y761600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x308200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x400200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x437000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x455400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x593400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x639400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x805000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x841800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x897000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -46133,39 +53719,259 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x312800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x354200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x372600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x418600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x455400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y788800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x492200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x529000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x630200y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x547400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x593400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y788800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x657800y788800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x703800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x749800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x878600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x915400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x423200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x487600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x616400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x736000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x864800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x874000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x924600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x119600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x216200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x326600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x220800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x262200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x289800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x110400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x253000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x653200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x667000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46183,15 +53989,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , - .X ( net_aps_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46209,13 +54013,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46233,19 +54037,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46254,14 +54059,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , - p1 ) ; +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -46269,7 +54074,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46278,16 +54083,18 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , + .X ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , p_abuf0 , - p1 ) ; +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -46295,7 +54102,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46304,15 +54111,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 ) ; input [0:0] Test_en ; @@ -46333,18 +54140,18 @@ supply0 VSS ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , - .X ( net_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , + .X ( BUF_net_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -46364,8 +54171,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46383,19 +54190,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -46404,14 +54211,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46474,13 +54281,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -46523,7 +54330,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -46585,8 +54392,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -46623,14 +54430,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -46641,7 +54448,7 @@ frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -46659,12 +54466,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -46686,9 +54494,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -46696,7 +54504,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -46706,7 +54514,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -46716,40 +54524,41 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , + p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -46769,8 +54578,7 @@ output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; -input p1 ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -46789,104 +54597,104 @@ supply0 VSS ; assign p_abuf1 = p_abuf2 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( fabric_regout[0] ) , - .p_abuf1 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) ) ; -mux_tree_size2_21 mux_fabric_out_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( fabric_regout[0] ) , .p_abuf2 ( p_abuf2 ) ) ; +grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; -mux_tree_size2_22 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; -mux_tree_size2_23 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , +module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , - p_abuf2 , p1 , p2 ) ; + p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -46904,13 +54712,14 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p1 ; -input p2 ; +output p_abuf3 ; +output p_abuf4 ; +input p0 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , @@ -46918,45 +54727,42 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_d .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , .p1 ( p1 ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_2_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46974,13 +54780,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -46998,13 +54804,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47022,19 +54828,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47043,20 +54850,23 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47065,20 +54875,26 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47087,13 +54903,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -47113,7 +54931,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -47133,8 +54951,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47152,19 +54970,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47173,14 +54992,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47243,13 +55062,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -47289,10 +55108,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -47354,8 +55173,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -47390,16 +55209,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -47410,7 +55229,7 @@ frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -47428,12 +55247,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -47455,9 +55275,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p2 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -47465,7 +55285,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -47475,7 +55295,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -47485,40 +55305,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_30 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -47533,7 +55353,10 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -47552,102 +55375,104 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_18 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_19 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_20 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , + .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , + p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -47662,56 +55487,58 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , + .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47729,13 +55556,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47753,13 +55580,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47777,19 +55604,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47798,20 +55626,22 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47820,20 +55650,24 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p2 ) ; +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47842,13 +55676,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -47868,7 +55704,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -47888,8 +55724,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47907,19 +55743,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47928,14 +55765,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -47998,13 +55835,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -48038,19 +55875,19 @@ supply0 VSS ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( @@ -48109,8 +55946,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -48154,7 +55991,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -48165,7 +56002,7 @@ frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -48183,12 +56020,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -48210,9 +56048,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -48220,7 +56058,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -48230,7 +56068,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -48240,40 +56078,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_29 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p0 , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -48288,8 +56126,9 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -48308,102 +56147,102 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_15 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_16 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; -mux_tree_size2_17 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -48418,58 +56257,53 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , - .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -48487,13 +56321,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -48511,13 +56345,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -48535,19 +56369,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , VDD , VSS , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48556,20 +56391,23 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48578,20 +56416,26 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48600,13 +56444,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -48626,7 +56472,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -48646,8 +56492,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -48665,19 +56511,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48686,14 +56533,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -48756,768 +56603,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; -input VDD ; -input VSS ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; - -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; -supply1 VDD ; -supply0 VSS ; - -frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; -supply1 VDD ; -supply0 VSS ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_28 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; -supply1 VDD ; -supply0 VSS ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_12 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_13 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_14 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input VDD ; -input VSS ; -input p0 ; - -supply1 VDD ; -supply0 VSS ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -output [0:16] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -49622,8 +56714,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -49658,16 +56750,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -49678,7 +56770,7 @@ frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -49696,12 +56788,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -49723,9 +56816,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -49733,7 +56826,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -49743,7 +56836,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -49753,40 +56846,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_27 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -49801,7 +56894,11 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -49820,102 +56917,104 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_9 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_10 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_11 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , + .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , + p_abuf3 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -49930,56 +57029,59 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , + .p2 ( p2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -49997,13 +57099,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50021,13 +57123,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50045,19 +57147,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50066,20 +57169,22 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +output p_abuf0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50088,20 +57193,25 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50110,13 +57220,17 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -50136,7 +57250,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -50156,8 +57270,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50175,19 +57289,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , p1 ) ; +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50196,14 +57311,790 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; +input VDD ; +input VSS ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , + VSS , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_sc_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; +supply1 VDD ; +supply0 VSS ; + +assign fabric_regout[0] = fabric_sc_out[0] ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_sc_out ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_sc_in ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_sc_in ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_sc_out ; +output [0:0] ccff_tail ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +supply1 VDD ; +supply0 VSS ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , + p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50266,13 +58157,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -50303,7 +58194,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( @@ -50377,8 +58268,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -50419,10 +58310,10 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -50433,7 +58324,7 @@ frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -50451,12 +58342,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -50478,9 +58370,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p1 ) ; + VSS , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -50488,7 +58380,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -50498,7 +58390,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -50508,40 +58400,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_26 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p1 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -50556,8 +58448,11 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -50576,102 +58471,104 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_6 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -mux_tree_size2_7 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; -mux_tree_size2_8 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p1 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -50686,58 +58583,59 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , - .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50755,13 +58653,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50779,13 +58677,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50803,56 +58701,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -50874,7 +58729,59 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -50894,7 +58801,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -50914,8 +58821,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -50933,12 +58840,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_25 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , VDD , VSS , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -50960,8 +58868,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51024,13 +58932,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -51064,7 +58972,7 @@ supply0 VSS ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( @@ -51135,8 +59043,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -51177,10 +59085,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -51191,7 +59099,7 @@ frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -51209,12 +59117,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -51236,7 +59145,7 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , VSS , p0 ) ; input [0:0] prog_clk ; @@ -51256,7 +59165,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -51266,7 +59175,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_25 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] @@ -51274,32 +59183,32 @@ mux_tree_size2_25 mux_frac_logic_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p0 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -51314,8 +59223,10 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -51334,102 +59245,103 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_3 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_4 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -mux_tree_size2_5 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; -mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf2 , p0 , + p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -51444,58 +59356,54 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , - .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51513,13 +59421,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51537,13 +59445,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51561,19 +59469,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51582,20 +59491,22 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51604,20 +59515,25 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , + p_abuf0 , p_abuf1 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51626,15 +59542,17 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -51654,7 +59572,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , VDD , VSS ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -51674,7 +59592,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module direct_interc ( in , out ) ; +module grid_clb_direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -51682,8 +59600,8 @@ assign out[0] = in[0] ; endmodule -module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb , VDD , VSS ) ; +module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51701,19 +59619,20 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , + p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51722,14 +59641,14 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -51792,13 +59711,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out , VDD , - VSS ) ; +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out , + VDD , VSS ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -51841,7 +59760,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -51903,8 +59822,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out , VDD , VSS ) ; +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out , VDD , VSS ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -51941,14 +59860,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -51959,7 +59878,7 @@ frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail , VDD , VSS ) ; input [0:0] prog_clk ; @@ -51977,12 +59896,13 @@ wire [0:15] frac_lut4_0_sram_inv ; supply1 VDD ; supply0 VSS ; -frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -52004,9 +59924,9 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , VDD , - VSS , p0 ) ; + VSS , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; @@ -52014,7 +59934,7 @@ output [0:1] frac_logic_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -52024,7 +59944,7 @@ wire [0:1] mux_tree_size2_0_sram_inv ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -52034,40 +59954,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_24 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , VDD , - VSS , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -52082,7 +60002,11 @@ output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -52101,102 +60025,104 @@ supply0 VSS ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_0 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_1 mux_fabric_out_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , + .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_2 mux_ff_0_D_0 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , + p_abuf2 , p1 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -52211,62 +60137,68 @@ output [0:0] fle_sc_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule -module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , - clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , - clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , +module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , clb_regout , clb_sc_out , ccff_tail , VDD , VSS , p_abuf0 , p_abuf3 , - p_abuf4 , p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , - p_abuf11 , p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , - p1 , p2 , p3 , p4 ) ; + p_abuf5 , p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , + p_abuf18 , p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , + p_abuf30 , p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -52298,24 +60230,27 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf3 ; -output p_abuf4 ; output p_abuf5 ; output p_abuf6 ; -output p_abuf7 ; output p_abuf8 ; -output p_abuf9 ; output p_abuf10 ; -output p_abuf11 ; output p_abuf12 ; -output p_abuf13 ; output p_abuf14 ; -output p_abuf15 ; output p_abuf16 ; +output p_abuf18 ; +output p_abuf20 ; +output p_abuf22 ; +output p_abuf24 ; +output p_abuf26 ; +output p_abuf28 ; +output p_abuf30 ; +output p_abuf31 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; +input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -52327,11 +60262,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; @@ -52343,65 +60276,70 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; supply1 VDD ; supply0 VSS ; -logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { p_abuf16 , p_abuf3 } ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , + .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { p_abuf4 , clb_O[2] } ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf6 ) , + .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { p_abuf6 , p_abuf7 } ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p2 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf10 ) , + .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , .p0 ( p0 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf14 ) , + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf18 ) , + .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , @@ -52412,20 +60350,22 @@ logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) , .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf22 ) , + .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { p_abuf14 , p_abuf15 } ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf26 ) , + .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , .p0 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , @@ -52436,289 +60376,202 @@ logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , - .p1 ( p2 ) , .p2 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , .p0 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf5 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf16 } ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( clb_O[2] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf7 } ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf6 } ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( clb_O[6] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( clb_O[9] ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( clb_O[10] ) ) ; -direct_interc direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( clb_O[11] ) ) ; -direct_interc direct_interc_12_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf11 } ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf15 } ) ) ; -direct_interc direct_interc_13_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( { p_abuf14 } ) ) ; -direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , - .out ( clb_O[14] ) ) ; -direct_interc direct_interc_15_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( clb_O[15] ) ) ; -direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( { p_abuf21 } ) ) ; +grid_clb_direct_interc direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf29 } ) ) ; +grid_clb_direct_interc direct_interc_15_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( { p_abuf30 } ) ) ; +grid_clb_direct_interc direct_interc_16_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , +grid_clb_direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( clb_I0[2] ) ) ; -direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , +grid_clb_direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( clb_I0[1] ) ) ; -direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , +grid_clb_direct_interc direct_interc_20_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( clb_I0[0] ) ) ; -direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , +grid_clb_direct_interc direct_interc_21_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( clb_I0i ) ) ; -direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , +grid_clb_direct_interc direct_interc_22_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , .out ( clb_regin ) ) ; -direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , +grid_clb_direct_interc direct_interc_23_ ( + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , .out ( clb_sc_in ) ) ; -direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , +grid_clb_direct_interc direct_interc_24_ ( + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , +grid_clb_direct_interc direct_interc_25_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , .out ( clb_I1[2] ) ) ; -direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , +grid_clb_direct_interc direct_interc_26_ ( + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , .out ( clb_I1[1] ) ) ; -direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , +grid_clb_direct_interc direct_interc_27_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , .out ( clb_I1[0] ) ) ; -direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , +grid_clb_direct_interc direct_interc_28_ ( + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , .out ( clb_I1i ) ) ; -direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , +grid_clb_direct_interc direct_interc_29_ ( + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , +grid_clb_direct_interc direct_interc_30_ ( + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , +grid_clb_direct_interc direct_interc_31_ ( + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , +grid_clb_direct_interc direct_interc_32_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , .out ( clb_I2[2] ) ) ; -direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , +grid_clb_direct_interc direct_interc_33_ ( + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( clb_I2[1] ) ) ; -direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , +grid_clb_direct_interc direct_interc_34_ ( + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , .out ( clb_I2[0] ) ) ; -direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , +grid_clb_direct_interc direct_interc_35_ ( + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , .out ( clb_I2i ) ) ; -direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , +grid_clb_direct_interc direct_interc_36_ ( + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , +grid_clb_direct_interc direct_interc_37_ ( + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , +grid_clb_direct_interc direct_interc_38_ ( + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , +grid_clb_direct_interc direct_interc_39_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , .out ( clb_I3[2] ) ) ; -direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , +grid_clb_direct_interc direct_interc_40_ ( + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( clb_I3[1] ) ) ; -direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , +grid_clb_direct_interc direct_interc_41_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , .out ( clb_I3[0] ) ) ; -direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , +grid_clb_direct_interc direct_interc_42_ ( + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , .out ( clb_I3i ) ) ; -direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , +grid_clb_direct_interc direct_interc_43_ ( + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , +grid_clb_direct_interc direct_interc_44_ ( + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , +grid_clb_direct_interc direct_interc_45_ ( + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , +grid_clb_direct_interc direct_interc_46_ ( + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , .out ( clb_I4[2] ) ) ; -direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , +grid_clb_direct_interc direct_interc_47_ ( + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( clb_I4[1] ) ) ; -direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , +grid_clb_direct_interc direct_interc_48_ ( + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , .out ( clb_I4[0] ) ) ; -direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , +grid_clb_direct_interc direct_interc_49_ ( + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , .out ( clb_I4i ) ) ; -direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , +grid_clb_direct_interc direct_interc_50_ ( + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , +grid_clb_direct_interc direct_interc_51_ ( + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , +grid_clb_direct_interc direct_interc_52_ ( + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , +grid_clb_direct_interc direct_interc_53_ ( + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , .out ( clb_I5[2] ) ) ; -direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , +grid_clb_direct_interc direct_interc_54_ ( + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( clb_I5[1] ) ) ; -direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , +grid_clb_direct_interc direct_interc_55_ ( + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , .out ( clb_I5[0] ) ) ; -direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , +grid_clb_direct_interc direct_interc_56_ ( + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , .out ( clb_I5i ) ) ; -direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , +grid_clb_direct_interc direct_interc_57_ ( + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , +grid_clb_direct_interc direct_interc_58_ ( + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , +grid_clb_direct_interc direct_interc_59_ ( + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , +grid_clb_direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , .out ( clb_I6[2] ) ) ; -direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , +grid_clb_direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( clb_I6[1] ) ) ; -direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , +grid_clb_direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , .out ( clb_I6[0] ) ) ; -direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , +grid_clb_direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , .out ( clb_I6i ) ) ; -direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , +grid_clb_direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , +grid_clb_direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , +grid_clb_direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , +grid_clb_direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , .out ( clb_I7[2] ) ) ; -direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_69 } ) , +grid_clb_direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( clb_I7[1] ) ) ; -direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_70 } ) , +grid_clb_direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , .out ( clb_I7[0] ) ) ; -direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_71 } ) , +grid_clb_direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , .out ( clb_I7i ) ) ; -direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_72 } ) , +grid_clb_direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_73 } ) , +grid_clb_direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_74 } ) , +grid_clb_direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , - .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , - .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , - .X ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , - .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , - .X ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , - .X ( p_abuf10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , - .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , - .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , - .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , - .X ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , - .X ( clb_O[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , - .X ( clb_O[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , - .X ( p_abuf11 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , - .X ( clb_O[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , - .X ( p_abuf12 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , - .X ( p_abuf13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , - .X ( clb_O[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , - .X ( clb_O[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , - .X ( clb_O[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , - .X ( p_abuf5 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , - .X ( clb_O[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , - .X ( p_abuf8 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , - .X ( p_abuf9 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52766,7 +60619,9 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_upper , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 , prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , + clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -52847,26 +60702,28 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf1 ; -wire p_abuf14 ; wire p_abuf2 ; -wire p_abuf5 ; -wire p_abuf4 ; -wire ropt_net_143 ; -wire ropt_net_148 ; +wire ropt_net_150 ; +wire ropt_net_141 ; +wire ropt_net_139 ; wire ropt_net_144 ; -wire p_abuf13 ; -wire p_abuf12 ; -wire ropt_net_131 ; -wire ropt_net_130 ; -wire ropt_net_133 ; +wire ropt_net_140 ; +wire p_abuf15 ; +wire ropt_net_147 ; supply1 VDD ; supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; -logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .clb_I0 ( { top_width_0_height_0__pin_0_[0] , top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , @@ -52899,271 +60756,236 @@ logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , - top_width_0_height_0__pin_37_upper[0] , - top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , - aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , - aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , - right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , - ropt_net_131 , ropt_net_130 } ) , - .clb_regout ( { ropt_net_134 } ) , - .clb_sc_out ( { aps_rename_153_ } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( ropt_net_133 ) , .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , - .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , - .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , - .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , - .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , - .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , - .p4 ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1176 ( .VNB ( VSS ) , + .clb_O ( { ropt_net_145 , aps_rename_136_ , + top_width_0_height_0__pin_36_lower[0] , + top_width_0_height_0__pin_37_lower[0] , + top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , + top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , + aps_rename_144_ , aps_rename_145_ , + right_width_0_height_0__pin_44_lower[0] , + right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , + .clb_regout ( { ropt_net_153 } ) , + .clb_sc_out ( { aps_rename_155_ } ) , + .ccff_tail ( { ropt_net_149 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_147 ) , + .p_abuf3 ( ropt_net_150 ) , .p_abuf5 ( p_abuf2 ) , + .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf10 ( ropt_net_141 ) , + .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , + .p_abuf14 ( ropt_net_139 ) , + .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf18 ( ropt_net_144 ) , + .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , + .p_abuf26 ( ropt_net_140 ) , + .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf30 ( p_abuf15 ) , + .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , + .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , + .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1089 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1177 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1090 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1178 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1091 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1179 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1092 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1180 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1093 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1181 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1094 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1182 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1095 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1183 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1096 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1184 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1097 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1185 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1098 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1186 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1099 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1187 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1100 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1188 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1101 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1189 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1102 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1190 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1103 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1191 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1104 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1192 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1105 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1193 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1106 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1194 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1107 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1195 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1108 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1196 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1109 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1197 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1110 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1198 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1111 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1199 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1112 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1200 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1113 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1201 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1114 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1202 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1115 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1203 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1116 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1204 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1117 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1205 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1118 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1206 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1119 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1207 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1120 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1208 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1121 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1209 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1122 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1210 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1123 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1211 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1124 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1212 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1125 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1213 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1126 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1214 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1215 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1216 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 \tapfiller!sky130_fd_sc_hd__tap_2!1217 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , - .X ( aps_rename_130_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , - .X ( aps_rename_131_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , - .X ( aps_rename_133_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , - .X ( aps_rename_134_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , .X ( aps_rename_135_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , - .X ( aps_rename_136_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , - .X ( aps_rename_138_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , - .X ( aps_rename_140_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , - .X ( aps_rename_142_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , - .X ( aps_rename_144_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , - .X ( aps_rename_146_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , - .X ( aps_rename_148_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , - .X ( aps_rename_149_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , - .X ( aps_rename_150_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , - .X ( aps_rename_151_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , - .X ( aps_rename_152_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , .X ( top_width_0_height_0__pin_35_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , - .X ( top_width_0_height_0__pin_36_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_5138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , - .X ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , - .X ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , - .X ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , - .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , - .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , - .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , .X ( bottom_width_0_height_0__pin_50_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , + .X ( aps_rename_154_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , + .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , + .X ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , + .X ( clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , + .X ( prog_clk__FEEDTHRU_3[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y0 ( @@ -53178,183 +61000,211 @@ sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y0 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y0 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y0 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1117800y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y0 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x979800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1016600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y27200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y27200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x377200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x414000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1062600y27200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1071800y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y27200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x423200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x602600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x883200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x901600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x910800y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x952200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x989000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1044200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y54400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x202400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x216200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x239200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y54400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x676200y54400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1025800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x768200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x860200y54400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x349600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x952200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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\xofiller!sky130_fd_sc_hd__fill_2!x648600y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x736000y108800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x404800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x772800y108800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x519800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x878600y108800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x529000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x552000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x151800y163200 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x151800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x248400y163200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x786600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x266800y163200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x276000y163200 ( +sky130_fd_sc_hd__fill_4 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VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x207000y190400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1053400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y190400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x41400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x50600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x115000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x391000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x648600y272000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x823400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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\xofiller!sky130_fd_sc_hd__fill_1!x1012000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1099400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x55200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x133400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x915400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x924600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x961400y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x970600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x979800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y353600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1159200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y353600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y380800 ( +sky130_fd_sc_hd__fill_2 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) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x809600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x818800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x818800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x910800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x933800y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1039600y380800 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y380800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1012000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x984400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1035000y435200 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x956800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1058000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y435200 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x280600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x331200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x124200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x377200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x409400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x427800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x552000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x561200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x170200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x602600y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x211600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x611800y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x299000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x653200y462400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x391000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x846400y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x515200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1035000y462400 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1108600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1127000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y462400 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x782000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1090200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x73600y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1108600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x133400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x184000y489600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x202400y489600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x156400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x216200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x961400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x565800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x584200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x680800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x772800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x901600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x920000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1021200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x27600y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x115000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x276000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x294400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x322000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x409400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x446200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x501400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x607200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x625600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x538200y516800 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x644000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x588800y516800 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x598000y516800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x740600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x690000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x708400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x754400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x984400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1002800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x115000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x234600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x243800y544000 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x795800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x607200y544000 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x317400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x791200y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x414000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x809600y544000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x547400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x584200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x855600y544000 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x676200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x234600y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x36800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x326600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x82800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x377200y761600 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x92000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x510600y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x170200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x529000y761600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x460000y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x777400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x510600y897600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x883200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x519800y897600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1205200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1223600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x299000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x335800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x345000y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x565800y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x395600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x607200y897600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x441600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x478400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 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.VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x266800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x501400y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x510600y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x556600y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x317400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x644000y952000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y952000 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x354200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y952000 ( 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.VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x611800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x648600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y979200 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x685400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x722200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y1006400 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x759000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 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\xofiller!sky130_fd_sc_hd__fill_4!x1113200y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1053400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y1006400 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1090200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x0y1033600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1127000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x18400y1033600 ( +sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1163800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x358800y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x395600y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x432400y1033600 ( +sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1200600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x441600y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x487600y1033600 ( +sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1219000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x496800y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x515200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x533600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x575000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x630200y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x648600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x690000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x699200y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x726800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x759000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x805000y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x933800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x943000y1033600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1113200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x1131600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x0y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x36800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x73600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x110400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x147200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x184000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x220800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x257600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x294400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x331200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x368000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x404800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 \xofiller!sky130_fd_sc_hd__fill_2!x423200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x432400y1060800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x446200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x483000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x519800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x556600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x593400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x630200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x667000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x703800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x740600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x777400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x814200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x851000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x887800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x933800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x970600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1007400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1044200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 \xofiller!sky130_fd_sc_hd__fill_8!x1081000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 \xofiller!sky130_fd_sc_hd__fill_4!x1117800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1136200y1060800 ( +sky130_fd_sc_hd__fill_1 \xofiller!sky130_fd_sc_hd__fill_1!x1228200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -54710,7 +62388,6 @@ wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_5_out ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; @@ -54749,7 +62426,6 @@ wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_1_ccff_tail ; wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; @@ -54785,7 +62461,6 @@ wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; @@ -54933,11 +62608,45 @@ wire [0:19] sb_2__2__0_chanx_left_out ; wire [0:19] sb_2__2__0_chany_bottom_out ; supply1 VDD ; supply0 VSS ; +wire [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:0] prog_clk__FEEDTHRU_2 ; +wire [0:0] prog_clk__FEEDTHRU_3 ; +wire [0:0] prog_clk__FEEDTHRU_4 ; +wire [0:0] prog_clk__FEEDTHRU_5 ; +wire [0:0] prog_clk__FEEDTHRU_6 ; +wire [0:0] prog_clk__FEEDTHRU_7 ; +wire [0:0] prog_clk__FEEDTHRU_8 ; +wire [0:0] prog_clk__FEEDTHRU_9 ; +wire [0:0] prog_clk__FEEDTHRU_10 ; +wire [0:0] prog_clk__FEEDTHRU_11 ; +wire [0:0] prog_clk__FEEDTHRU_12 ; +wire [0:0] prog_clk__FEEDTHRU_13 ; +wire [0:0] prog_clk__FEEDTHRU_14 ; +wire [0:0] prog_clk__FEEDTHRU_15 ; +wire [0:0] prog_clk__FEEDTHRU_16 ; +wire [0:0] prog_clk__FEEDTHRU_17 ; +wire [0:0] prog_clk__FEEDTHRU_18 ; +wire [0:0] prog_clk__FEEDTHRU_19 ; +wire [0:0] prog_clk__FEEDTHRU_20 ; +wire [0:0] Test_en__FEEDTHRU_1 ; +wire [0:0] Test_en__FEEDTHRU_2 ; +wire [0:0] Test_en__FEEDTHRU_3 ; +wire [0:0] Test_en__FEEDTHRU_4 ; +wire [0:0] Test_en__FEEDTHRU_5 ; +wire [0:0] Test_en__FEEDTHRU_6 ; +wire [0:0] clk__FEEDTHRU_1 ; +wire [0:0] clk__FEEDTHRU_2 ; +wire [0:0] clk__FEEDTHRU_3 ; +wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , +grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -54955,7 +62664,7 @@ grid_clb grid_clb_1__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , @@ -55006,15 +62715,19 @@ grid_clb grid_clb_1__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1517 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -55031,8 +62744,8 @@ grid_clb grid_clb_1__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -55084,14 +62797,19 @@ grid_clb grid_clb_1__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_57 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_2729 } ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -55109,7 +62827,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -55160,15 +62878,20 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_911 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_1315 } ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -55185,8 +62908,8 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -55238,13 +62961,17 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; +sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -55258,8 +62985,7 @@ sb_0__0_ sb_0__0_ ( .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__1_ sb_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -55277,9 +63003,9 @@ sb_0__1_ sb_0__1_ ( .chany_top_out ( sb_0__1__0_chany_top_out ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -55296,11 +63022,10 @@ sb_0__2_ sb_0__2_ ( .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , +sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , @@ -55329,11 +63054,19 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -55375,9 +63108,14 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_tail ( sb_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -55412,12 +63150,14 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , .VDD ( VDD ) , .VSS ( VSS ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -55439,8 +63179,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -55474,9 +63213,10 @@ sb_2__1_ sb_2__1_ ( .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -55501,10 +63241,10 @@ sb_2__2_ sb_2__2_ ( .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .prog_clk ( { ctsbuf_net_3032 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -55538,11 +63278,13 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_35 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -55576,11 +63318,12 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1416 } ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -55602,13 +63345,12 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , - .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -55630,12 +63372,12 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , - .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , - .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -55665,11 +63407,11 @@ cbx_1__2_ cbx_1__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -55699,11 +63441,10 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , +cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -55717,9 +63458,9 @@ cby_0__1_ cby_0__1_ ( .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -55733,9 +63474,9 @@ cby_0__1_ cby_0__2_ ( .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; +cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -55757,9 +63498,12 @@ cby_1__1_ cby_1__1_ ( .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -55781,9 +63525,12 @@ cby_1__1_ cby_1__2_ ( .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -55813,9 +63560,9 @@ cby_2__1_ cby_2__1_ ( .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_46 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -55845,7 +63592,8 @@ cby_2__1_ cby_2__2_ ( .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; @@ -55853,11 +63601,8 @@ direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , .out ( direct_interc_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -direct_interc_5 direct_interc_5_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_5_out ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_0 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1 ( .VNB ( VSS ) , @@ -58034,222 +65779,15 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1086 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1087 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1088 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1089 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1090 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1091 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1092 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1093 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1094 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1095 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1096 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1097 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1098 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1099 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1100 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1101 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1102 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1103 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1104 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1105 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1106 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1107 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1108 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1109 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1110 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1111 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1112 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1113 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1114 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1115 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1116 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1117 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1118 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1119 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1120 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1121 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1122 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1123 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1124 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1125 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1126 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1127 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1128 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1129 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1130 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1131 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1132 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1133 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1134 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1135 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1136 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1137 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1138 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1139 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1140 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1141 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1142 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1143 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1144 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1145 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1146 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1147 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1148 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1149 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1150 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1151 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1152 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1153 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1154 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1155 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1156 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1157 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1158 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1159 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1160 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1161 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1162 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1163 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1164 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1165 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1166 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1167 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1168 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1169 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1170 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1171 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1172 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_24 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_810 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_911 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1012 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_1517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( - .A ( SYNOPSYS_UNCONNECTED_31 ) , .Y ( SYNOPSYS_UNCONNECTED_32 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( - .A ( SYNOPSYS_UNCONNECTED_33 ) , .Y ( SYNOPSYS_UNCONNECTED_34 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( - .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( - .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1618 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1719 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , + .Y ( ctsbuf_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( + .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( @@ -58258,75 +65796,98 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , + .Y ( ctsbuf_net_1214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , + .Y ( ctsbuf_net_1315 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( + .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , + .Y ( ctsbuf_net_1517 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( +sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , + .Y ( ctsbuf_net_2729 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( + .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , + .Y ( ctsbuf_net_3032 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y0 ( +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( + .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y0 ( +sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , + .Y ( ctsbuf_net_3436 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_3537 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58348,7 +65909,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58380,89 +65943,89 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58488,61 +66051,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58576,7 +66139,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -58596,45 +66161,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -58660,373 +66227,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59046,72 +66611,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y54400 ( @@ -59132,7 +66697,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59216,9 +66783,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59246,7 +66811,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59324,9 +66891,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59360,7 +66925,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59406,19 +66973,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -59444,373 +67011,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y81600 ( .VGND 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xofiller_sky130_fd_sc_hd__fill_8_x5469400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -59830,72 +67395,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y108800 ( @@ -59916,7 +67481,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60000,13 +67567,11 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3408600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60030,7 +67595,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60062,53 +67629,53 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4439000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4457400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60142,7 +67709,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60188,19 +67757,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -60226,373 +67795,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y136000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2709400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y136000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3445400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y136000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4218200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y136000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4954200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y136000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5727000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60612,72 +68179,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y163200 ( @@ -60698,7 +68265,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60782,9 +68351,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60812,7 +68379,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60890,9 +68459,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60926,7 +68493,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -60972,19 +68541,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -61010,373 +68579,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y190400 ( +sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x3187800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x3960600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x4733400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61396,72 +68963,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y217600 ( @@ -61482,7 +69049,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61566,9 +69135,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61596,7 +69163,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61674,9 +69243,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61710,7 +69277,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -61756,19 +69325,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -61794,373 +69363,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y244800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1826200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y244800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2599000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y244800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3335000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y244800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4107800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_4_x4880600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x5616600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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+sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62180,72 +69747,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y272000 ( @@ -62266,7 +69833,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62350,9 +69919,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62380,7 +69947,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62458,9 +70027,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62494,7 +70061,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62540,19 +70109,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -62578,373 +70147,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y299200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3298200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y299200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4071000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y299200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4843800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -62964,72 +70531,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y326400 ( @@ -63050,7 +70617,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63134,9 +70703,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63164,7 +70731,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63242,9 +70811,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63278,7 +70845,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63324,19 +70893,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -63362,373 +70931,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1936600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2709400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3445400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4218200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4954200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y353600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5727000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63748,72 +71315,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y380800 ( @@ -63834,7 +71401,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63918,9 +71487,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -63948,7 +71515,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64026,9 +71595,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64062,7 +71629,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64108,19 +71677,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -64146,373 +71715,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y408000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3187800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y408000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3960600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y408000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4733400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y408000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5469400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64532,65 +72099,71 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1117800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1228200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1265000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1301800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1338600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1375400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64612,7 +72185,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64696,9 +72271,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64726,7 +72299,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64804,9 +72379,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64840,7 +72413,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -64886,19 +72461,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -64924,373 +72499,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y462400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2635800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y462400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3371800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y462400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4144600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y462400 ( 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xofiller_sky130_fd_sc_hd__fill_2_x4899000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y462400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x6426200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65310,72 +72883,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y489600 ( @@ -65396,7 +72969,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65480,9 +73055,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65510,7 +73083,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65588,9 +73163,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65624,7 +73197,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -65670,19 +73245,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -65708,373 +73283,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y516800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4071000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y516800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4843800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y516800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5579800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66094,72 +73667,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y544000 ( @@ -66180,7 +73753,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66264,9 +73839,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66294,7 +73867,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66372,9 +73947,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66408,7 +73981,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66454,19 +74029,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -66492,373 +74067,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y571200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2709400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y571200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3445400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y571200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4218200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -66878,72 +74451,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y598400 ( @@ -66964,7 +74537,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67048,9 +74623,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67078,7 +74651,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67156,9 +74731,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67192,7 +74765,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67238,19 +74813,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -67276,373 +74851,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y625600 ( 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.VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x5524600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67662,72 +75235,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y652800 ( @@ -67748,7 +75321,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67832,9 +75407,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67862,7 +75435,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67940,9 +75515,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -67976,7 +75549,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68022,19 +75597,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -68060,373 +75635,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y680000 ( 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xofiller_sky130_fd_sc_hd__fill_4_x4880600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68446,72 +76019,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y707200 ( @@ -68532,7 +76105,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68616,9 +76191,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68646,7 +76219,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68724,9 +76299,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68760,7 +76333,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -68806,19 +76381,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -68844,373 +76419,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1789400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2562200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3298200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4071000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4843800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y734400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5579800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69230,72 +76803,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y761600 ( @@ -69316,7 +76889,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69400,9 +76975,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69430,7 +77003,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69508,9 +77083,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69544,7 +77117,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -69590,19 +77165,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -69628,373 +77203,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y788800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3445400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y788800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4218200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y788800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4954200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70014,72 +77587,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y816000 ( @@ -70100,7 +77673,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70184,9 +77759,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70214,7 +77787,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70292,9 +77867,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70328,7 +77901,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70374,19 +77949,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -70412,373 +77987,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1679000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2451800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3187800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3960600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4733400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5469400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y843200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x6242200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70798,72 +78371,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y870400 ( @@ -70884,7 +78457,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70968,9 +78543,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -70998,7 +78571,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71076,9 +78651,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71112,7 +78685,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71158,19 +78733,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -71196,373 +78771,375 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y897600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3298200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y897600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4034200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y897600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4807000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y897600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5543000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -71582,322 +79159,86 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2750800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y924800 ( @@ -71942,19 +79283,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -71980,374 +79321,130 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2723200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2792200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y952000 ( @@ -72366,322 +79463,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y979200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y979200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y979200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y979200 ( @@ -72726,19 +79589,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y979200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y979200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y979200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -72764,374 +79627,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1006400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1006400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1006400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1006400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1006400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1006400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1006400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1006400 ( @@ -73150,322 +79767,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1033600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1033600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1033600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1033600 ( @@ -73510,19 +79893,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1033600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1033600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1033600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1033600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -73548,374 +79931,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1060800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1060800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y1060800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1060800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1060800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1060800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1060800 ( @@ -73934,322 +80071,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1088000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1088000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2819800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4880600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1088000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1088000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1088000 ( @@ -74294,19 +80197,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1088000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1088000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1088000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1088000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -74332,374 +80235,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1115200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1115200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1115200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1115200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1115200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1115200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1115200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1115200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1115200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1115200 ( @@ -74718,165 +80375,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1142400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1142400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1142400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1142400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1142400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1142400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1142400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1142400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1142400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -74902,140 +80539,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1169600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1169600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1169600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1169600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1169600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1169600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1169600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1169600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1169600 ( @@ -75054,165 +80679,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1196800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1196800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1196800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1196800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1196800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1196800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1196800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1196800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1196800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -75238,140 +80843,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1224000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1224000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1224000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1224000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1224000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1224000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1224000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1224000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1224000 ( @@ -75390,165 +80983,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1251200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1251200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1251200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1251200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1251200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1251200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1251200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1251200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1251200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -75574,140 +81147,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1278400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1278400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1278400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1278400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1278400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1278400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1278400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1278400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1278400 ( @@ -75726,165 +81287,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1305600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1305600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1305600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1305600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1305600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1305600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1305600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1305600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1305600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -75910,140 +81451,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1332800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1332800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1332800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1332800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1332800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1332800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1332800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1332800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1332800 ( @@ -76062,165 +81591,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1360000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1360000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1360000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1360000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1360000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1360000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1360000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1360000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1360000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -76246,140 +81755,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1387200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1387200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1387200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1387200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1387200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1387200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1387200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1387200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1387200 ( @@ -76398,165 +81895,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1414400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1414400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1414400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1414400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1414400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1414400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1414400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1414400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1414400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -76582,140 +82059,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1441600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1441600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1441600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1441600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1441600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1441600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1441600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1441600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1441600 ( @@ -76734,165 +82199,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1468800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1468800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1468800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1468800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1468800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1468800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1468800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1468800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1468800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -76918,140 +82363,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1496000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1496000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1496000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1496000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1496000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1496000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1496000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1496000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1496000 ( @@ -77070,165 +82503,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1523200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1523200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1523200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1523200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1523200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1523200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1523200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1523200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1523200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -77254,140 +82667,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1550400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1550400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1550400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1550400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1550400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1550400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1550400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1550400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1550400 ( @@ -77406,165 +82807,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1577600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1577600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1577600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1577600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1577600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1577600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1577600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1577600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1577600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -77590,140 +82971,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1604800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1604800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1604800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1604800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1604800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1604800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1604800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1604800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1604800 ( @@ -77742,165 +83111,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1632000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1632000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1632000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1632000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1632000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1632000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1632000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1632000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1632000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -77926,140 +83275,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1659200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1659200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1659200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1659200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1659200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1659200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1659200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1659200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1659200 ( @@ -78078,165 +83415,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1686400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1686400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1686400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1686400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1686400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1686400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1686400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1686400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1686400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -78262,140 +83579,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1713600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1713600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1713600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1713600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1713600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1713600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1713600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1713600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1713600 ( @@ -78414,165 +83719,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1740800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1740800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1740800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1740800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1740800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1740800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1740800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1740800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1740800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -78598,144 +83883,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1768000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1768000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1768000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1768000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1768000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1768000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1768000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1768000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1768000 ( @@ -78754,285 +84031,289 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y1795200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y1795200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1795200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1795200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1795200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1795200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1795200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1795200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -79058,272 +84339,280 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1822400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y1822400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y1822400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1822400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1822400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1822400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1822400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1822400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1822400 ( @@ -79342,295 +84631,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1849600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y1849600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1849600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2277000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2295400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2304600y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2327600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2364400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2401200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2438000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2474800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2511600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2548400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2585200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2622000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2658800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2695600y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2769200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2806000y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2842800y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y1849600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1849600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1849600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1849600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1849600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1849600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -79656,276 +84795,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1876800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y1876800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y1876800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y1876800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1876800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1876800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2433400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2442600y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2465600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2502400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2539200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2576000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2612800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2649600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2686400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2796800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2833600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2870400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2907200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2944000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2980800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3974400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4011200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4048000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4084800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4121600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4158400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4195200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4232000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4268800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4305600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4324000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1876800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1876800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1876800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1876800 ( @@ -79944,157 +84943,257 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1904000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y1904000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3808800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y1904000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y1904000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y1904000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y1904000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1904000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1904000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1904000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1904000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -80120,149 +85219,241 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3698400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3749000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3785800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y1931200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y1931200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y1931200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y1931200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y1931200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1931200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y1931200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1931200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -80282,202 +85473,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y1958400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y1958400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1958400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y1958400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y1958400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y1958400 ( @@ -80522,19 +85599,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y1958400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y1958400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1958400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1958400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -80560,248 +85637,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1985600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y1985600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y1985600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y1985600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y1985600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y1985600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y1985600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y1985600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y1985600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y1985600 ( @@ -80820,202 +85777,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2012800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2012800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2012800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2012800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2012800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2012800 ( @@ -81060,19 +85903,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2012800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2012800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2012800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2012800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -81098,254 +85941,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2040000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2040000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2040000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2040000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2040000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2040000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2040000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2040000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2040000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2040000 ( @@ -81364,157 +86081,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2067200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2067200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2067200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2067200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2067200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2067200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2067200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2067200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -81540,140 +86245,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2094400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2094400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2094400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2094400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2094400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2094400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2094400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2094400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2094400 ( @@ -81692,157 +86385,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2121600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2121600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2121600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2121600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2121600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2121600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2121600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2121600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -81868,140 +86549,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2148800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2148800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2148800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2148800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2148800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2148800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2148800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2148800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2148800 ( @@ -82020,157 +86689,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2176000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2176000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2176000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2176000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2176000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2176000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2176000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2176000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -82196,140 +86853,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2203200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2203200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2203200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2203200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2203200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2203200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2203200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2203200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2203200 ( @@ -82348,157 +86993,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2230400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2230400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2230400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2230400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2230400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2230400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2230400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2230400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -82524,140 +87157,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2257600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2257600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2257600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2257600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2257600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2257600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2257600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2257600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2257600 ( @@ -82676,157 +87297,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2284800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2284800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2284800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2284800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2284800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2284800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2284800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2284800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -82852,140 +87461,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2312000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2312000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2312000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2312000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2312000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2312000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2312000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2312000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2312000 ( @@ -83004,157 +87601,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2339200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2339200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2339200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2339200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2339200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2339200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2339200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2339200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -83180,140 +87765,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2366400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2366400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2366400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2366400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2366400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2366400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2366400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2366400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2366400 ( @@ -83332,157 +87905,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2393600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2393600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2393600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2393600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2393600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2393600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2393600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2393600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -83508,140 +88069,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2420800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2420800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2420800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2420800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2420800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2420800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2420800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2420800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2420800 ( @@ -83660,157 +88209,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2448000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2448000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2448000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2448000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2448000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2448000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2448000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2448000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -83836,140 +88373,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2475200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2475200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2475200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2475200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2475200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2475200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2475200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2475200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2475200 ( @@ -83988,157 +88513,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2502400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2502400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2502400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2502400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2502400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2502400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2502400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2502400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -84164,140 +88677,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2529600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2529600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2529600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2529600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2529600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2529600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2529600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2529600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2529600 ( @@ -84316,157 +88817,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2556800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2556800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2556800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2556800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2556800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2556800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2556800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2556800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -84492,140 +88981,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2584000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2584000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2584000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2584000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2584000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2584000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2584000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2584000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2584000 ( @@ -84644,157 +89121,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2611200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2611200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2611200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2611200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2611200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2611200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2611200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2611200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -84820,140 +89285,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2638400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2638400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2638400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2638400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2638400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2638400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2638400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2638400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2638400 ( @@ -84972,157 +89425,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2665600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2665600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2665600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2665600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2665600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2665600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2665600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2665600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -85148,140 +89589,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2692800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2692800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2692800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2692800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2692800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2692800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2692800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2692800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2692800 ( @@ -85300,157 +89737,259 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2720000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y2720000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2720000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2720000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2720000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y2720000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2720000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2720000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2720000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2720000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -85476,139 +90015,241 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3698400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3735200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3772000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2747200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3808800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y2747200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2747200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y2747200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2747200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -85628,157 +90269,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2774400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2774400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2774400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2774400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2774400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2774400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2774400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2774400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -85804,150 +90433,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2801600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2801600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2801600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2801600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2801600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2801600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2801600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2801600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2801600 ( @@ -85966,200 +90581,232 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2828800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y2828800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2828800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4958800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2828800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5018600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5055400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5092200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5129000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5165800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5202600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5239400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5276200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2828800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2828800 ( @@ -86204,19 +90851,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2828800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2828800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2828800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2828800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -86242,248 +90889,280 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2856000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2856000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2856000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2856000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2856000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y2856000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2856000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y2856000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y2856000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y2856000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2856000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2856000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2856000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2856000 ( @@ -86502,204 +91181,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y2883200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1458200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1485800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1522600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1559400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1596200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1633000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1669800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1706600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1743400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1780200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1817000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1853800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2883200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2883200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2883200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2883200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2883200 ( @@ -86744,19 +91307,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2883200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2883200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2883200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2883200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -86782,254 +91345,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2910400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2910400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y2910400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y2910400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2910400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2910400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y2910400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2910400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2910400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2910400 ( @@ -87048,157 +91485,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2937600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2937600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2937600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2937600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2937600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2937600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2937600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2937600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -87224,148 +91649,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y2964800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y2964800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2964800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y2964800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y2964800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y2964800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y2964800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2964800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2964800 ( @@ -87384,285 +91789,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y2992000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y2992000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y2992000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y2992000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y2992000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y2992000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y2992000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y2992000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y2992000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -87688,272 +91953,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3019200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3019200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3019200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3019200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3019200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3019200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3019200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3019200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3019200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3019200 ( @@ -87972,289 +92093,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3046400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3046400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3046400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3046400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3046400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3046400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3046400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3046400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3046400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -88280,272 +92257,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3073600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3073600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3073600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3073600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3073600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3073600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3073600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3073600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3073600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3073600 ( @@ -88564,165 +92397,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3100800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3100800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3100800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3100800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3100800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3100800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3100800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3100800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3100800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -88748,140 +92561,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3128000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3128000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3128000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3128000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3128000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3128000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3128000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3128000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3128000 ( @@ -88900,165 +92701,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3155200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3155200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3155200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3155200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3155200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3155200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3155200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3155200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3155200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -89084,140 +92865,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3182400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3182400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3182400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3182400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3182400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3182400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3182400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3182400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3182400 ( @@ -89236,165 +93005,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3209600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3209600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3209600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3209600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3209600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3209600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3209600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3209600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3209600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -89420,140 +93169,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3236800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3236800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3236800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3236800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3236800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3236800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3236800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3236800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3236800 ( @@ -89572,165 +93309,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3264000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1007400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1016600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3264000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3264000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3264000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3264000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3264000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3264000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3264000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3264000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -89756,140 +93473,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3291200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3291200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3291200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3291200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3291200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3291200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3291200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3291200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3291200 ( @@ -89908,165 +93613,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3318400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3318400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3318400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3318400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3318400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3318400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3318400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3318400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3318400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -90092,140 +93777,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3345600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3345600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3345600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3345600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3345600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3345600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3345600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3345600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3345600 ( @@ -90244,165 +93917,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3372800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3372800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3372800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3372800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3372800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3372800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3372800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3372800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3372800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -90428,140 +94081,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3400000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3400000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3400000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3400000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3400000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3400000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3400000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3400000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3400000 ( @@ -90580,165 +94221,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3427200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3427200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3427200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3427200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3427200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3427200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3427200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3427200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3427200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -90764,140 +94385,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3454400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3454400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3454400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3454400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3454400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3454400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3454400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3454400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3454400 ( @@ -90916,165 +94525,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3481600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3481600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3481600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3481600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3481600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3481600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3481600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3481600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3481600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91100,140 +94689,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3508800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3508800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3508800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3508800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3508800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3508800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3508800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3508800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3508800 ( @@ -91252,165 +94829,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3536000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3536000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3536000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3536000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3536000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3536000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3536000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3536000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3536000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91436,140 +94993,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3563200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3563200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3563200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3563200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3563200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3563200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3563200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3563200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3563200 ( @@ -91588,165 +95133,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3590400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3590400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3590400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3590400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3590400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3590400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3590400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3590400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3590400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -91772,140 +95297,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3617600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3617600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3617600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3617600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3617600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3617600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3617600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3617600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3617600 ( @@ -91924,165 +95437,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3644800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3644800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3644800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3644800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3644800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3644800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3644800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3644800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3644800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -92108,140 +95601,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3672000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3672000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3672000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3672000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3672000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3672000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3672000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3672000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3672000 ( @@ -92260,165 +95741,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3699200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y3699200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3699200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3699200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3699200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3699200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3699200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3699200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3699200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -92444,144 +95905,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3726400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3726400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3726400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3726400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3726400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3726400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3726400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3726400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3726400 ( @@ -92600,75 +96053,75 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2019400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -92688,203 +96141,201 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3753600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3969800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3979000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y3753600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3753600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3753600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3753600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3753600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3753600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3753600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3753600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -92910,272 +96361,276 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3780800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2856600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2875000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2884200y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2925600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2962400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3780800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3780800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4917400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4935800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4945000y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4986400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5023200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3780800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3780800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3780800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3780800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3780800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3780800 ( @@ -93194,289 +96649,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3808000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y3808000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3808000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y3808000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3808000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3808000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3808000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3808000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3808000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -93502,272 +96813,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3835200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y3835200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y3835200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y3835200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3835200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3835200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3864000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3900800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3937600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3956000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3835200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3835200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3835200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3835200 ( @@ -93786,157 +96961,259 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3330400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3348800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3862400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3862400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3730600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3767400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3804200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y3862400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y3862400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y3862400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y3862400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y3862400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3862400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3862400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3862400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3862400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -93962,149 +97239,235 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3256800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3293600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3330400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3367200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3404000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3440800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3477600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3514400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3551200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3588000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3624800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3661600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3698400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y3889600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3889600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y3889600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3889600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -94124,202 +97487,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3916800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3916800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3916800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3916800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3916800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3916800 ( @@ -94364,19 +97613,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3916800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3916800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3916800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3916800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -94402,248 +97651,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3944000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3944000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3944000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y3944000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y3944000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y3944000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3944000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3944000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3944000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3944000 ( @@ -94662,202 +97791,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y3971200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y3971200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3726000y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3971200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3971200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3971200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3971200 ( @@ -94902,19 +97917,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y3971200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y3971200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3971200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3971200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -94940,254 +97955,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y3998400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y3998400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y3998400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y3998400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y3998400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y3998400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y3998400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y3998400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y3998400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y3998400 ( @@ -95206,157 +98095,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4025600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4025600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4025600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4025600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4025600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4025600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4025600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4025600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95382,140 +98259,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4052800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4052800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4052800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4052800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4052800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4052800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4052800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4052800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4052800 ( @@ -95534,157 +98399,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4080000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4080000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4080000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4080000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4080000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4080000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4080000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4080000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -95710,140 +98563,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4107200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4107200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4107200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4107200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4107200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4107200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4107200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4107200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4107200 ( @@ -95862,157 +98703,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4134400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4134400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4134400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4134400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4134400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4134400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4134400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4134400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96038,140 +98867,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4161600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4161600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4161600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4161600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4161600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4161600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4161600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4161600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4161600 ( @@ -96190,157 +99007,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4188800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4188800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4188800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4188800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4188800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4188800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4188800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4188800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96366,140 +99171,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4216000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4216000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4216000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4216000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4216000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4216000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4216000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4216000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4216000 ( @@ -96518,157 +99311,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4243200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4243200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4243200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4243200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4243200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4243200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4243200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4243200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -96694,140 +99475,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4270400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4270400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4270400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4270400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4270400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4270400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4270400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4270400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4270400 ( @@ -96846,157 +99615,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4297600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4297600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4297600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4297600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4297600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4297600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4297600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4297600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97022,140 +99779,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4324800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4324800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4324800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4324800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4324800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4324800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4324800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4324800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4324800 ( @@ -97174,157 +99919,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4352000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4352000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4352000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4352000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4352000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4352000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4352000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4352000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97350,140 +100083,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4379200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4379200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4379200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4379200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4379200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4379200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4379200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4379200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4379200 ( @@ -97502,157 +100223,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4406400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4406400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4406400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4406400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4406400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4406400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4406400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4406400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -97678,140 +100387,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4433600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4433600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4433600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4433600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4433600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4433600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4433600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4433600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4433600 ( @@ -97830,157 +100527,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4460800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4460800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4460800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4460800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4460800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4460800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4460800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4460800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98006,140 +100691,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4488000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4488000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4488000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4488000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4488000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4488000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4488000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4488000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4488000 ( @@ -98158,157 +100831,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4515200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4515200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4515200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4515200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4515200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4515200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4515200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4515200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98334,140 +100995,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4542400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4542400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4542400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4542400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4542400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4542400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4542400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4542400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4542400 ( @@ -98486,157 +101135,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4569600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4569600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4569600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4569600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4569600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4569600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4569600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4569600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98662,140 +101299,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4596800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4596800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4596800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4596800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4596800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4596800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4596800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4596800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4596800 ( @@ -98814,157 +101439,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4624000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4624000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4624000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4624000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4624000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4624000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4624000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4624000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -98990,140 +101603,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4651200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4651200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4651200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4651200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4651200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4651200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4651200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4651200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4651200 ( @@ -99142,157 +101751,259 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1274200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1292600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3220000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3238400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4678400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3247600y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3270600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3307400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3344200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y4678400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4678400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4678400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4678400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y4678400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4678400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4678400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4678400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4678400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99318,139 +102029,245 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1752600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1761800y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2999200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3036000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3072800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3109600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3146400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3183200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3220000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3256800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3275200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3813400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3822600y4705600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5060000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5096800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5133600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5170400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5207200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5244000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5280800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5317600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5354400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4705600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5391200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4705600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5409600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4705600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5418800y4705600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4705600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y4705600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4705600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -99470,157 +102287,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4732800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4732800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4732800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4732800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4732800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4732800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4732800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4732800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -99646,150 +102451,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4760000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1702000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1738800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1757200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3045200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3063600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3818000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4760000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5106000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4760000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5124400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4760000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4760000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4760000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4760000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4760000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4760000 ( @@ -99808,202 +102599,234 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3703000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4659800y4787200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4678200y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3726000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4701200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3762800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4738000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3799600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4848400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4885200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4903600y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4787200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4787200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4787200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4787200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4787200 ( @@ -100048,19 +102871,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4787200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4787200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4787200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4787200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -100086,248 +102909,282 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4814400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4814400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1844600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1692800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1729600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1766400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4814400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1803200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3339600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3376400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3413200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3450000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3486800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3523600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3560400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3597200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3634000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3670800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3707600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5290000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5326800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5363600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5400400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5437200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5474000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5510800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5547600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5584400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5621200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5658000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4814400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4814400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1812400y4814400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4814400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3040600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3059000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3068200y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3790400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3827200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3864000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3873200y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4659800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4678200y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4710400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4747200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4857600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4894400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4903600y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5101400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5119800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5129000y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4814400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4814400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4814400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4814400 ( @@ -100346,202 +103203,88 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y4841600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4841600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4841600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4841600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4841600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4841600 ( @@ -100586,19 +103329,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4841600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4841600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4841600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4841600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -100624,254 +103367,126 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4868800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4868800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1863000y4868800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3008400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3045200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3082000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3118800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3155600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3192400y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3229200y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3266000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3302800y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3339600y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3358000y4868800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4868800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4868800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3813400y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4958800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4995600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5032400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5069200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5106000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5142800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5179600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5216400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5253200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5290000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5308400y4868800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4868800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4868800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4868800 ( @@ -100890,157 +103505,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4896000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4896000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4896000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4896000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4896000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4896000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4896000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4896000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -101066,148 +103669,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4923200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4923200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4923200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1803200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1840000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1858400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3017600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3054400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3072800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3753600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3790400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3808800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4968000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5004800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5023200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4923200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4923200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4923200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4923200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4923200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4923200 ( @@ -101226,285 +103809,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y4950400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y4950400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y4950400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1927400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1964200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2001000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2037800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2074600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2111400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2148200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2185000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2221800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2258600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2295400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2332200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2369000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y4950400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y4950400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y4950400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y4950400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4950400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4950400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -101530,272 +103973,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y4977600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y4977600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y4977600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y4977600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y4977600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y4977600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y4977600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y4977600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y4977600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y4977600 ( @@ -101814,289 +104113,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5004800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1867600y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1886000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1895200y5004800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5004800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1909000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1945800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1982600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2019400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2056200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2093000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2129800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2166600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2203400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2240200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2277000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2313800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2350600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2387400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2424200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2461000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2497800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2534600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2571400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2608200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2645000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2681800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2718600y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2755400y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2792200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2829000y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2865800y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2884200y5004800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2921000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2957800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2994600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3031400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3068200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3818000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3836400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3845600y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3859400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3896200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3933000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3969800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4006600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4043400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4080200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4117000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4153800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4190600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4227400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4264200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4301000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4337800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4374600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4411400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4448200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4485000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4521800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4558600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4595400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4632200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4669000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4705800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4742600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4779400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4816200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4834600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4871400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4908200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4945000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4981800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5018600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5004800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5004800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5004800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5004800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5004800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -102122,272 +104277,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5032000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5032000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5032000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1794000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1830800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1867600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1904400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1941200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2051600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2088400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2125200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2162000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2198800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2235600y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2272400y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2309200y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2346000y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2382800y5032000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5032000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5032000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3059000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x3077400y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3744400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3781200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3818000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3854800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3891600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4002000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4075600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4112400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4149200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4186000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4222800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4259600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4296400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4333200y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5009400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5027800y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5032000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5032000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5032000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5032000 ( @@ -102406,165 +104417,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5059200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5059200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5059200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5059200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5059200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5059200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5059200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5059200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5059200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -102590,140 +104581,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5086400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5086400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5086400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5086400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5086400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5086400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5086400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5086400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5086400 ( @@ -102742,165 +104721,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5113600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5113600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5113600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5113600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5113600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5113600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5113600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5113600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5113600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -102926,140 +104885,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5140800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5140800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5140800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5140800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5140800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5140800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5140800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5140800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5140800 ( @@ -103078,165 +105025,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5168000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5168000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5168000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5168000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5168000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5168000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5168000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5168000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5168000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -103262,140 +105189,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5195200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5195200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5195200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5195200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5195200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5195200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5195200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5195200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5195200 ( @@ -103414,165 +105329,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5222400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5222400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5222400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5222400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5222400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5222400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5222400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5222400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5222400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -103598,140 +105493,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5249600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5249600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5249600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5249600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5249600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5249600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5249600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5249600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5249600 ( @@ -103750,165 +105633,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5276800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5276800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5276800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5276800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5276800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5276800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5276800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5276800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5276800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -103934,140 +105797,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5304000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5304000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5304000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5304000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5304000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5304000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5304000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5304000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5304000 ( @@ -104086,165 +105937,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5331200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5331200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5331200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5331200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5331200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5331200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5331200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5331200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5331200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -104270,140 +106101,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5358400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5358400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5358400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5358400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5358400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5358400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5358400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5358400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5358400 ( @@ -104422,165 +106241,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5385600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5385600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5385600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5385600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5385600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5385600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5385600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5385600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5385600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -104606,140 +106405,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5412800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5412800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5412800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5412800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5412800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5412800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5412800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5412800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5412800 ( @@ -104758,165 +106545,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5440000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5440000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5440000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5440000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5440000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5440000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5440000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5440000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5440000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -104942,140 +106709,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5467200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5467200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5467200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5467200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5467200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5467200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5467200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5467200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5467200 ( @@ -105094,165 +106849,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5494400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5494400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5494400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5494400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5494400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5494400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5494400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5494400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5494400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -105278,140 +107013,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5521600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5521600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5521600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5521600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5521600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5521600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5521600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5521600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5521600 ( @@ -105430,165 +107153,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5548800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5548800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5548800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5548800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5548800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5548800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5548800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5548800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5548800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -105614,140 +107317,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5576000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5576000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5576000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5576000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5576000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5576000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5576000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5576000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5576000 ( @@ -105766,165 +107457,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5603200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5603200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5603200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5603200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5603200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5603200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5603200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5603200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5603200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -105950,140 +107621,128 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5630400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5630400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1108600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5630400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1968800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2014800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2005600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2723200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2861200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2760000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3928400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4029600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3965200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4066400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4784000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4811600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4820800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5768400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5805200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5842000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5878800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5915600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5952400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5989200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6026000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6062800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6099600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6136400y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6173200y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6210000y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6246800y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5630400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5630400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5630400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5630400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5630400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5630400 ( @@ -106102,165 +107761,145 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y5657600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5657600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5924800y5657600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5934000y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5657600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6288200y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6325000y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6361800y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6398600y5657600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6435400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6472200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6509000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6545800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6582600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6619400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6656200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6693000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6729800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6766600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5657600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5657600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5657600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5657600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -106286,158 +107925,136 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x979800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x998200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1117800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y5684800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1007400y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1987200y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1978000y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2024000y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2014800y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2042400y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2033200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2824400y5684800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2732400y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2861200y5684800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2769200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2870400y5684800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2787600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4038800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4075600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4094000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4793200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4830000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4848400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5814400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5851200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5888000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5924800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5961600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5998400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6035200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6072000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6108800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6145600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6182400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6219200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6256000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6292800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6329600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6366400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6403200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6440000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6476800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6513600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6550400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6587200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6624000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6660800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6697600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6734400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6771200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6808000y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6844800y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6881600y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6918400y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6955200y5684800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6964400y5684800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2884200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x2893400y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3937600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3974400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3992800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4774800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4811600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4820800y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4834600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x4843800y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5694800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5731600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5768400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5786800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x5796000y5684800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5809800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5846600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5883400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5920200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5957000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5993800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6030600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6067400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6104200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6141000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6177800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6214600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6251400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5684800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5684800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5684800 ( @@ -106456,72 +108073,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5712000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5712000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5712000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5712000 ( @@ -106542,7 +108159,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106574,61 +108193,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106656,7 +108275,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106682,61 +108303,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106770,7 +108391,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5712000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5712000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -106816,19 +108439,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5712000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5712000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5712000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5712000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -106854,373 +108477,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5739200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5739200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5739200 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x2175800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5739200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2856600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5739200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3629400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5739200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4402200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5739200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5739200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5739200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5739200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5739200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107240,72 +108861,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5766400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5766400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5766400 ( @@ -107326,7 +108947,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107410,9 +109033,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107440,7 +109061,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107518,9 +109141,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5766400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107554,7 +109175,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5766400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5766400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -107600,19 +109223,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5766400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5766400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5766400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5766400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -107638,373 +109261,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5793600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5793600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5793600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1458200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5793600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2231000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5793600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2967000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5793600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5308400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5345200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5382000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5418800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5455600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5492400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5529200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5566000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5602800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5639600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5676400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5713200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5750000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5786800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5823600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5860400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5897200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5934000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5970800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6007600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6044400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6081200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6118000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6154800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6191600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6228400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6265200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6283600y5793600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5793600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5793600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5793600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5793600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5793600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108024,72 +109645,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5820800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5820800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5820800 ( @@ -108110,7 +109731,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108194,9 +109817,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108224,7 +109845,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108302,9 +109925,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5820800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108338,7 +109959,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5820800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5820800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108384,19 +110007,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5820800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5820800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5820800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5820800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -108422,373 +110045,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5848000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5848000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2341400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5848000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_2_x2378200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5848000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3132600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3850200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y5848000 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3905400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y5848000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5848000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5848000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5848000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5848000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5848000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108808,72 +110429,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5875200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5875200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5875200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5875200 ( @@ -108894,7 +110515,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5875200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -108978,9 +110601,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109008,7 +110629,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5875200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109086,9 +110709,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5875200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109122,7 +110743,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5875200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5875200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109168,19 +110791,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5875200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5875200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5875200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5875200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -109206,373 +110829,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5902400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5902400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y5902400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3739800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y5902400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3795000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y5902400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4512600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5902400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x4531000y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5902400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5248600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5902400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5902400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5902400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5902400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5902400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109592,72 +111213,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5929600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5929600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5929600 ( @@ -109678,7 +111299,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109762,9 +111385,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109792,7 +111413,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109870,9 +111493,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5929600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109906,7 +111527,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5929600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5929600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -109952,19 +111575,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5929600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5929600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5929600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5929600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -109990,373 +111613,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y5956800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y5956800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y5956800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2341400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y5956800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_2_x2378200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y5956800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5956800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y5956800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y5956800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y5956800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y5956800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5956800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110376,72 +111997,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y5984000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y5984000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y5984000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y5984000 ( @@ -110462,7 +112083,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110546,9 +112169,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110576,7 +112197,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110654,9 +112277,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y5984000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110690,7 +112311,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y5984000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y5984000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -110736,19 +112359,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y5984000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y5984000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y5984000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y5984000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -110774,373 +112397,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6011200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6011200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; 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xofiller_sky130_fd_sc_hd__fill_8_x740600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6011200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1458200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6011200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2231000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6011200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2967000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6011200 ( 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+sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6011200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6011200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6011200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6011200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6011200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111160,72 +112781,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6038400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6038400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6038400 ( @@ -111246,7 +112867,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111330,9 +112953,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111360,7 +112981,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111438,9 +113061,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6038400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111474,7 +113095,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6038400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6038400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111520,19 +113143,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6038400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6038400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6038400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6038400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -111558,373 +113181,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6065600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6065600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6065600 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_2_x2378200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6065600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6065600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3850200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6065600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6065600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6065600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6065600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6065600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6065600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -111944,72 +113565,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6092800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6092800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6092800 ( @@ -112030,7 +113651,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112114,9 +113737,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112144,7 +113765,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112222,9 +113845,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6092800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112258,7 +113879,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6092800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6092800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112304,19 +113927,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6092800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6092800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6092800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6092800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -112342,373 +113965,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6120000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6120000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6120000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1458200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6120000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2231000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6120000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2967000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x6021400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6120000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6120000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6120000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6120000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6120000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112728,72 +114349,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6147200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6147200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6147200 ( @@ -112814,7 +114435,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112898,9 +114521,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -112928,7 +114549,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113006,9 +114629,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6147200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113042,7 +114663,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6147200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6147200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113088,19 +114711,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6147200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6147200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6147200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6147200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -113126,373 +114749,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6174400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6174400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6174400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_2_x2378200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6174400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6174400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3132600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6174400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3850200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6174400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6174400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6174400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6174400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6174400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6174400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113512,72 +115133,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6201600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6201600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6201600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6201600 ( @@ -113598,7 +115219,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6201600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113682,9 +115305,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113712,7 +115333,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6201600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113790,9 +115413,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6201600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113826,7 +115447,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6201600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6201600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -113872,19 +115495,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6201600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6201600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6201600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6201600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -113910,373 +115533,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6228800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6228800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6228800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x1458200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6228800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x1513400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6228800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2231000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6228800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x2967000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6228800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3739800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6228800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3795000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6228800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4512600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6228800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x4531000y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6228800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5248600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6228800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x6021400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6228800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6228800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6228800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6228800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6228800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114296,72 +115917,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6256000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6256000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6256000 ( @@ -114382,7 +116003,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114466,9 +116089,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114496,7 +116117,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114574,9 +116197,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6256000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114610,7 +116231,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6256000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6256000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -114656,19 +116279,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6256000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6256000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6256000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6256000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -114694,373 +116317,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6283200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6283200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6283200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3463800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3500600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6283200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6283200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6283200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6283200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6283200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6283200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115080,72 +116701,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6310400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6310400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6310400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6310400 ( @@ -115166,7 +116787,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115250,9 +116873,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115280,7 +116901,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115358,9 +116981,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6310400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115394,7 +117015,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6310400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6310400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115440,19 +117063,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6310400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6310400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6310400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6310400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -115478,373 +117101,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6337600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6337600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6337600 ( +sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x4512600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4236600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4273400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6337600 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5248600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6337600 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x6076600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6337600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6337600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6337600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6337600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6337600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -115864,72 +117485,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6364800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6364800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6364800 ( @@ -115950,7 +117571,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116034,9 +117657,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116064,7 +117685,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116142,9 +117765,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6364800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116178,7 +117799,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6364800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6364800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116224,19 +117847,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6364800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6364800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6364800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6364800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -116262,373 +117885,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6392000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6392000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6392000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3077400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6392000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3850200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3537400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6392000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4623000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4310200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6392000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6392000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6392000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6392000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6392000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116648,74 +118269,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y6419200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6419200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1085600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1232800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1269600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1306400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1343200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1380000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6419200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6419200 ( @@ -116736,7 +118355,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116820,9 +118441,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116850,7 +118469,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116928,9 +118549,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6419200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -116964,7 +118583,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6419200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6419200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117010,19 +118631,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6419200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6419200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6419200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6419200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -117048,373 +118669,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6446400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6446400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6446400 ( .VGND ( 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+sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6446400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6446400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6446400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6446400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6446400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117434,72 +119053,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6473600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6473600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6473600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6473600 ( @@ -117520,7 +119139,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117604,9 +119225,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117634,7 +119253,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117712,9 +119333,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6473600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117748,7 +119367,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6473600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6473600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -117794,19 +119415,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6473600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6473600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6473600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6473600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -117832,373 +119453,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6500800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6500800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6500800 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3592600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6500800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x4365400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6500800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5101400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6500800 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5156600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6500800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6500800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6500800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6500800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6500800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118218,72 +119837,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6528000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6528000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6528000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6528000 ( @@ -118304,7 +119923,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118388,9 +120009,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118418,7 +120037,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118496,9 +120117,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6528000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118532,7 +120151,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6528000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6528000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -118578,19 +120199,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6528000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6528000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6528000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6528000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -118616,373 +120237,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6555200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6555200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6555200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x2378200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6555200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3114200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3408600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3445400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3482200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3519000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3555800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3592600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6555200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3887000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3574200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3923800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3611000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3960600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3647800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4181400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3868600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4218200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3905400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3942200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3979000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4015800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6555200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4659800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6555200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6555200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6555200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6555200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6555200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119002,72 +120621,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6582400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6582400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6582400 ( @@ -119088,7 +120707,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119172,9 +120793,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119202,7 +120821,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119280,9 +120901,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6582400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119316,7 +120935,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6582400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6582400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119362,19 +120983,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6582400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6582400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6582400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6582400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -119400,373 +121021,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6609600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6609600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6609600 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3592600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6609600 ( .VGND ( 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+sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6609600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6609600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6609600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6609600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6609600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119786,72 +121405,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6636800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6636800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6636800 ( @@ -119872,7 +121491,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119956,9 +121577,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -119986,7 +121605,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120064,9 +121685,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6636800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120100,7 +121719,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6636800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6636800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120146,19 +121767,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6636800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6636800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6636800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6636800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -120184,373 +121805,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6664000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6664000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6664000 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4659800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6664000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6664000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6664000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6664000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6664000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120570,72 +122189,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6691200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6691200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6691200 ( @@ -120656,7 +122275,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120740,9 +122361,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120770,7 +122389,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120848,9 +122469,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6691200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120884,7 +122503,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6691200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6691200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -120930,19 +122551,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6691200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6691200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6691200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6691200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -120968,373 +122589,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6718400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6718400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6718400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3592600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6718400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3647800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6718400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4365400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6718400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x4383800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6718400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5101400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6718400 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5156600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6718400 ( 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xofiller_sky130_fd_sc_hd__fill_8_x5874200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6718400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6718400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6718400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6718400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6718400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121354,72 +122973,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6745600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6745600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6745600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6745600 ( @@ -121440,7 +123059,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121524,9 +123145,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121554,7 +123173,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121632,9 +123253,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6745600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121668,7 +123287,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6745600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6745600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -121714,19 +123335,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6745600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6745600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6745600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6745600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -121752,373 +123373,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6772800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6772800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6772800 ( +sky130_fd_sc_hd__fill_8 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xofiller_sky130_fd_sc_hd__fill_8_x4659800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6772800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6772800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6772800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6772800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6772800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122138,72 +123757,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6800000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6800000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6800000 ( @@ -122224,7 +123843,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122308,9 +123929,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122338,7 +123957,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122416,9 +124037,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6800000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122452,7 +124071,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6800000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6800000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122498,19 +124119,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6800000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6800000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6800000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6800000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -122536,373 +124157,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6827200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6827200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2249400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2286200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2323000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2359800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6827200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x3592600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3629400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3666200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3353400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3703000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3390200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3739800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3427000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6827200 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x3647800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3997400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3684600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4034200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3721400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4071000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3758200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4107800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3795000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4144600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3831800y6827200 ( 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xofiller_sky130_fd_sc_hd__fill_8_x4365400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4052600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4089400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4126200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4163000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4199800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6827200 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5101400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6827200 ( .VGND ( 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xofiller_sky130_fd_sc_hd__fill_8_x5874200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6827200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6827200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6827200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6827200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6827200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -122922,72 +124541,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6854400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6854400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6854400 ( @@ -123008,7 +124627,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123092,9 +124713,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123122,7 +124741,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123200,9 +124821,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6854400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123236,7 +124855,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6854400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6854400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123282,19 +124903,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6854400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6854400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6854400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6854400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -123320,373 +124941,371 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y6881600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y6881600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1495000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1531800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1568600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1605400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1642200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1679000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1403000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1439800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1476600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1513400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1863000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1550200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1899800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1587000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1936600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1623800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1973400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1660600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2010200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1697400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2047000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1734200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2083800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1771000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2120600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1807800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2157400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1844600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2194200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1881400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2231000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1918200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2267800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1955000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1991800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2028600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2065400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2102200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2139000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2175800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2212600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6881600 ( .VGND ( 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VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5359000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5395800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5432600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5469400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5506200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5543000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5579800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5616600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5303800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5653400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5340600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5690200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5377400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5727000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5414200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5763800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5451000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5800600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5487800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5524600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5561400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5598200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5635000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5984600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5671800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6021400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5708600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6058200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5745400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6095000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5782200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6131800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5819000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6168600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5855800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5892600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5929400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5966200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6003000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6039800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6076600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6113400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6150200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6187000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6223800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6260600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6881600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6881600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6775800y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6812600y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6849400y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6886200y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6923000y6881600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6959800y6881600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6881600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123706,72 +125325,72 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1214400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1251200y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1288000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1324800y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1361600y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1398400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1407600y6908800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6908800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1458200y6908800 ( @@ -123792,7 +125411,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123876,9 +125497,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3335000y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123906,7 +125525,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -123984,9 +125605,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5285400y6908800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124020,7 +125639,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6908800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6908800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124066,19 +125687,19 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6757400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6908800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6941400y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6908800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6908800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6908800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -124096,73 +125717,73 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y6936000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y6936000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y6936000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1219000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1255800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1292600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1329400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1366200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1403000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1200600y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1237400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1274200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1311000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1347800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1384600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1421400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124184,7 +125805,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1715800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1752600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1789400y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1789400y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1807800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1826200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124216,61 +125839,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2304600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2341400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2378200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2378200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2396600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2415000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2433400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2451800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2470200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2488600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2507000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2525400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2543800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2562200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2580600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2599000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2617400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2635800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2654200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2672600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2691000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2709400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2727800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2746200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2764600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2783000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2801400y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x2819800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2838200y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x2838200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2875000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2856600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2911800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2893400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2948600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2930200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2985400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x2967000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3022200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3003800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3059000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3040600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3095800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3077400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3132600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3114200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3169400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3151000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3206200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3187800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3243000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3224600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3279800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3261400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3316600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3298200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3353400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3335000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3371800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124298,7 +125921,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3776600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3813400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3850200y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x3850200y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x3868600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x3887000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124324,61 +125949,61 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4255000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4291800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4328600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4328600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4347000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4365400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4383800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4402200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4420600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4439000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4457400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4475800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4494200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4512600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4531000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4549400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4567800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4586200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4604600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4623000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4641400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4659800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4678200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4696600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4715000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4733400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4751800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4770200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4788600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4807000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4825400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4843800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4862200y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x4880600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4899000y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x4899000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4935800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4917400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4972600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4954200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5009400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x4991000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5046200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5027800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5083000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5064600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5119800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5101400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5156600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5138200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5193400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5175000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5230200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5211800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5267000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5248600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5303800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5285400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5322200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124412,7 +126037,9 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5837400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5874200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5911000y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x5911000y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x5929400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x5947800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -124432,45 +126059,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6205400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6242200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6279000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6279000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6297400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6315800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6334200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6352600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6371000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6389400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6407800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6426200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6444600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6463000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6481400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6499800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6518200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6536600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6555000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6573400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6591800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6610200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6628600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6647000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6665400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6683800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6702200y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6720600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6739000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6757400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6785000y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6794200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6821800y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6831000y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6858600y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6867800y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6895400y6936000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6904600y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x6932200y6936000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6941400y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x6969000y6936000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6959800y6936000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x6978200y6936000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x6987400y6936000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef index 601e375..f8a4092 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:cfb3d851a1114eb1d0e5257e314de9662bd4591be78d3e3b910ebd6f961ff42a -size 1319821 +oid sha256:704815829c6833cb52fc685dd119fcf6b96477b477ad8f8280fb7a55bd85dd6f +size 1055555 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v index 9861918..4bb92e9 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/fpga_core/fpga_core_icv_in_design.pt.v @@ -4,14 +4,6 @@ // // // -module direct_interc_5 ( in , out ) ; -input [0:0] in ; -output [0:0] out ; - -assign out[0] = in[0] ; -endmodule - - module direct_interc_2 ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -36,7 +28,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( in[0] ) , .X ( out[0] ) ) ; endmodule -module direct_interc_4 ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -44,40 +36,55 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; output [0:0] mem_outb ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_7 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; + +wire aps_rename_1_ ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_7 ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -86,25 +93,27 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; -EMBEDDED_IO_7 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_7 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__7 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -113,33 +122,30 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; -logical_tile_io_mode_physical__iopad_7 logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; -direct_interc_4 direct_interc_0_ ( + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc_4 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -148,19 +154,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -169,19 +175,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -190,19 +196,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -211,19 +217,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -232,19 +238,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -253,19 +259,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -274,19 +280,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -295,16 +301,18 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -314,7 +322,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -325,8 +333,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -342,13 +350,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -358,7 +366,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -369,8 +377,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -386,13 +394,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -402,7 +410,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -413,8 +421,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -430,13 +438,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_10 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -446,7 +454,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -457,8 +465,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -474,13 +482,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_6_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -490,7 +498,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -501,8 +509,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -518,13 +526,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_5_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -534,7 +542,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -545,8 +553,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -562,13 +570,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -578,7 +586,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -589,8 +597,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -606,13 +614,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -622,7 +630,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -633,8 +641,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -650,16 +658,14 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -668,19 +674,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -689,19 +695,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -710,19 +716,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -731,19 +737,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -752,19 +758,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -773,19 +779,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -794,19 +800,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -815,19 +821,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -836,16 +842,18 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -857,7 +865,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -874,8 +882,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -891,13 +899,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -909,7 +917,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -926,8 +934,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -943,13 +951,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -961,7 +969,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -978,8 +986,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -995,13 +1003,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_18 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1013,7 +1021,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1030,8 +1038,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1047,13 +1055,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1065,7 +1073,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1082,8 +1090,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1099,13 +1107,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1117,7 +1125,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1134,8 +1142,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1151,13 +1159,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1169,7 +1177,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1186,8 +1194,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1203,13 +1211,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1221,7 +1229,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1238,8 +1246,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1255,13 +1263,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1273,7 +1281,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1290,8 +1298,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1316,7 +1324,8 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1347,6 +1356,7 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1399,281 +1409,354 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0_6 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) ) ; -mux_tree_tapbuf_size10_1_5 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) ) ; -mux_tree_tapbuf_size10_5_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) ) ; -mux_tree_tapbuf_size10_6_4 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) ) ; -mux_tree_tapbuf_size10_7_2 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) ) ; -mux_tree_tapbuf_size10_18 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) ) ; -mux_tree_tapbuf_size10_2_5 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) ) ; -mux_tree_tapbuf_size10_3_5 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) ) ; -mux_tree_tapbuf_size10_4_5 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) ) ; -mux_tree_tapbuf_size10_mem_0_6 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_4 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_2 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_18 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_5 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_5 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_5 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_6 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) ) ; -mux_tree_tapbuf_size8_4_3 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) ) ; -mux_tree_tapbuf_size8_5_3 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) ) ; -mux_tree_tapbuf_size8_6_3 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) ) ; -mux_tree_tapbuf_size8_10 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) ) ; -mux_tree_tapbuf_size8_1_5 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) ) ; -mux_tree_tapbuf_size8_2_3 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) ) ; -mux_tree_tapbuf_size8_3_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) ) ; -mux_tree_tapbuf_size8_mem_0_6 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_3 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_3 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_3 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_10 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_5 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_3 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io__7 logical_tile_io_mode_io__0 ( +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , - .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1688,13 +1771,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1709,13 +1792,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1730,13 +1813,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1751,13 +1834,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1772,13 +1855,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1793,13 +1876,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1814,13 +1897,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1835,12 +1918,276 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1880,7 +2227,7 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1924,272 +2271,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2204,15 +2287,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2227,13 +2310,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2248,13 +2331,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2269,13 +2352,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2290,13 +2373,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2311,13 +2394,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2332,13 +2415,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2353,12 +2436,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_3_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2410,7 +2493,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2462,7 +2545,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2514,7 +2597,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_17 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2566,7 +2649,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2618,7 +2701,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2670,7 +2753,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2722,7 +2805,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2780,7 +2863,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -2804,6 +2890,10 @@ output [0:0] left_grid_pin_29_ ; output [0:0] left_grid_pin_30_ ; output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2853,327 +2943,354 @@ wire [0:0] mux_tree_tapbuf_size8_mem_5_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; -mux_tree_tapbuf_size10_0_5 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5_3 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6_3 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10_17 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1_4 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_4 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3_4 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0_5 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_3 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_3 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_17 mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_4 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_4 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_5 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4_2 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5_2 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6_2 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_9 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1_4 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3_2 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0_5 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_2 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_2 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_2 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_9 mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_4 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_2 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 \prog_clk[0]_bip379 ( .A ( prog_clk[0] ) , + .X ( \prog_clk__FEEDTHRU_2[0]0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( \prog_clk__FEEDTHRU_2[0]0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; endmodule -module direct_interc_3 ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -3181,8 +3298,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3191,13 +3308,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_6 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -3211,17 +3330,17 @@ wire aps_rename_2_ ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_6 ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 , p_abuf1 ) ; @@ -3238,22 +3357,24 @@ output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_6 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_6 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__6 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -3264,7 +3385,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -3272,17 +3393,17 @@ logical_tile_io_mode_physical__iopad_6 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_3 direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc_3 direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3302,7 +3423,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_16 ( in , sram , sram_inv , out , p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3320,8 +3441,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -3351,6 +3470,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -3359,7 +3480,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; + right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -3374,250 +3495,246 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; -mux_tree_tapbuf_size10_16 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem_16 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -logical_tile_io_mode_io__6 logical_tile_io_mode_io__0 ( +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) ) ; endmodule -module direct_interc_2 ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -3625,8 +3742,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3635,15 +3752,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb0_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO_5 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -3654,14 +3771,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_5 ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -3677,21 +3794,23 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_5 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_5 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io__5 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -3702,7 +3821,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -3710,17 +3829,14 @@ logical_tile_io_mode_physical__iopad_5 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_2 direct_interc_0_ ( +cbx_1__2__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc_2 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3740,8 +3856,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3761,8 +3877,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3782,8 +3898,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3803,8 +3919,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3824,8 +3940,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3840,13 +3956,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3866,8 +3982,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -3887,7 +4003,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_3_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3931,7 +4047,227 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -3965,13 +4301,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_1_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4015,220 +4351,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4243,13 +4367,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4269,8 +4393,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4290,8 +4414,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4311,8 +4435,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4332,8 +4456,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4353,8 +4477,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4374,8 +4498,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4390,13 +4514,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -4411,12 +4535,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4468,7 +4592,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4520,7 +4644,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4572,7 +4696,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_15 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4624,7 +4748,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4676,7 +4800,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4728,7 +4852,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4780,7 +4904,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4796,10 +4920,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -4825,14 +4946,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_0_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -4931,7 +5051,7 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -4985,327 +5105,386 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0_4 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1_3 mux_top_ipin_0 ( + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5_2 mux_top_ipin_3 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6_2 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7_1 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_15 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2_3 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3_3 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4_3 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0_4 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_2 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_15 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_3 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_4 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4_1 mux_top_ipin_2 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5_1 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6_1 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1_3 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2_1 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3_1 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0_4 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5_1 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6_1 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_8 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_3 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2_1 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3_1 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io__5 logical_tile_io_mode_io__0 ( +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5320,13 +5499,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5341,13 +5520,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5362,13 +5541,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5383,13 +5562,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5404,13 +5583,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5425,13 +5604,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5446,13 +5625,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5467,12 +5646,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5516,7 +5695,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5560,139 +5739,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_7 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5726,13 +5773,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5776,7 +5823,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -5820,8 +5867,140 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5836,13 +6015,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5857,13 +6036,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5878,13 +6057,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5899,13 +6078,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5920,13 +6099,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5941,13 +6120,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5962,13 +6141,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -5983,12 +6162,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_3_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6040,7 +6219,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6092,7 +6271,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6144,7 +6323,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_14 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6196,7 +6375,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6248,7 +6427,55 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6300,7 +6527,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -6318,8 +6545,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6349,58 +6574,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -6411,8 +6586,8 @@ module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -6436,12 +6611,11 @@ output [0:0] bottom_grid_pin_13_ ; output [0:0] bottom_grid_pin_14_ ; output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -6493,318 +6667,388 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0_3 mux_top_ipin_0 ( +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4_2 mux_top_ipin_3 ( + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5_1 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6_1 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_14 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1_2 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2_2 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3_2 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0_3 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_2 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6_1 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_14 mem_top_ipin_8 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_2 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0_3 mux_top_ipin_1 ( +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_7 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1_2 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0_3 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_7 mem_top_ipin_9 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1_2 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; + .X ( ropt_net_153 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; + .X ( ropt_net_156 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) ) ; + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) ) ; + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) ) ; + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6813,17 +7057,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( \_gOb15_mem_outb[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -6831,21 +7073,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -6855,26 +7098,26 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -6885,25 +7128,22 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -6917,8 +7157,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -6926,21 +7166,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -6950,17 +7188,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -6968,9 +7205,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -6981,7 +7219,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -6989,18 +7227,15 @@ logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7014,8 +7249,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7023,22 +7258,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7048,17 +7280,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7066,9 +7297,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7079,7 +7311,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7087,18 +7319,15 @@ logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7112,8 +7341,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7121,22 +7350,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7146,17 +7372,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7164,9 +7389,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7177,7 +7403,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7185,18 +7411,15 @@ logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc_1 direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc_1 direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7210,8 +7433,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7222,13 +7445,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -7244,12 +7468,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7257,9 +7482,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7270,7 +7496,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7279,13 +7505,13 @@ logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -7293,8 +7519,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7308,8 +7534,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -7320,13 +7546,13 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -7342,12 +7568,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -7355,9 +7582,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -7368,7 +7596,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -7377,14 +7605,14 @@ logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7399,13 +7627,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7420,13 +7648,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7441,13 +7669,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7462,13 +7690,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7483,13 +7711,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -7504,12 +7732,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_13 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7561,7 +7789,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7613,7 +7841,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7665,7 +7893,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7717,59 +7945,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -7817,6 +7993,58 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -7832,7 +8060,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -7871,13 +8099,15 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -7897,375 +8127,401 @@ wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ; wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0_2 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1_1 mux_top_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2_1 mux_top_ipin_2 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3_1 mux_top_ipin_3 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4_1 mux_top_ipin_4 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_13 mux_top_ipin_5 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0_2 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2_1 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3_1 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4_1 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_13 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8281,7 +8537,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_10 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8298,8 +8554,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8315,7 +8571,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8339,7 +8595,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8363,7 +8619,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8387,7 +8643,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -8400,14 +8656,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8423,8 +8677,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8440,8 +8694,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8457,8 +8711,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8474,8 +8728,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8491,8 +8745,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8508,8 +8762,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8525,8 +8779,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8542,8 +8796,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8559,8 +8813,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8576,8 +8830,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8593,8 +8847,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8610,8 +8864,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8627,8 +8881,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8644,8 +8898,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8661,8 +8915,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8678,8 +8932,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8695,8 +8949,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8712,8 +8966,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8729,8 +8983,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8746,8 +9000,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8763,8 +9017,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8780,8 +9034,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -8797,7 +9051,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_23 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8817,7 +9071,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8837,7 +9091,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8857,7 +9111,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8877,7 +9131,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8897,7 +9151,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8917,7 +9171,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8937,7 +9191,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8957,7 +9211,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -8977,27 +9231,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9017,7 +9251,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9037,7 +9271,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9057,7 +9291,147 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9073,7 +9447,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9093,7 +9467,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -9109,163 +9523,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9284,8 +9542,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9303,8 +9561,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9322,8 +9580,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9341,7 +9599,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9373,7 +9631,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9405,7 +9663,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9437,7 +9695,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9450,8 +9708,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9466,10 +9722,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_11 ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -9488,8 +9748,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9507,8 +9767,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9526,8 +9786,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -9545,7 +9805,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9581,7 +9841,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9617,7 +9877,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9653,7 +9913,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -9665,10 +9925,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -9682,10 +9939,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -9837,433 +10093,451 @@ wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_5 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2_1 mux_left_track_1 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_11 mux_left_track_5 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0_5 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_11 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_4 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2_1 mux_left_track_3 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_8 mux_left_track_7 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0_4 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_9_3 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0_5 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1_5 mux_bottom_track_13 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2_5 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3_5 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4_5 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5_3 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6_3 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7_3 mux_bottom_track_27 ( + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8_3 mux_bottom_track_29 ( + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10_3 mux_left_track_11 ( + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11_3 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13_3 mux_left_track_17 ( + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14_3 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15_2 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16_2 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17_1 mux_left_track_27 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18_1 mux_left_track_29 ( + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_23 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_5 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_5 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_5 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_5 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_5 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_3 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_3 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_3 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_3 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_2 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17_1 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18_1 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_23 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_6 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3_10 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1_4 mux_left_track_25 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0_6 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_10 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10275,15 +10549,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10294,13 +10570,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10311,13 +10587,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10328,13 +10604,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10345,13 +10621,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10362,12 +10638,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10387,7 +10663,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10407,7 +10683,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10427,7 +10723,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10447,27 +10743,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10482,12 +10758,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10499,13 +10775,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10516,13 +10792,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10533,13 +10809,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10550,13 +10826,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -10567,36 +10843,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10620,7 +10872,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10644,7 +10896,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10668,7 +10920,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10692,7 +10944,88 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2_3 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10706,69 +11039,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10796,7 +11072,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10824,7 +11100,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10852,7 +11128,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -10864,8 +11140,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -10877,10 +11151,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10896,12 +11172,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -10949,7 +11225,45 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -10963,50 +11277,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11042,7 +11318,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11078,7 +11354,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11092,8 +11368,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -11111,10 +11385,107 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11128,13 +11499,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11147,107 +11518,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11287,7 +11643,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11322,12 +11678,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11367,7 +11723,43 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -11407,128 +11799,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_10 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11543,13 +11815,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11564,12 +11836,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11637,7 +11909,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11705,7 +11977,28 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -11721,13 +12014,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11742,33 +12035,56 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11812,7 +12128,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11856,52 +12172,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11916,13 +12188,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -11937,12 +12209,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -11990,13 +12262,11 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -12061,7 +12331,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -12097,6 +12367,8 @@ output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -12197,71 +12469,75 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram ; wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; -mux_tree_tapbuf_size10_12 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0_1 mux_bottom_track_1 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0_1 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_1_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_track_8 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0_2 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size14_1 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -12270,8 +12546,8 @@ mux_tree_tapbuf_size14_1 mux_top_track_4 ( chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -12280,429 +12556,516 @@ mux_tree_tapbuf_size14_0_1 mux_bottom_track_5 ( chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem_1 mem_top_track_4 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5_2 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0_4 mux_bottom_track_17 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1_4 mux_left_track_1 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4_2 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_4 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_2 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6_10 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0_4 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1_1 mux_bottom_track_33 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem_10 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_4 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9_2 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_9 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0_5 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1_4 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem_9 mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_5 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_4 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_5 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1_3 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2_3 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3_3 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_9 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0_5 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_3 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_9 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_4 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1_4 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2_4 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3_4 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0_4 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_4 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_4 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_4 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) ) ; + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -12721,8 +13084,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12740,8 +13103,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12759,8 +13122,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12778,7 +13141,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12806,7 +13169,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12834,7 +13197,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12862,7 +13225,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -12874,8 +13237,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12887,11 +13248,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12902,15 +13265,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12926,8 +13289,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12943,8 +13306,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12960,8 +13323,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12977,8 +13340,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -12994,8 +13357,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13011,8 +13374,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13028,8 +13391,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13045,8 +13408,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13062,8 +13425,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13079,8 +13442,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13096,7 +13459,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13113,8 +13476,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13130,8 +13493,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13147,8 +13510,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13164,8 +13527,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13181,8 +13544,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13198,8 +13561,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13215,8 +13578,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13232,7 +13595,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13242,57 +13605,17 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_8_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13308,7 +13631,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13323,12 +13646,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13348,7 +13671,159 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13368,7 +13843,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13388,7 +13863,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13408,7 +13883,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13428,7 +13903,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13448,7 +13923,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13468,7 +13943,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13488,7 +13963,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13508,128 +13983,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13645,7 +14000,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13662,7 +14017,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13686,7 +14041,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -13710,7 +14065,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13729,8 +14084,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13748,7 +14103,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13780,7 +14135,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13812,7 +14167,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_9 ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -13831,8 +14186,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -13850,7 +14205,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13886,7 +14241,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -13900,6 +14255,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -13917,8 +14274,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -14043,395 +14398,454 @@ wire [0:2] mux_tree_tapbuf_size6_1_sram_inv ; wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; -mux_tree_tapbuf_size6_0_3 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6_9 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0_3 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_9 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_3 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_7 mux_top_track_6 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0_3 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_7 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_8 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0_4 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem_8 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_4 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_12_2 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13_2 mux_top_track_12 ( + .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14_2 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15_1 mux_top_track_16 ( + .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16_1 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_20 mux_top_track_26 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11_2 mux_left_track_9 ( + .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0_3 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1_3 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2_3 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4_3 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5_2 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6_2 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7_2 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8_2 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9_2 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10_2 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_2 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_3 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_3 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_3 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_3 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_2 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_2 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_2 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_2 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size4_0_4 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1_3 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_8 mux_left_track_7 ( + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0_4 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_8 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_8 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14445,14 +14859,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14488,7 +14902,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14500,12 +14914,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14515,17 +14929,17 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_7 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14537,13 +14951,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14554,13 +14968,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14571,13 +14985,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14588,13 +15002,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14605,13 +15019,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14622,12 +15036,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14646,12 +15060,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14675,7 +15089,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14699,7 +15113,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14723,7 +15137,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14747,7 +15161,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -14771,7 +15185,45 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14785,50 +15237,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14856,7 +15270,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14884,7 +15298,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14912,7 +15326,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14926,12 +15340,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -14963,7 +15377,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -14977,13 +15505,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14996,166 +15524,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15195,7 +15569,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15235,7 +15609,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15275,7 +15649,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15288,7 +15662,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -15308,14 +15681,11 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_0_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15355,7 +15725,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15395,7 +15765,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -15435,7 +15805,68 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15451,33 +15882,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15521,7 +15931,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15565,8 +15975,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15581,13 +15991,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15602,12 +16012,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15675,7 +16085,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15743,7 +16153,49 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -15759,54 +16211,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15854,51 +16264,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -15946,8 +16312,56 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -15962,12 +16376,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -16034,7 +16448,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -16074,6 +16490,8 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -16161,7 +16579,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_11 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -16169,52 +16587,55 @@ mux_tree_tapbuf_size10_11 mux_right_track_0 ( chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem_11 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -16224,8 +16645,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -16234,439 +16655,531 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_2 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0_1 mux_left_track_9 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0_1 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_6_1 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_9 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0_3 mux_bottom_track_1 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1_3 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4_1 mux_left_track_17 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5_1 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_9 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_3 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_3 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size5_6 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem_6 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_7 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0_3 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1_2 mux_bottom_track_25 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem_7 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_3 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_3 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1_2 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2_2 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3_2 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4_1 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3_7 mux_bottom_track_23 ( + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0_3 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_2 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4_1 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_7 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_19 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_8 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem_8 mem_left_track_33 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16680,71 +17193,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16784,7 +17238,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16824,7 +17278,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16864,7 +17318,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -16877,10 +17331,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -16897,15 +17348,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16920,13 +17370,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16941,13 +17391,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16962,13 +17412,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16983,13 +17433,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17004,13 +17454,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17025,13 +17475,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17046,13 +17496,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17067,13 +17517,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17088,13 +17538,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17109,13 +17559,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17130,13 +17580,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17151,12 +17601,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17208,7 +17658,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17260,7 +17710,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17312,7 +17762,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17364,7 +17814,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17416,7 +17866,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17468,7 +17918,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17520,7 +17970,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17572,7 +18022,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17624,7 +18074,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17676,7 +18126,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17728,7 +18178,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -17780,8 +18230,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17798,13 +18248,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17821,13 +18271,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17844,13 +18294,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -17867,12 +18317,164 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -17948,79 +18550,7 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -18044,8 +18574,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -18093,87 +18621,13 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18188,13 +18642,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18209,13 +18663,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18230,13 +18684,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18251,13 +18705,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18272,13 +18726,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18293,13 +18747,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18314,13 +18768,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -18335,12 +18789,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18400,7 +18854,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18460,7 +18914,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18520,7 +18974,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18580,7 +19034,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18640,7 +19094,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18700,7 +19154,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18760,7 +19214,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -18836,7 +19290,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail ) ; + chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -18880,6 +19337,11 @@ output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -18965,7 +19427,7 @@ wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -18973,8 +19435,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -18982,8 +19444,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -18991,8 +19453,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -19000,8 +19462,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -19009,8 +19471,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -19018,8 +19480,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -19027,8 +19489,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -19036,48 +19498,54 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -19086,9 +19554,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -19098,8 +19567,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -19108,9 +19577,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -19119,358 +19589,534 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7_8 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2_1 mux_right_track_32 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_2 mux_bottom_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1_2 mux_left_track_33 ( + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem_8 mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_2 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; + .X ( ropt_net_168 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19484,33 +20130,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19542,7 +20167,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19574,7 +20199,26 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19588,31 +20232,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19624,7 +20249,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19638,13 +20266,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -19656,7 +20285,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19670,14 +20302,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19692,13 +20325,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19713,12 +20346,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19774,7 +20407,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -19793,8 +20426,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -19827,10 +20458,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19842,12 +20475,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -19867,7 +20500,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -19879,13 +20512,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19896,13 +20529,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19913,13 +20546,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19930,13 +20563,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19947,13 +20580,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19964,13 +20597,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -19981,12 +20614,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20010,7 +20643,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20034,7 +20667,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20058,7 +20691,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20082,7 +20715,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20106,7 +20739,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20130,7 +20763,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -20154,7 +20787,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0_2 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20168,31 +20820,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20220,7 +20853,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20248,7 +20881,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20262,13 +21009,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20281,13 +21028,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20300,126 +21047,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20459,7 +21092,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20499,7 +21132,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20539,7 +21172,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20579,7 +21212,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20619,7 +21252,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20659,7 +21292,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20699,7 +21332,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20739,7 +21372,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -20779,7 +21412,49 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -20795,54 +21470,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20886,7 +21519,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20930,7 +21563,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -20985,7 +21618,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -21019,6 +21656,16 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -21105,271 +21752,292 @@ wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7_2 mux_top_track_6 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1_1 mux_left_track_3 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0_1 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0_1 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; -mux_tree_tapbuf_size4_6 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_2 mux_top_track_10 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem_6 mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_2 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_0_2 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1_1 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2_1 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3_1 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_6 mux_top_track_24 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0_2 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2_1 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3_1 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_6 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_38 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -21377,204 +22045,261 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_7 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0_2 mux_left_track_25 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0_2 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0_2 mux_left_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem_5 mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21585,15 +22310,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21609,8 +22336,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21626,8 +22353,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21643,7 +22370,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21660,8 +22387,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21677,8 +22404,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21694,8 +22421,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21711,8 +22438,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21728,8 +22455,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21745,8 +22472,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21762,8 +22489,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21779,8 +22506,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21796,8 +22523,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21813,8 +22540,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21830,8 +22557,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21847,8 +22574,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21864,8 +22591,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21881,7 +22608,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_1_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21901,7 +22628,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21921,7 +22648,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21941,7 +22668,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21961,7 +22688,23 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -21981,7 +22724,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22001,7 +22764,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22021,7 +22784,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22041,7 +22804,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_13_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22061,7 +22824,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22081,7 +22844,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22101,7 +22864,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22121,7 +22884,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22141,7 +22904,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22161,7 +22924,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22181,29 +22944,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22223,28 +22964,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22260,7 +22981,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22277,7 +22998,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22301,7 +23022,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -22325,7 +23046,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22344,8 +23065,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22363,7 +23084,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22395,7 +23116,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22427,7 +23148,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_6 ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22446,8 +23167,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22465,7 +23186,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22501,7 +23222,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -22640,334 +23361,383 @@ wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0_1 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_6 mux_right_track_4 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0_1 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_6 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0_1 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_4 mux_right_track_6 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_4 mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_4 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0_1 mux_right_track_24 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0_1 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_4_2 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6_1 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7_1 mux_right_track_16 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8_1 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9_1 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10_1 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11_1 mux_right_track_26 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13_1 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14_1 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_17 mux_right_track_38 ( + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0_2 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1_2 mux_bottom_track_25 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4_2 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8_1 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9_1 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10_1 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0_2 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_2 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -22984,8 +23754,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23001,8 +23771,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23018,8 +23788,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23035,8 +23805,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23052,8 +23822,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23069,7 +23839,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23089,7 +23859,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23109,7 +23879,39 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23129,7 +23931,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23149,48 +23951,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23202,13 +23964,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23225,8 +23987,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23242,8 +24004,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23259,8 +24021,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23276,7 +24038,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23300,7 +24062,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23324,7 +24086,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23348,7 +24110,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23372,7 +24134,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -23396,7 +24158,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23415,8 +24177,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23434,8 +24196,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23453,7 +24215,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23493,7 +24255,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23533,7 +24295,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23573,8 +24335,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23592,8 +24354,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23611,8 +24373,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23630,8 +24392,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23649,8 +24411,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23668,7 +24430,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23687,8 +24449,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23706,7 +24468,35 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23734,7 +24524,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23762,35 +24552,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23818,7 +24580,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23846,7 +24608,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23874,7 +24636,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -23902,8 +24664,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23921,8 +24683,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23940,8 +24702,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23959,8 +24721,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23978,7 +24740,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23997,7 +24759,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24029,7 +24791,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24061,7 +24823,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24093,7 +24855,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24125,7 +24887,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24157,8 +24919,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24176,8 +24938,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24195,8 +24957,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24214,8 +24976,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24233,7 +24995,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -24252,8 +25014,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24271,8 +25033,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -24290,7 +25052,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24326,7 +25088,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24362,7 +25124,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24398,7 +25160,45 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24434,7 +25234,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24470,43 +25270,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -24548,7 +25312,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -24568,6 +25332,7 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -24668,471 +25433,547 @@ wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_3 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0_1 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2_1 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0_1 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2_1 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0_1 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2_1 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3_1 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4_1 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_36 ( + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0_1 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2_1 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3_1 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4_1 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__buf_2 \prog_clk[0]_bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25151,8 +25992,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25170,8 +26011,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25189,8 +26030,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25208,7 +26049,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25236,7 +26077,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25264,35 +26105,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -25320,8 +26133,32 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25334,13 +26171,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25356,8 +26193,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25373,8 +26210,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25390,8 +26227,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25407,8 +26244,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25424,8 +26261,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25441,8 +26278,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25458,8 +26295,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25475,8 +26312,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25492,8 +26329,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25509,8 +26346,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25526,8 +26363,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25543,7 +26380,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -25560,8 +26397,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25577,8 +26414,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25594,7 +26431,67 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25614,27 +26511,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25654,7 +26531,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25674,7 +26551,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25694,7 +26571,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25714,7 +26631,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25734,7 +26651,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25754,7 +26671,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25774,7 +26691,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25794,7 +26711,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25814,87 +26731,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -25994,309 +26831,350 @@ wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , .X ( chanx_right_out[18] ) ) ; endmodule -module mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_23 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26307,15 +27185,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_40__56 ( .A ( mem_out[1] ) , - .X ( net_aps_56 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_aps_56 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_40__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26326,13 +27202,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_39__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26343,64 +27219,69 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_23 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_23 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_22 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( out[0] ) , + .X ( BUF_net_91 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_120 ( .A ( BUF_net_91 ) , + .X ( p_abuf0 ) ) ; endmodule -module mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_21 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_89 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk , p_abuf0 , p_abuf1 , p_abuf2 ) ; input [0:0] Test_en ; @@ -26416,16 +27297,16 @@ output p_abuf2 ; sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , .Q ( p_abuf2 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( net_net_100 ) , - .X ( p_abuf0 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_101 ( .A ( p_abuf2 ) , - .X ( net_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( .A ( p_abuf2 ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( p_abuf2 ) , .X ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( p_abuf2 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_60 ( .A ( p_abuf2 ) , + .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_60 ) , + .X ( p_abuf1 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -26440,8 +27321,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26452,29 +27333,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26515,12 +27396,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb7_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_36__52 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__53 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -26556,7 +27437,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -26610,8 +27491,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -26643,14 +27524,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -26660,7 +27541,7 @@ frac_lut4_mux frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -26674,11 +27555,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -26699,14 +27581,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -26714,7 +27596,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -26723,40 +27605,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , - p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p1 , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p_abuf3 , p_abuf4 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -26774,8 +27656,7 @@ output p_abuf1 ; output p_abuf2 ; output p_abuf3 ; output p_abuf4 ; -input p1 ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -26792,103 +27673,103 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign p_abuf1 = p_abuf2 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( fabric_regout[0] ) , .p_abuf1 ( p_abuf0 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( fabric_regout[0] ) , .p_abuf2 ( p_abuf2 ) ) ; -mux_tree_size2_21 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_21 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p_abuf0 ( p_abuf3 ) , .p1 ( p1 ) ) ; -mux_tree_size2_22 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_22 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p_abuf0 ( p_abuf4 ) , .p1 ( p1 ) ) ; -mux_tree_size2_23 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf4 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_23 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_21 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_22 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_23 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , - p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , + p_abuf3 , p_abuf4 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -26904,10 +27785,11 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; -input p1 ; -input p2 ; +output p_abuf3 ; +output p_abuf4 ; +input p0 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , @@ -26915,45 +27797,42 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_d .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf3 ) , .p_abuf4 ( p_abuf4 ) , - .p1 ( p1 ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_2_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26964,13 +27843,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26981,13 +27860,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -26998,60 +27877,68 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_20 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_19 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_19 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_87 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module mux_tree_size2_18 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_18 ( in , sram , sram_inv , out , p_abuf0 , + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -27066,7 +27953,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -27081,8 +27968,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_30 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27093,29 +27980,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_32__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_30 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_30 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27156,12 +28043,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb6_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__47 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__48 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_6 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -27194,10 +28081,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -27251,8 +28138,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_6 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -27282,16 +28169,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -27301,7 +28188,7 @@ frac_lut4_mux_6 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -27315,11 +28202,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_6 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -27340,14 +28228,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_6 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p2 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -27355,7 +28243,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -27364,39 +28252,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_30 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -27409,7 +28298,10 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -27426,100 +28318,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_13 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_18 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_18 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_19 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_19 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_20 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_20 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p2 ( p2 ) ) ; -mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_18 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_19 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_20 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p2 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_6 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -27532,53 +28424,54 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p2 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p0 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p0 ( p0 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27589,13 +28482,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__46 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__47 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27606,13 +28499,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__45 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__46 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27623,60 +28516,66 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__44 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__45 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_17 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module mux_tree_size2_15 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -27691,7 +28590,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -27706,8 +28605,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_29 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27718,29 +28617,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__43 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__44 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -27781,12 +28680,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb5_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__42 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__43 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_5 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -27815,642 +28714,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_6_ ( - .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -endmodule - - -module frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; -input [0:3] in ; -input [0:15] sram ; -input [0:15] sram_inv ; -input [0:0] mode ; -input [0:0] mode_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; -wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; -wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; - -sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , - .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , - .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , - .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; -sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , - .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , - .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , - .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , - .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , - sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , - .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , - sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , - sky130_fd_sc_hd__inv_1_3_Y[0] } ) , - .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( - prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , - frac_lut4_lut4_out , ccff_tail ) ; -input [0:0] prog_clk ; -input [0:3] frac_lut4_in ; -input [0:0] ccff_head ; -output [0:1] frac_lut4_lut3_out ; -output [0:0] frac_lut4_lut4_out ; -output [0:0] ccff_tail ; - -wire [0:0] frac_lut4_0_mode ; -wire [0:15] frac_lut4_0_sram ; -wire [0:15] frac_lut4_0_sram_inv ; - -frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , - .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , - .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( - .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , - .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , - frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , - frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , - frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , - frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , - frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , - .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , - frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , - frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , - frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , - frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , - frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , - frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , - frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , - SYNOPSYS_UNCONNECTED_2 } ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; -input [0:0] prog_clk ; -input [0:3] frac_logic_in ; -input [0:0] ccff_head ; -output [0:1] frac_logic_out ; -output [0:0] ccff_tail ; -input p0 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( - .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , - .ccff_head ( ccff_head ) , - .frac_lut4_lut3_out ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , - frac_logic_out[1] } ) , - - .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_29 mux_frac_logic_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( frac_logic_in[3] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , - p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fabric_in ; -input [0:0] fabric_regin ; -input [0:0] fabric_sc_in ; -input [0:0] fabric_clk ; -input [0:0] ccff_head ; -output [0:1] fabric_out ; -output [0:0] fabric_regout ; -output [0:0] fabric_sc_out ; -output [0:0] ccff_tail ; -input p0 ; -input p2 ; - -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; -wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:1] mux_tree_size2_0_sram ; -wire [0:1] mux_tree_size2_0_sram_inv ; -wire [0:1] mux_tree_size2_1_sram ; -wire [0:1] mux_tree_size2_1_sram_inv ; -wire [0:0] mux_tree_size2_2_out ; -wire [0:1] mux_tree_size2_2_sram ; -wire [0:1] mux_tree_size2_2_sram_inv ; -wire [0:0] mux_tree_size2_mem_0_ccff_tail ; -wire [0:0] mux_tree_size2_mem_1_ccff_tail ; - -assign fabric_regout[0] = fabric_sc_out[0] ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , - .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( - .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , - .ff_DI ( fabric_sc_in ) , - .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( - .Test_en ( Test_en ) , .clk ( clk ) , - .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , - .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , - .ff_Q ( fabric_sc_out ) , - .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_15 mux_fabric_out_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] - } ) , - .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_16 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] - } ) , - .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p2 ( p2 ) ) ; -mux_tree_size2_17 mux_ff_0_D_0 ( - .in ( { - logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , - fabric_regin[0] } ) , - .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , - .mem_out ( mux_tree_size2_0_sram ) , - .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , - .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , - .mem_out ( mux_tree_size2_1_sram ) , - .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , - .mem_out ( mux_tree_size2_2_sram ) , - .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - - .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , - .out ( fabric_clk ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 , p2 ) ; -input [0:0] prog_clk ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:3] fle_in ; -input [0:0] fle_regin ; -input [0:0] fle_sc_in ; -input [0:0] fle_clk ; -input [0:0] ccff_head ; -output [0:1] fle_out ; -output [0:0] fle_regout ; -output [0:0] fle_sc_out ; -output [0:0] ccff_tail ; -input p0 ; -input p2 ; - -logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( - .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , - .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , - .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , - .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; -direct_interc direct_interc_0_ ( - .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , - .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( fle_clk ) ) ; -endmodule - - -module mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__41 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( - Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; -input [0:0] Test_en ; -input [0:0] clk ; -input [0:0] ff_D ; -input [0:0] ff_DI ; -output [0:0] ff_Q ; -input [0:0] ff_clk ; - -sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , - .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , - .Q ( ff_Q[0] ) ) ; -endmodule - - -module mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:1] mem_out ; -output [0:1] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__38 ( .A ( mem_out[1] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:16] mem_out ; -output [0:16] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[16] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; -input [0:15] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:1] lut3_out ; -output [0:0] lut4_out ; - -wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; -wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( - .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( - .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( - .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_5_ ( @@ -28504,8 +28775,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_5 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -28544,7 +28815,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_5 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -28554,7 +28825,7 @@ frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -28568,11 +28839,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_5 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_5 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -28593,14 +28865,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p3 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -28608,7 +28880,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -28617,39 +28889,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_28 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_29 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_29 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -28662,7 +28935,9 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -28679,100 +28954,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p3 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_11 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_12 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_15 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_13 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_16 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_14 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_17 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_15 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_16 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_17 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_5 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -28785,53 +29060,50 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +input p3 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28842,13 +29114,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__36 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__42 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28859,13 +29131,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28876,60 +29148,68 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__40 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_14 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_13 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module mux_tree_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p_abuf0 , + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -28944,7 +29224,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -28959,8 +29239,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_28 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28971,29 +29251,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__33 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__39 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_27 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29033,13 +29313,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[16] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb4_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__38 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_4 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29129,8 +29409,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_4 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -29160,16 +29440,16 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_4 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -29179,7 +29459,7 @@ frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -29193,11 +29473,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_4 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_4 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -29218,14 +29499,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29233,7 +29514,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -29242,39 +29523,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_27 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_28 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_28 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29287,7 +29569,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29304,100 +29590,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_9 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_9 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_12 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_10 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_13 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_11 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p_abuf1 ( p_abuf3 ) , .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_14 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p3 ( p3 ) ) ; +grid_clb_mux_tree_size2_mem_12 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_13 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_14 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_4 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p_abuf3 , p2 , + p3 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29410,53 +29697,55 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf2 ; +output p_abuf3 ; +input p2 ; +input p3 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p_abuf3 ( p_abuf3 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf3 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29467,13 +29756,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__37 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29484,13 +29773,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__30 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__36 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29501,60 +29790,68 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__29 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_8 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_11 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_7 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p_abuf0 , + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +output p_abuf0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; endmodule -module mux_tree_size2_6 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_9 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +output p_abuf0 ; +output p_abuf1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -29569,7 +29866,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -29584,8 +29881,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_27 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29596,29 +29893,667 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__28 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__34 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_26 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_27 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:16] mem_out ; +output [0:16] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_5_ ( .D ( mem_out[4] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[5] ) , .Q_N ( mem_outb[5] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_6_ ( .D ( mem_out[5] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[6] ) , .Q_N ( mem_outb[6] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_7_ ( .D ( mem_out[6] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[7] ) , .Q_N ( mem_outb[7] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_8_ ( .D ( mem_out[7] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[8] ) , .Q_N ( mem_outb[8] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_9_ ( .D ( mem_out[8] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[9] ) , .Q_N ( mem_outb[9] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_10_ ( .D ( mem_out[9] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[10] ) , .Q_N ( mem_outb[10] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_11_ ( .D ( mem_out[10] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[11] ) , .Q_N ( mem_outb[11] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_12_ ( .D ( mem_out[11] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[12] ) , .Q_N ( mem_outb[12] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_13_ ( .D ( mem_out[12] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[13] ) , .Q_N ( mem_outb[13] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_14_ ( .D ( mem_out[13] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[14] ) , .Q_N ( mem_outb[14] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb3_mem_outb[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__33 ( .A ( mem_out[16] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_mux_3 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +input [0:15] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_4_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_5_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( + .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( + .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_5_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_6_ ( + .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_5_ ( .A0 ( in[11] ) , .A1 ( in[10] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_6_ ( .A0 ( in[13] ) , .A1 ( in[12] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_7_ ( .A0 ( in[15] ) , .A1 ( in[14] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__buf_2_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__buf_2_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__buf_2_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_3 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; +input [0:3] in ; +input [0:15] sram ; +input [0:15] sram_inv ; +input [0:0] mode ; +input [0:0] mode_inv ; +output [0:1] lut3_out ; +output [0:0] lut4_out ; + +wire [0:0] sky130_fd_sc_hd__buf_2_0_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_1_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_2_X ; +wire [0:0] sky130_fd_sc_hd__buf_2_3_X ; +wire [0:0] sky130_fd_sc_hd__inv_1_0_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_1_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_2_Y ; +wire [0:0] sky130_fd_sc_hd__inv_1_3_Y ; +wire [0:0] sky130_fd_sc_hd__or2_1_0_X ; + +sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__or2_1_0_ ( .A ( mode[0] ) , + .B ( in[3] ) , .X ( sky130_fd_sc_hd__or2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_0_ ( .A ( in[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_0_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_1_ ( .A ( in[1] ) , + .Y ( sky130_fd_sc_hd__inv_1_1_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_2_ ( .A ( in[2] ) , + .Y ( sky130_fd_sc_hd__inv_1_2_Y[0] ) ) ; +sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , + .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , + .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , + .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( + .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , + .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; +grid_clb_frac_lut4_mux_3 frac_lut4_mux_0_ ( .in ( sram ) , + .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , + sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , + .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , + sky130_fd_sc_hd__inv_1_1_Y[0] , sky130_fd_sc_hd__inv_1_2_Y[0] , + sky130_fd_sc_hd__inv_1_3_Y[0] } ) , + .lut3_out ( lut3_out ) , .lut4_out ( lut4_out ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 ( + prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , + frac_lut4_lut4_out , ccff_tail ) ; +input [0:0] prog_clk ; +input [0:3] frac_lut4_in ; +input [0:0] ccff_head ; +output [0:1] frac_lut4_lut3_out ; +output [0:0] frac_lut4_lut4_out ; +output [0:0] ccff_tail ; + +wire [0:0] frac_lut4_0_mode ; +wire [0:15] frac_lut4_0_sram ; +wire [0:15] frac_lut4_0_sram_inv ; + +grid_clb_frac_lut4_3 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , + .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , + .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_3 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( ccff_tail ) , + .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , + frac_lut4_0_sram[2] , frac_lut4_0_sram[3] , frac_lut4_0_sram[4] , + frac_lut4_0_sram[5] , frac_lut4_0_sram[6] , frac_lut4_0_sram[7] , + frac_lut4_0_sram[8] , frac_lut4_0_sram[9] , frac_lut4_0_sram[10] , + frac_lut4_0_sram[11] , frac_lut4_0_sram[12] , frac_lut4_0_sram[13] , + frac_lut4_0_sram[14] , frac_lut4_0_sram[15] , frac_lut4_0_mode[0] } ) , + .mem_outb ( { frac_lut4_0_sram_inv[0] , frac_lut4_0_sram_inv[1] , + frac_lut4_0_sram_inv[2] , frac_lut4_0_sram_inv[3] , + frac_lut4_0_sram_inv[4] , frac_lut4_0_sram_inv[5] , + frac_lut4_0_sram_inv[6] , frac_lut4_0_sram_inv[7] , + frac_lut4_0_sram_inv[8] , frac_lut4_0_sram_inv[9] , + frac_lut4_0_sram_inv[10] , frac_lut4_0_sram_inv[11] , + frac_lut4_0_sram_inv[12] , frac_lut4_0_sram_inv[13] , + frac_lut4_0_sram_inv[14] , frac_lut4_0_sram_inv[15] , + SYNOPSYS_UNCONNECTED_2 } ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p2 ) ; +input [0:0] prog_clk ; +input [0:3] frac_logic_in ; +input [0:0] ccff_head ; +output [0:1] frac_logic_out ; +output [0:0] ccff_tail ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( + .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , + .ccff_head ( ccff_head ) , + .frac_lut4_lut3_out ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] , + frac_logic_out[1] } ) , + + .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; +grid_clb_mux_tree_size2_27 mux_frac_logic_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_27 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_in[0] ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( frac_logic_in[1] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( frac_logic_in[2] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( frac_logic_in[3] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fabric_in ; +input [0:0] fabric_regin ; +input [0:0] fabric_sc_in ; +input [0:0] fabric_clk ; +input [0:0] ccff_head ; +output [0:1] fabric_out ; +output [0:0] fabric_regout ; +output [0:0] fabric_sc_out ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; +wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; +wire [0:1] mux_tree_size2_0_sram ; +wire [0:1] mux_tree_size2_0_sram_inv ; +wire [0:1] mux_tree_size2_1_sram ; +wire [0:1] mux_tree_size2_1_sram_inv ; +wire [0:0] mux_tree_size2_2_out ; +wire [0:1] mux_tree_size2_2_sram ; +wire [0:1] mux_tree_size2_2_sram_inv ; +wire [0:0] mux_tree_size2_mem_0_ccff_tail ; +wire [0:0] mux_tree_size2_mem_1_ccff_tail ; + +assign fabric_regout[0] = fabric_sc_out[0] ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , + .ccff_head ( ccff_head ) , + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .p2 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , + .ff_DI ( fabric_sc_in ) , + .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_7 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( + .Test_en ( Test_en ) , .clk ( clk ) , + .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , + .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , + .ff_Q ( fabric_sc_out ) , + .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +grid_clb_mux_tree_size2_9 mux_fabric_out_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] + } ) , + .sram ( mux_tree_size2_0_sram ) , + .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_10 mux_fabric_out_1 ( + .in ( { fabric_sc_out[0] , + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] + } ) , + .sram ( mux_tree_size2_1_sram ) , + .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , + .p_abuf0 ( p_abuf2 ) , .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_11 mux_ff_0_D_0 ( + .in ( { + logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , + fabric_regin[0] } ) , + .sram ( mux_tree_size2_2_sram ) , + .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_9 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , + .mem_out ( mux_tree_size2_0_sram ) , + .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; +grid_clb_mux_tree_size2_mem_10 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , + .mem_out ( mux_tree_size2_1_sram ) , + .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; +grid_clb_mux_tree_size2_mem_11 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , + .mem_out ( mux_tree_size2_2_sram ) , + .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_sc_out ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fabric_in[0] ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fabric_in[1] ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fabric_in[2] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fabric_in[3] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fabric_sc_in ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fabric_clk ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , + + .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , + .out ( fabric_clk ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_3 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p2 ) ; +input [0:0] prog_clk ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:3] fle_in ; +input [0:0] fle_regin ; +input [0:0] fle_sc_in ; +input [0:0] fle_clk ; +input [0:0] ccff_head ; +output [0:1] fle_out ; +output [0:0] fle_regout ; +output [0:0] fle_sc_out ; +output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p2 ; + +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , + .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , + .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , + .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( + .in ( { SYNOPSYS_UNCONNECTED_1 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fle_regout ) ) ; +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( fle_sc_out ) ) ; +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fle_in[0] ) ) ; +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( fle_in[1] ) ) ; +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( fle_in[2] ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( fle_in[3] ) ) ; +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , + .out ( fle_regin ) ) ; +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( fle_sc_in ) ) ; +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , + .out ( fle_clk ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__32 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__31 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__30 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p2 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p2 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_7 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_6 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +output p_abuf1 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 ( + Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; +input [0:0] Test_en ; +input [0:0] clk ; +input [0:0] ff_D ; +input [0:0] ff_DI ; +output [0:0] ff_Q ; +input [0:0] ff_clk ; + +sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , + .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( clk[0] ) , + .Q ( ff_Q[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_mem_26 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:1] mem_out ; +output [0:1] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__29 ( .A ( mem_out[1] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29659,12 +30594,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb2_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__27 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__28 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_2 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -29691,7 +30626,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; @@ -29754,8 +30689,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_2 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -29791,10 +30726,10 @@ sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -29804,7 +30739,7 @@ frac_lut4_mux_2 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -29818,11 +30753,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_2 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -29843,14 +30779,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_2 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p1 ; +input p0 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -29858,7 +30794,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -29867,40 +30803,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_26 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_26 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_26 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p1 , - p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -29913,8 +30849,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -29931,100 +30870,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p0 ( p0 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_6 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_6 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_7 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_7 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p1 ( p1 ) ) ; -mux_tree_size2_8 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_8 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; -mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p2 ( p2 ) ) ; +grid_clb_mux_tree_size2_mem_6 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_7 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_8 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p1 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_2 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , + p2 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30037,54 +30977,55 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p1 ; -input p3 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p0 ; +input p2 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30095,13 +31036,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__27 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30112,13 +31053,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__25 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__26 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30129,44 +31070,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__24 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__25 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_5 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_size2_4 ( in , sram , sram_inv , out , p3 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p3 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -30182,7 +31091,43 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p1 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_68 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_mux_tree_size2_3 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +output p_abuf0 ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( out[0] ) , .X ( p_abuf0 ) ) ; +endmodule + + +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30197,7 +31142,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30212,8 +31157,8 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_25 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30224,12 +31169,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__23 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__24 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_25 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -30245,8 +31190,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30287,12 +31232,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb1_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__23 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_1 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30321,7 +31266,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_0_ ( .A ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .X ( lut3_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( lut3_out[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .X ( lut4_out[0] ) ) ; @@ -30382,8 +31327,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_1 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -30419,10 +31364,10 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -30432,7 +31377,7 @@ frac_lut4_mux_1 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -30446,11 +31391,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_1 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -30471,7 +31417,7 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_1 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 ( prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -30486,7 +31432,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -30495,7 +31441,7 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_25 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_25 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] @@ -30503,32 +31449,32 @@ mux_tree_size2_25 mux_frac_logic_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; -mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_25 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 , - p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30541,8 +31487,10 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -30559,100 +31507,100 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_3 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_3 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_4 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_4 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p3 ( p3 ) ) ; -mux_tree_size2_5 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_5 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p3 ( p3 ) ) ; -mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p0 ( p0 ) ) ; +grid_clb_mux_tree_size2_mem_3 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_4 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_5 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 , p3 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_1 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf2 , p0 , p1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -30665,54 +31613,51 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; +output p_abuf0 ; +output p_abuf2 ; input p0 ; -input p3 ; +input p1 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf2 ) , + .p0 ( p0 ) , .p1 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , +grid_clb_direct_interc direct_interc_3_ ( + .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , +grid_clb_direct_interc direct_interc_4_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , +grid_clb_direct_interc direct_interc_6_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , +grid_clb_direct_interc direct_interc_9_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , +grid_clb_direct_interc direct_interc_10_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_clk ) ) ; endmodule -module mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30723,13 +31668,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__22 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30740,13 +31685,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__20 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__21 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30757,63 +31702,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__19 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__20 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_2 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_1 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_64 ( .A ( p_abuf0 ) , .X ( out[0] ) ) ; endmodule -module mux_tree_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p_abuf0 , + p_abuf1 , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( net_net_61 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( net_net_61 ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( p_abuf1 ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_63 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30828,7 +31777,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( Test_en , clk , ff_D , ff_DI , ff_Q , ff_clk ) ; input [0:0] Test_en ; input [0:0] clk ; @@ -30843,7 +31792,7 @@ sky130_fd_sc_hd__sdfxtp_1 sky130_fd_sc_hd__sdfxtp_1_0_ ( .D ( ff_D[0] ) , endmodule -module direct_interc ( in , out ) ; +module grid_clb_direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -30851,8 +31800,8 @@ assign out[0] = in[0] ; endmodule -module mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , mem_out , - mem_outb ) ; +module grid_clb_mux_tree_size2_mem_24 ( prog_clk , ccff_head , ccff_tail , + mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30863,29 +31812,29 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__18 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__19 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p1 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -30926,12 +31875,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_15_ ( .D ( mem_out[14] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[15] ) , .Q_N ( mem_outb[15] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[16] ) , .Q_N ( \_gOb0_mem_outb[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__17 ( .A ( mem_out[16] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__18 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; endmodule -module frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; +module grid_clb_frac_lut4_mux_0 ( in , sram , sram_inv , lut3_out , lut4_out ) ; input [0:15] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -30967,7 +31916,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_4_ ( +sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_4_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_4_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_5_ ( @@ -31021,8 +31970,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , lut3_out , - lut4_out ) ; +module grid_clb_frac_lut4_0 ( in , sram , sram_inv , mode , mode_inv , + lut3_out , lut4_out ) ; input [0:3] in ; input [0:15] sram ; input [0:15] sram_inv ; @@ -31054,14 +32003,14 @@ sky130_fd_sc_hd__inv_1 sky130_fd_sc_hd__inv_1_3_ ( .Y ( sky130_fd_sc_hd__inv_1_3_Y[0] ) ) ; sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_0_ ( .A ( in[0] ) , .X ( sky130_fd_sc_hd__buf_2_0_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_1_ ( .A ( in[1] ) , .X ( sky130_fd_sc_hd__buf_2_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_2_ ( .A ( in[2] ) , .X ( sky130_fd_sc_hd__buf_2_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_2_3_ ( +sky130_fd_sc_hd__dlygate4sd3_1 sky130_fd_sc_hd__buf_2_3_ ( .A ( sky130_fd_sc_hd__or2_1_0_X[0] ) , .X ( sky130_fd_sc_hd__buf_2_3_X[0] ) ) ; -frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , +grid_clb_frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , .sram ( { sky130_fd_sc_hd__buf_2_0_X[0] , sky130_fd_sc_hd__buf_2_1_X[0] , sky130_fd_sc_hd__buf_2_2_X[0] , sky130_fd_sc_hd__buf_2_3_X[0] } ) , .sram_inv ( { sky130_fd_sc_hd__inv_1_0_Y[0] , @@ -31071,7 +32020,7 @@ frac_lut4_mux_0 frac_lut4_mux_0_ ( .in ( sram ) , endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( prog_clk , frac_lut4_in , ccff_head , frac_lut4_lut3_out , frac_lut4_lut4_out , ccff_tail ) ; input [0:0] prog_clk ; @@ -31085,11 +32034,12 @@ wire [0:0] frac_lut4_0_mode ; wire [0:15] frac_lut4_0_sram ; wire [0:15] frac_lut4_0_sram_inv ; -frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , .sram ( frac_lut4_0_sram ) , - .sram_inv ( frac_lut4_0_sram_inv ) , .mode ( frac_lut4_0_mode ) , +grid_clb_frac_lut4_0 frac_lut4_0_ ( .in ( frac_lut4_in ) , + .sram ( frac_lut4_0_sram ) , .sram_inv ( frac_lut4_0_sram_inv ) , + .mode ( frac_lut4_0_mode ) , .mode_inv ( { SYNOPSYS_UNCONNECTED_1 } ) , .lut3_out ( frac_lut4_lut3_out ) , .lut4_out ( frac_lut4_lut4_out ) ) ; -frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( +grid_clb_frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( { frac_lut4_0_sram[0] , frac_lut4_0_sram[1] , @@ -31110,14 +32060,14 @@ frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem_0 frac_lut4_sky130_fd_sc_hd__dfxbp_1_mem endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( - prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( + prog_clk , frac_logic_in , ccff_head , frac_logic_out , ccff_tail , p1 ) ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] ccff_tail ; -input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out ; @@ -31125,7 +32075,7 @@ wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_0_sram_inv ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0 ( .prog_clk ( prog_clk ) , .frac_lut4_in ( frac_logic_in ) , .ccff_head ( ccff_head ) , .frac_lut4_lut3_out ( { @@ -31134,39 +32084,40 @@ logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logi .frac_lut4_lut4_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) ) ; -mux_tree_size2_24 mux_frac_logic_out_0 ( +grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( frac_logic_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , + .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( frac_logic_out[1] ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_in[0] ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( frac_logic_in[1] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( frac_logic_in[2] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( frac_logic_in[3] ) ) ; endmodule -module logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( prog_clk , - Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , fabric_clk , - ccff_head , fabric_out , fabric_regout , fabric_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( + prog_clk , Test_en , clk , fabric_in , fabric_regin , fabric_sc_in , + fabric_clk , ccff_head , fabric_out , fabric_regout , fabric_sc_out , + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31179,7 +32130,11 @@ output [0:1] fabric_out ; output [0:0] fabric_regout ; output [0:0] fabric_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -31196,100 +32151,101 @@ wire [0:0] mux_tree_size2_mem_1_ccff_tail ; assign fabric_regout[0] = fabric_sc_out[0] ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .prog_clk ( prog_clk ) , .frac_logic_in ( fabric_in ) , .ccff_head ( ccff_head ) , .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( + .p1 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_Q ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en ( Test_en ) , .clk ( clk ) , .ff_D ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) , .ff_DI ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) , .ff_Q ( fabric_sc_out ) , .ff_clk ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; -mux_tree_size2_0 mux_fabric_out_0 ( +grid_clb_mux_tree_size2_0 mux_fabric_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( mux_tree_size2_0_sram_inv ) , .out ( fabric_out[0] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_1 mux_fabric_out_1 ( + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p4 ( p4 ) ) ; +grid_clb_mux_tree_size2_1 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( mux_tree_size2_1_sram_inv ) , .out ( fabric_out[1] ) , - .p0 ( p0 ) ) ; -mux_tree_size2_2 mux_ff_0_D_0 ( + .p_abuf0 ( p_abuf2 ) , .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_2 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_regin[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( mux_tree_size2_2_sram_inv ) , .out ( mux_tree_size2_2_out ) , - .p0 ( p0 ) ) ; -mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , + .p1 ( p1 ) ) ; +grid_clb_mux_tree_size2_mem_0 mem_fabric_out_0 ( .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_size2_0_sram ) , .mem_outb ( mux_tree_size2_0_sram_inv ) ) ; -mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_1 mem_fabric_out_1 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_size2_1_sram ) , .mem_outb ( mux_tree_size2_1_sram_inv ) ) ; -mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , +grid_clb_mux_tree_size2_mem_2 mem_ff_0_D_0 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_size2_mem_1_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_size2_2_sram ) , .mem_outb ( mux_tree_size2_2_sram_inv ) ) ; -direct_interc direct_interc_0_ ( +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_1_ ( +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_sc_out ) ) ; -direct_interc direct_interc_2_ ( +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_in[0] ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fabric_in[1] ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fabric_in[2] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fabric_in[3] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fabric_sc_in ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fabric_clk ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( fabric_clk ) ) ; endmodule -module logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , clk , - fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , - fle_regout , fle_sc_out , ccff_tail , p0 ) ; +module grid_clb_logical_tile_clb_mode_default__fle_0 ( prog_clk , Test_en , + clk , fle_in , fle_regin , fle_sc_in , fle_clk , ccff_head , fle_out , + fle_regout , fle_sc_out , ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 , + p4 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31302,59 +32258,64 @@ output [0:1] fle_out ; output [0:0] fle_regout ; output [0:0] fle_sc_out ; output [0:0] ccff_tail ; -input p0 ; +output p_abuf0 ; +output p_abuf1 ; +output p_abuf2 ; +input p1 ; +input p4 ; -logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( +grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fabric_in ( fle_in ) , .fabric_regin ( fle_regin ) , .fabric_sc_in ( fle_sc_in ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_regout ( fle_regout ) , .fabric_sc_out ( fle_sc_out ) , - .ccff_tail ( ccff_tail ) , .p0 ( p0 ) ) ; -direct_interc direct_interc_0_ ( + .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , + .p_abuf2 ( p_abuf2 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( fle_out[0] ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( fle_out[1] ) ) ; -direct_interc direct_interc_2_ ( + .out ( { p_abuf2 } ) ) ; +grid_clb_direct_interc direct_interc_2_ ( .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( fle_regout ) ) ; -direct_interc direct_interc_3_ ( +grid_clb_direct_interc direct_interc_3_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( fle_sc_out ) ) ; -direct_interc direct_interc_4_ ( +grid_clb_direct_interc direct_interc_4_ ( .in ( { SYNOPSYS_UNCONNECTED_5 } ) , .out ( fle_in[0] ) ) ; -direct_interc direct_interc_5_ ( +grid_clb_direct_interc direct_interc_5_ ( .in ( { SYNOPSYS_UNCONNECTED_6 } ) , .out ( fle_in[1] ) ) ; -direct_interc direct_interc_6_ ( +grid_clb_direct_interc direct_interc_6_ ( .in ( { SYNOPSYS_UNCONNECTED_7 } ) , .out ( fle_in[2] ) ) ; -direct_interc direct_interc_7_ ( +grid_clb_direct_interc direct_interc_7_ ( .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( fle_in[3] ) ) ; -direct_interc direct_interc_8_ ( +grid_clb_direct_interc direct_interc_8_ ( .in ( { SYNOPSYS_UNCONNECTED_9 } ) , .out ( fle_regin ) ) ; -direct_interc direct_interc_9_ ( +grid_clb_direct_interc direct_interc_9_ ( .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( fle_sc_in ) ) ; -direct_interc direct_interc_10_ ( +grid_clb_direct_interc direct_interc_10_ ( .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( fle_clk ) ) ; endmodule -module logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , clb_I0 , - clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , clb_I3i , - clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , clb_I7 , - clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , - clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf4 , - p_abuf5 , p_abuf6 , p_abuf7 , p_abuf8 , p_abuf9 , p_abuf10 , p_abuf11 , - p_abuf12 , p_abuf13 , p_abuf14 , p_abuf15 , p_abuf16 , p0 , p1 , p2 , p3 , - p4 ) ; +module grid_clb_logical_tile_clb_mode_clb_ ( prog_clk , Test_en , clk , + clb_I0 , clb_I0i , clb_I1 , clb_I1i , clb_I2 , clb_I2i , clb_I3 , + clb_I3i , clb_I4 , clb_I4i , clb_I5 , clb_I5i , clb_I6 , clb_I6i , + clb_I7 , clb_I7i , clb_regin , clb_sc_in , clb_clk , ccff_head , clb_O , + clb_regout , clb_sc_out , ccff_tail , p_abuf0 , p_abuf3 , p_abuf5 , + p_abuf6 , p_abuf8 , p_abuf10 , p_abuf12 , p_abuf14 , p_abuf16 , p_abuf18 , + p_abuf20 , p_abuf22 , p_abuf24 , p_abuf26 , p_abuf28 , p_abuf30 , + p_abuf31 , p0 , p1 , p2 , p3 , p4 , p5 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31384,24 +32345,27 @@ output [0:0] clb_sc_out ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf3 ; -output p_abuf4 ; output p_abuf5 ; output p_abuf6 ; -output p_abuf7 ; output p_abuf8 ; -output p_abuf9 ; output p_abuf10 ; -output p_abuf11 ; output p_abuf12 ; -output p_abuf13 ; output p_abuf14 ; -output p_abuf15 ; output p_abuf16 ; +output p_abuf18 ; +output p_abuf20 ; +output p_abuf22 ; +output p_abuf24 ; +output p_abuf26 ; +output p_abuf28 ; +output p_abuf30 ; +output p_abuf31 ; input p0 ; input p1 ; input p2 ; input p3 ; input p4 ; +input p5 ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_regout ; @@ -31413,11 +32377,9 @@ wire [0:0] logical_tile_clb_mode_default__fle_2_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_2_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_ccff_tail ; -wire [0:0] logical_tile_clb_mode_default__fle_3_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_3_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_ccff_tail ; -wire [1:1] logical_tile_clb_mode_default__fle_4_fle_out ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_4_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_5_ccff_tail ; @@ -31427,65 +32389,69 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_regout ; wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; -logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( +grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I0[2] , clb_I0[1] , clb_I0[0] , clb_I0i[0] } ) , .fle_regin ( clb_regin ) , .fle_sc_in ( clb_sc_in ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , - .fle_out ( { p_abuf16 , p_abuf3 } ) , + .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p0 ( p0 ) ) ; -logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( + .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p_abuf2 ( p_abuf5 ) , + .p1 ( p2 ) , .p4 ( p5 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I1[2] , clb_I1[1] , clb_I1[0] , clb_I1i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_0_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .fle_out ( { p_abuf4 , clb_O[2] } ) , + .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .p0 ( p0 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( + .p_abuf0 ( p_abuf6 ) , .p_abuf2 ( p_abuf8 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I2[2] , clb_I2[1] , clb_I2[0] , clb_I2i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_1_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , - .fle_out ( { p_abuf6 , p_abuf7 } ) , + .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p1 ( p2 ) , .p3 ( p4 ) ) ; -logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( + .p_abuf0 ( p_abuf10 ) , .p_abuf1 ( p_abuf11 ) , .p_abuf2 ( p_abuf12 ) , + .p0 ( p0 ) , .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I3[2] , clb_I3[1] , clb_I3[0] , clb_I3i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_2_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .fle_out ( { logical_tile_clb_mode_default__fle_3_fle_out[0] , clb_O[6] } ) , + .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( + .p_abuf0 ( p_abuf14 ) , .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , + .p2 ( p3 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I4[2] , clb_I4[1] , clb_I4[0] , clb_I4i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_3_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , - .fle_out ( { clb_O[9] , logical_tile_clb_mode_default__fle_4_fle_out[1] } ) , + .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_4_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p0 ( p1 ) ) ; -logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( + .p_abuf0 ( p_abuf18 ) , .p_abuf2 ( p_abuf20 ) , .p_abuf3 ( p_abuf21 ) , + .p2 ( p3 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I5[2] , clb_I5[1] , clb_I5[0] , clb_I5i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_4_fle_regout ) , @@ -31496,20 +32462,21 @@ logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .fle_regout ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p0 ( p1 ) , .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( + .p_abuf0 ( p_abuf22 ) , .p_abuf2 ( p_abuf24 ) , .p3 ( p4 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I6[2] , clb_I6[1] , clb_I6[0] , clb_I6i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_5_fle_regout ) , .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .fle_out ( { p_abuf14 , p_abuf15 } ) , + .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_regout ( logical_tile_clb_mode_default__fle_6_fle_regout ) , .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p2 ( p3 ) ) ; -logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( + .p_abuf0 ( p_abuf26 ) , .p_abuf2 ( p_abuf28 ) , .p_abuf3 ( p_abuf29 ) , + .p0 ( p1 ) ) ; +grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .fle_in ( { clb_I7[2] , clb_I7[1] , clb_I7[0] , clb_I7i[0] } ) , .fle_regin ( logical_tile_clb_mode_default__fle_6_fle_regout ) , @@ -31519,287 +32486,203 @@ logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_regout ( clb_regout ) , .fle_sc_out ( clb_sc_out ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p_abuf2 ( p_abuf2 ) , .p1 ( p2 ) , .p2 ( p3 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf2 ( p_abuf2 ) , .p_abuf3 ( p_abuf30 ) , .p_abuf4 ( p_abuf31 ) , + .p0 ( p1 ) ) ; +grid_clb_direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf3 } ) ) ; -direct_interc direct_interc_1_ ( + .out ( { p_abuf5 } ) ) ; +grid_clb_direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf16 } ) ) ; -direct_interc direct_interc_2_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , - .out ( clb_O[2] ) ) ; -direct_interc direct_interc_3_ ( - .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf4 } ) ) ; -direct_interc direct_interc_4_ ( - .in ( { SYNOPSYS_UNCONNECTED_5 } ) , - .out ( { p_abuf7 } ) ) ; -direct_interc direct_interc_5_ ( - .in ( { SYNOPSYS_UNCONNECTED_6 } ) , - .out ( { p_abuf6 } ) ) ; -direct_interc direct_interc_6_ ( - .in ( { SYNOPSYS_UNCONNECTED_7 } ) , - .out ( clb_O[6] ) ) ; -direct_interc direct_interc_7_ ( - .in ( { SYNOPSYS_UNCONNECTED_8 } ) , - .out ( logical_tile_clb_mode_default__fle_3_fle_out ) ) ; -direct_interc direct_interc_8_ ( - .in ( { SYNOPSYS_UNCONNECTED_9 } ) , - .out ( logical_tile_clb_mode_default__fle_4_fle_out ) ) ; -direct_interc direct_interc_9_ ( - .in ( { SYNOPSYS_UNCONNECTED_10 } ) , - .out ( clb_O[9] ) ) ; -direct_interc direct_interc_10_ ( - .in ( { SYNOPSYS_UNCONNECTED_11 } ) , - .out ( clb_O[10] ) ) ; -direct_interc direct_interc_11_ ( - .in ( { SYNOPSYS_UNCONNECTED_12 } ) , - .out ( clb_O[11] ) ) ; -direct_interc direct_interc_12_ ( - .in ( { SYNOPSYS_UNCONNECTED_13 } ) , +grid_clb_direct_interc direct_interc_5_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { p_abuf11 } ) ) ; +grid_clb_direct_interc direct_interc_7_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( { p_abuf15 } ) ) ; -direct_interc direct_interc_13_ ( - .in ( { SYNOPSYS_UNCONNECTED_14 } ) , - .out ( { p_abuf14 } ) ) ; -direct_interc direct_interc_14_ ( - .in ( { SYNOPSYS_UNCONNECTED_15 } ) , - .out ( clb_O[14] ) ) ; -direct_interc direct_interc_15_ ( - .in ( { SYNOPSYS_UNCONNECTED_16 } ) , - .out ( clb_O[15] ) ) ; -direct_interc direct_interc_16_ ( - .in ( { SYNOPSYS_UNCONNECTED_17 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_17_ ( - .in ( { SYNOPSYS_UNCONNECTED_18 } ) , +grid_clb_direct_interc direct_interc_8_ ( + .in ( { SYNOPSYS_UNCONNECTED_5 } ) , + .out ( { p_abuf21 } ) ) ; +grid_clb_direct_interc direct_interc_12_ ( + .in ( { SYNOPSYS_UNCONNECTED_6 } ) , + .out ( { p_abuf29 } ) ) ; +grid_clb_direct_interc direct_interc_15_ ( + .in ( { SYNOPSYS_UNCONNECTED_7 } ) , + .out ( { p_abuf30 } ) ) ; +grid_clb_direct_interc direct_interc_16_ ( + .in ( { SYNOPSYS_UNCONNECTED_8 } ) , .out ( { p_abuf2 } ) ) ; -direct_interc direct_interc_18_ ( - .in ( { SYNOPSYS_UNCONNECTED_19 } ) , +grid_clb_direct_interc direct_interc_17_ ( + .in ( { SYNOPSYS_UNCONNECTED_9 } ) , + .out ( { p_abuf1 } ) ) ; +grid_clb_direct_interc direct_interc_18_ ( + .in ( { SYNOPSYS_UNCONNECTED_10 } ) , .out ( clb_I0[2] ) ) ; -direct_interc direct_interc_19_ ( - .in ( { SYNOPSYS_UNCONNECTED_20 } ) , +grid_clb_direct_interc direct_interc_19_ ( + .in ( { SYNOPSYS_UNCONNECTED_11 } ) , .out ( clb_I0[1] ) ) ; -direct_interc direct_interc_20_ ( - .in ( { SYNOPSYS_UNCONNECTED_21 } ) , +grid_clb_direct_interc direct_interc_20_ ( + .in ( { SYNOPSYS_UNCONNECTED_12 } ) , .out ( clb_I0[0] ) ) ; -direct_interc direct_interc_21_ ( - .in ( { SYNOPSYS_UNCONNECTED_22 } ) , +grid_clb_direct_interc direct_interc_21_ ( + .in ( { SYNOPSYS_UNCONNECTED_13 } ) , .out ( clb_I0i ) ) ; -direct_interc direct_interc_22_ ( - .in ( { SYNOPSYS_UNCONNECTED_23 } ) , +grid_clb_direct_interc direct_interc_22_ ( + .in ( { SYNOPSYS_UNCONNECTED_14 } ) , .out ( clb_regin ) ) ; -direct_interc direct_interc_23_ ( - .in ( { SYNOPSYS_UNCONNECTED_24 } ) , +grid_clb_direct_interc direct_interc_23_ ( + .in ( { SYNOPSYS_UNCONNECTED_15 } ) , .out ( clb_sc_in ) ) ; -direct_interc direct_interc_24_ ( - .in ( { SYNOPSYS_UNCONNECTED_25 } ) , +grid_clb_direct_interc direct_interc_24_ ( + .in ( { SYNOPSYS_UNCONNECTED_16 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_25_ ( - .in ( { SYNOPSYS_UNCONNECTED_26 } ) , +grid_clb_direct_interc direct_interc_25_ ( + .in ( { SYNOPSYS_UNCONNECTED_17 } ) , .out ( clb_I1[2] ) ) ; -direct_interc direct_interc_26_ ( - .in ( { SYNOPSYS_UNCONNECTED_27 } ) , +grid_clb_direct_interc direct_interc_26_ ( + .in ( { SYNOPSYS_UNCONNECTED_18 } ) , .out ( clb_I1[1] ) ) ; -direct_interc direct_interc_27_ ( - .in ( { SYNOPSYS_UNCONNECTED_28 } ) , +grid_clb_direct_interc direct_interc_27_ ( + .in ( { SYNOPSYS_UNCONNECTED_19 } ) , .out ( clb_I1[0] ) ) ; -direct_interc direct_interc_28_ ( - .in ( { SYNOPSYS_UNCONNECTED_29 } ) , +grid_clb_direct_interc direct_interc_28_ ( + .in ( { SYNOPSYS_UNCONNECTED_20 } ) , .out ( clb_I1i ) ) ; -direct_interc direct_interc_29_ ( - .in ( { SYNOPSYS_UNCONNECTED_30 } ) , +grid_clb_direct_interc direct_interc_29_ ( + .in ( { SYNOPSYS_UNCONNECTED_21 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_regout ) ) ; -direct_interc direct_interc_30_ ( - .in ( { SYNOPSYS_UNCONNECTED_31 } ) , +grid_clb_direct_interc direct_interc_30_ ( + .in ( { SYNOPSYS_UNCONNECTED_22 } ) , .out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) ) ; -direct_interc direct_interc_31_ ( - .in ( { SYNOPSYS_UNCONNECTED_32 } ) , +grid_clb_direct_interc direct_interc_31_ ( + .in ( { SYNOPSYS_UNCONNECTED_23 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_32_ ( - .in ( { SYNOPSYS_UNCONNECTED_33 } ) , +grid_clb_direct_interc direct_interc_32_ ( + .in ( { SYNOPSYS_UNCONNECTED_24 } ) , .out ( clb_I2[2] ) ) ; -direct_interc direct_interc_33_ ( - .in ( { SYNOPSYS_UNCONNECTED_34 } ) , +grid_clb_direct_interc direct_interc_33_ ( + .in ( { SYNOPSYS_UNCONNECTED_25 } ) , .out ( clb_I2[1] ) ) ; -direct_interc direct_interc_34_ ( - .in ( { SYNOPSYS_UNCONNECTED_35 } ) , +grid_clb_direct_interc direct_interc_34_ ( + .in ( { SYNOPSYS_UNCONNECTED_26 } ) , .out ( clb_I2[0] ) ) ; -direct_interc direct_interc_35_ ( - .in ( { SYNOPSYS_UNCONNECTED_36 } ) , +grid_clb_direct_interc direct_interc_35_ ( + .in ( { SYNOPSYS_UNCONNECTED_27 } ) , .out ( clb_I2i ) ) ; -direct_interc direct_interc_36_ ( - .in ( { SYNOPSYS_UNCONNECTED_37 } ) , +grid_clb_direct_interc direct_interc_36_ ( + .in ( { SYNOPSYS_UNCONNECTED_28 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_regout ) ) ; -direct_interc direct_interc_37_ ( - .in ( { SYNOPSYS_UNCONNECTED_38 } ) , +grid_clb_direct_interc direct_interc_37_ ( + .in ( { SYNOPSYS_UNCONNECTED_29 } ) , .out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) ) ; -direct_interc direct_interc_38_ ( - .in ( { SYNOPSYS_UNCONNECTED_39 } ) , +grid_clb_direct_interc direct_interc_38_ ( + .in ( { SYNOPSYS_UNCONNECTED_30 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_39_ ( - .in ( { SYNOPSYS_UNCONNECTED_40 } ) , +grid_clb_direct_interc direct_interc_39_ ( + .in ( { SYNOPSYS_UNCONNECTED_31 } ) , .out ( clb_I3[2] ) ) ; -direct_interc direct_interc_40_ ( - .in ( { SYNOPSYS_UNCONNECTED_41 } ) , +grid_clb_direct_interc direct_interc_40_ ( + .in ( { SYNOPSYS_UNCONNECTED_32 } ) , .out ( clb_I3[1] ) ) ; -direct_interc direct_interc_41_ ( - .in ( { SYNOPSYS_UNCONNECTED_42 } ) , +grid_clb_direct_interc direct_interc_41_ ( + .in ( { SYNOPSYS_UNCONNECTED_33 } ) , .out ( clb_I3[0] ) ) ; -direct_interc direct_interc_42_ ( - .in ( { SYNOPSYS_UNCONNECTED_43 } ) , +grid_clb_direct_interc direct_interc_42_ ( + .in ( { SYNOPSYS_UNCONNECTED_34 } ) , .out ( clb_I3i ) ) ; -direct_interc direct_interc_43_ ( - .in ( { SYNOPSYS_UNCONNECTED_44 } ) , +grid_clb_direct_interc direct_interc_43_ ( + .in ( { SYNOPSYS_UNCONNECTED_35 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_regout ) ) ; -direct_interc direct_interc_44_ ( - .in ( { SYNOPSYS_UNCONNECTED_45 } ) , +grid_clb_direct_interc direct_interc_44_ ( + .in ( { SYNOPSYS_UNCONNECTED_36 } ) , .out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) ) ; -direct_interc direct_interc_45_ ( - .in ( { SYNOPSYS_UNCONNECTED_46 } ) , +grid_clb_direct_interc direct_interc_45_ ( + .in ( { SYNOPSYS_UNCONNECTED_37 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_46_ ( - .in ( { SYNOPSYS_UNCONNECTED_47 } ) , +grid_clb_direct_interc direct_interc_46_ ( + .in ( { SYNOPSYS_UNCONNECTED_38 } ) , .out ( clb_I4[2] ) ) ; -direct_interc direct_interc_47_ ( - .in ( { SYNOPSYS_UNCONNECTED_48 } ) , +grid_clb_direct_interc direct_interc_47_ ( + .in ( { SYNOPSYS_UNCONNECTED_39 } ) , .out ( clb_I4[1] ) ) ; -direct_interc direct_interc_48_ ( - .in ( { SYNOPSYS_UNCONNECTED_49 } ) , +grid_clb_direct_interc direct_interc_48_ ( + .in ( { SYNOPSYS_UNCONNECTED_40 } ) , .out ( clb_I4[0] ) ) ; -direct_interc direct_interc_49_ ( - .in ( { SYNOPSYS_UNCONNECTED_50 } ) , +grid_clb_direct_interc direct_interc_49_ ( + .in ( { SYNOPSYS_UNCONNECTED_41 } ) , .out ( clb_I4i ) ) ; -direct_interc direct_interc_50_ ( - .in ( { SYNOPSYS_UNCONNECTED_51 } ) , +grid_clb_direct_interc direct_interc_50_ ( + .in ( { SYNOPSYS_UNCONNECTED_42 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_regout ) ) ; -direct_interc direct_interc_51_ ( - .in ( { SYNOPSYS_UNCONNECTED_52 } ) , +grid_clb_direct_interc direct_interc_51_ ( + .in ( { SYNOPSYS_UNCONNECTED_43 } ) , .out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) ) ; -direct_interc direct_interc_52_ ( - .in ( { SYNOPSYS_UNCONNECTED_53 } ) , +grid_clb_direct_interc direct_interc_52_ ( + .in ( { SYNOPSYS_UNCONNECTED_44 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_53_ ( - .in ( { SYNOPSYS_UNCONNECTED_54 } ) , +grid_clb_direct_interc direct_interc_53_ ( + .in ( { SYNOPSYS_UNCONNECTED_45 } ) , .out ( clb_I5[2] ) ) ; -direct_interc direct_interc_54_ ( - .in ( { SYNOPSYS_UNCONNECTED_55 } ) , +grid_clb_direct_interc direct_interc_54_ ( + .in ( { SYNOPSYS_UNCONNECTED_46 } ) , .out ( clb_I5[1] ) ) ; -direct_interc direct_interc_55_ ( - .in ( { SYNOPSYS_UNCONNECTED_56 } ) , +grid_clb_direct_interc direct_interc_55_ ( + .in ( { SYNOPSYS_UNCONNECTED_47 } ) , .out ( clb_I5[0] ) ) ; -direct_interc direct_interc_56_ ( - .in ( { SYNOPSYS_UNCONNECTED_57 } ) , +grid_clb_direct_interc direct_interc_56_ ( + .in ( { SYNOPSYS_UNCONNECTED_48 } ) , .out ( clb_I5i ) ) ; -direct_interc direct_interc_57_ ( - .in ( { SYNOPSYS_UNCONNECTED_58 } ) , +grid_clb_direct_interc direct_interc_57_ ( + .in ( { SYNOPSYS_UNCONNECTED_49 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_regout ) ) ; -direct_interc direct_interc_58_ ( - .in ( { SYNOPSYS_UNCONNECTED_59 } ) , +grid_clb_direct_interc direct_interc_58_ ( + .in ( { SYNOPSYS_UNCONNECTED_50 } ) , .out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) ) ; -direct_interc direct_interc_59_ ( - .in ( { SYNOPSYS_UNCONNECTED_60 } ) , +grid_clb_direct_interc direct_interc_59_ ( + .in ( { SYNOPSYS_UNCONNECTED_51 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_60_ ( - .in ( { SYNOPSYS_UNCONNECTED_61 } ) , +grid_clb_direct_interc direct_interc_60_ ( + .in ( { SYNOPSYS_UNCONNECTED_52 } ) , .out ( clb_I6[2] ) ) ; -direct_interc direct_interc_61_ ( - .in ( { SYNOPSYS_UNCONNECTED_62 } ) , +grid_clb_direct_interc direct_interc_61_ ( + .in ( { SYNOPSYS_UNCONNECTED_53 } ) , .out ( clb_I6[1] ) ) ; -direct_interc direct_interc_62_ ( - .in ( { SYNOPSYS_UNCONNECTED_63 } ) , +grid_clb_direct_interc direct_interc_62_ ( + .in ( { SYNOPSYS_UNCONNECTED_54 } ) , .out ( clb_I6[0] ) ) ; -direct_interc direct_interc_63_ ( - .in ( { SYNOPSYS_UNCONNECTED_64 } ) , +grid_clb_direct_interc direct_interc_63_ ( + .in ( { SYNOPSYS_UNCONNECTED_55 } ) , .out ( clb_I6i ) ) ; -direct_interc direct_interc_64_ ( - .in ( { SYNOPSYS_UNCONNECTED_65 } ) , +grid_clb_direct_interc direct_interc_64_ ( + .in ( { SYNOPSYS_UNCONNECTED_56 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_regout ) ) ; -direct_interc direct_interc_65_ ( - .in ( { SYNOPSYS_UNCONNECTED_66 } ) , +grid_clb_direct_interc direct_interc_65_ ( + .in ( { SYNOPSYS_UNCONNECTED_57 } ) , .out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) ) ; -direct_interc direct_interc_66_ ( - .in ( { SYNOPSYS_UNCONNECTED_67 } ) , +grid_clb_direct_interc direct_interc_66_ ( + .in ( { SYNOPSYS_UNCONNECTED_58 } ) , .out ( clb_clk ) ) ; -direct_interc direct_interc_67_ ( - .in ( { SYNOPSYS_UNCONNECTED_68 } ) , +grid_clb_direct_interc direct_interc_67_ ( + .in ( { SYNOPSYS_UNCONNECTED_59 } ) , .out ( clb_I7[2] ) ) ; -direct_interc direct_interc_68_ ( - .in ( { SYNOPSYS_UNCONNECTED_69 } ) , +grid_clb_direct_interc direct_interc_68_ ( + .in ( { SYNOPSYS_UNCONNECTED_60 } ) , .out ( clb_I7[1] ) ) ; -direct_interc direct_interc_69_ ( - .in ( { SYNOPSYS_UNCONNECTED_70 } ) , +grid_clb_direct_interc direct_interc_69_ ( + .in ( { SYNOPSYS_UNCONNECTED_61 } ) , .out ( clb_I7[0] ) ) ; -direct_interc direct_interc_70_ ( - .in ( { SYNOPSYS_UNCONNECTED_71 } ) , +grid_clb_direct_interc direct_interc_70_ ( + .in ( { SYNOPSYS_UNCONNECTED_62 } ) , .out ( clb_I7i ) ) ; -direct_interc direct_interc_71_ ( - .in ( { SYNOPSYS_UNCONNECTED_72 } ) , +grid_clb_direct_interc direct_interc_71_ ( + .in ( { SYNOPSYS_UNCONNECTED_63 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_regout ) ) ; -direct_interc direct_interc_72_ ( - .in ( { SYNOPSYS_UNCONNECTED_73 } ) , +grid_clb_direct_interc direct_interc_72_ ( + .in ( { SYNOPSYS_UNCONNECTED_64 } ) , .out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) ) ; -direct_interc direct_interc_73_ ( - .in ( { SYNOPSYS_UNCONNECTED_74 } ) , +grid_clb_direct_interc direct_interc_73_ ( + .in ( { SYNOPSYS_UNCONNECTED_65 } ) , .out ( clb_clk ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( p_abuf3 ) , - .X ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( p_abuf4 ) , - .X ( BUF_net_63 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( p_abuf6 ) , - .X ( BUF_net_66 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( clb_O[2] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( p_abuf7 ) , - .X ( BUF_net_67 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , .X ( clb_O[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( - .A ( logical_tile_clb_mode_default__fle_3_fle_out[0] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_74 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , .X ( clb_O[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( clb_O[6] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_73 ( .A ( clb_O[9] ) , - .X ( p_abuf10 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_75 ( - .A ( logical_tile_clb_mode_default__fle_4_fle_out[1] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( p_abuf14 ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_77 ( .A ( clb_O[11] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( .A ( clb_O[10] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_81 ( .A ( p_abuf15 ) , - .X ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( BUF_net_62 ) , - .X ( clb_O[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_103 ( .A ( BUF_net_66 ) , - .X ( clb_O[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( BUF_net_75 ) , - .X ( p_abuf11 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_105 ( .A ( BUF_net_80 ) , - .X ( clb_O[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( BUF_net_77 ) , - .X ( p_abuf12 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_107 ( .A ( BUF_net_79 ) , - .X ( p_abuf13 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_108 ( .A ( BUF_net_81 ) , - .X ( clb_O[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_110 ( .A ( p_abuf16 ) , - .X ( clb_O[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( BUF_net_63 ) , - .X ( clb_O[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( BUF_net_65 ) , - .X ( p_abuf5 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( BUF_net_67 ) , - .X ( clb_O[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_115 ( .A ( BUF_net_69 ) , - .X ( p_abuf8 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( BUF_net_71 ) , - .X ( p_abuf9 ) ) ; endmodule @@ -31847,7 +32730,8 @@ module grid_clb ( prog_clk , Test_en , clk , top_width_0_height_0__pin_0_ , right_width_0_height_0__pin_49_upper , right_width_0_height_0__pin_49_lower , bottom_width_0_height_0__pin_50_ , bottom_width_0_height_0__pin_51_ , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + prog_clk__FEEDTHRU_3 , Test_en__FEEDTHRU_1 , clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:0] Test_en ; input [0:0] clk ; @@ -31926,24 +32810,26 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +output [0:0] prog_clk__FEEDTHRU_3 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_1 ; -wire p_abuf1 ; -wire p_abuf14 ; wire p_abuf2 ; -wire p_abuf5 ; -wire p_abuf4 ; -wire ropt_net_143 ; -wire ropt_net_148 ; +wire ropt_net_150 ; +wire ropt_net_141 ; +wire ropt_net_139 ; wire ropt_net_144 ; -wire p_abuf13 ; -wire p_abuf12 ; -wire ropt_net_131 ; -wire ropt_net_130 ; -wire ropt_net_133 ; +wire ropt_net_140 ; +wire p_abuf15 ; +wire ropt_net_147 ; assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_3[0] ; +assign prog_clk__FEEDTHRU_2[0] = prog_clk__FEEDTHRU_3[0] ; -logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( +grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .clk ( clk ) , .clb_I0 ( { top_width_0_height_0__pin_0_[0] , top_width_0_height_0__pin_1_[0] , top_width_0_height_0__pin_2_[0] } ) , @@ -31976,161 +32862,142 @@ logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .clb_regin ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , .clb_clk ( left_width_0_height_0__pin_52_ ) , .ccff_head ( ccff_head ) , - .clb_O ( { ropt_net_145 , ropt_net_137 , aps_rename_132_ , - top_width_0_height_0__pin_37_upper[0] , - top_width_0_height_0__pin_38_upper[0] , ropt_net_141 , - aps_rename_137_ , aps_rename_139_ , aps_rename_141_ , - aps_rename_143_ , aps_rename_145_ , aps_rename_147_ , - right_width_0_height_0__pin_46_upper[0] , ropt_net_146 , - ropt_net_131 , ropt_net_130 } ) , - .clb_regout ( { ropt_net_134 } ) , - .clb_sc_out ( { aps_rename_153_ } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( ropt_net_133 ) , - .p_abuf3 ( p_abuf1 ) , .p_abuf4 ( p_abuf2 ) , - .p_abuf5 ( top_width_0_height_0__pin_36_upper[0] ) , - .p_abuf6 ( p_abuf4 ) , .p_abuf7 ( p_abuf5 ) , - .p_abuf8 ( top_width_0_height_0__pin_41_upper[0] ) , - .p_abuf9 ( ropt_net_143 ) , .p_abuf10 ( ropt_net_148 ) , - .p_abuf11 ( right_width_0_height_0__pin_42_upper[0] ) , - .p_abuf12 ( right_width_0_height_0__pin_45_upper[0] ) , - .p_abuf13 ( ropt_net_144 ) , .p_abuf14 ( p_abuf12 ) , - .p_abuf15 ( p_abuf13 ) , .p_abuf16 ( p_abuf14 ) , .p0 ( optlc_net_125 ) , - .p1 ( optlc_net_126 ) , .p2 ( optlc_net_127 ) , .p3 ( optlc_net_128 ) , - .p4 ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( p_abuf1 ) , - .X ( aps_rename_130_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( p_abuf14 ) , - .X ( aps_rename_131_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( aps_rename_132_ ) , - .X ( aps_rename_133_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( p_abuf2 ) , - .X ( aps_rename_134_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( p_abuf5 ) , + .clb_O ( { ropt_net_145 , aps_rename_136_ , + top_width_0_height_0__pin_36_lower[0] , + top_width_0_height_0__pin_37_lower[0] , + top_width_0_height_0__pin_38_lower[0] , aps_rename_140_ , + top_width_0_height_0__pin_40_lower[0] , aps_rename_143_ , + aps_rename_144_ , aps_rename_145_ , + right_width_0_height_0__pin_44_lower[0] , + right_width_0_height_0__pin_45_lower[0] , aps_rename_148_ , + aps_rename_150_ , aps_rename_152_ , ropt_net_142 } ) , + .clb_regout ( { ropt_net_153 } ) , + .clb_sc_out ( { aps_rename_155_ } ) , + .ccff_tail ( { ropt_net_149 } ) , + .p_abuf0 ( ropt_net_147 ) , .p_abuf3 ( ropt_net_150 ) , + .p_abuf5 ( p_abuf2 ) , + .p_abuf6 ( top_width_0_height_0__pin_37_upper[0] ) , + .p_abuf8 ( top_width_0_height_0__pin_36_upper[0] ) , + .p_abuf10 ( ropt_net_141 ) , + .p_abuf12 ( top_width_0_height_0__pin_38_upper[0] ) , + .p_abuf14 ( ropt_net_139 ) , + .p_abuf16 ( top_width_0_height_0__pin_40_upper[0] ) , + .p_abuf18 ( ropt_net_144 ) , + .p_abuf20 ( right_width_0_height_0__pin_42_upper[0] ) , + .p_abuf22 ( right_width_0_height_0__pin_45_upper[0] ) , + .p_abuf24 ( right_width_0_height_0__pin_44_upper[0] ) , + .p_abuf26 ( ropt_net_140 ) , + .p_abuf28 ( right_width_0_height_0__pin_46_upper[0] ) , + .p_abuf30 ( p_abuf15 ) , + .p_abuf31 ( right_width_0_height_0__pin_48_upper[0] ) , + .p0 ( optlc_net_128 ) , .p1 ( optlc_net_129 ) , .p2 ( optlc_net_130 ) , + .p3 ( optlc_net_131 ) , .p4 ( optlc_net_132 ) , .p5 ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( Test_en[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( p_abuf2 ) , .X ( aps_rename_135_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( p_abuf4 ) , - .X ( aps_rename_136_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( aps_rename_137_ ) , - .X ( aps_rename_138_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__7 ( .A ( aps_rename_139_ ) , - .X ( aps_rename_140_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( aps_rename_141_ ) , - .X ( aps_rename_142_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( aps_rename_143_ ) , - .X ( aps_rename_144_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__10 ( .A ( aps_rename_145_ ) , - .X ( aps_rename_146_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__11 ( .A ( aps_rename_147_ ) , - .X ( aps_rename_148_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( p_abuf13 ) , - .X ( aps_rename_149_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( p_abuf12 ) , - .X ( aps_rename_150_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__14 ( .A ( ropt_net_131 ) , - .X ( aps_rename_151_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( ropt_net_130 ) , - .X ( aps_rename_152_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( aps_rename_153_ ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( aps_rename_130_ ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_85 ( .A ( aps_rename_131_ ) , - .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_86 ( .A ( aps_rename_133_ ) , - .X ( top_width_0_height_0__pin_36_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_134_ ) , - .X ( top_width_0_height_0__pin_37_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( aps_rename_135_ ) , - .X ( BUF_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( aps_rename_136_ ) , - .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_90 ( .A ( aps_rename_138_ ) , - .X ( BUF_net_90 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_91 ( .A ( aps_rename_140_ ) , - .X ( ropt_net_136 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_142_ ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_93 ( .A ( aps_rename_144_ ) , - .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_94 ( .A ( aps_rename_146_ ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_95 ( .A ( aps_rename_148_ ) , - .X ( right_width_0_height_0__pin_45_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_96 ( .A ( aps_rename_149_ ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( aps_rename_150_ ) , - .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_98 ( .A ( aps_rename_151_ ) , - .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_99 ( .A ( aps_rename_152_ ) , - .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( BUF_net_119 ) , - .X ( top_width_0_height_0__pin_38_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( BUF_net_88 ) , - .X ( BUF_net_119 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_120 ( .A ( BUF_net_89 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( BUF_net_122 ) , - .X ( top_width_0_height_0__pin_40_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_122 ( .A ( BUF_net_90 ) , - .X ( BUF_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_130 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_884 ( .A ( ropt_net_130 ) , - .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_885 ( .A ( ropt_net_131 ) , - .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_886 ( .A ( ropt_net_132 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_133 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_134 ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_889 ( .A ( ropt_net_135 ) , - .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_890 ( .A ( ropt_net_136 ) , - .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_893 ( .A ( ropt_net_137 ) , - .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_896 ( .A ( ropt_net_138 ) , - .X ( right_width_0_height_0__pin_44_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_897 ( .A ( ropt_net_139 ) , - .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_898 ( .A ( ropt_net_140 ) , - .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_899 ( .A ( ropt_net_141 ) , - .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_900 ( .A ( ropt_net_142 ) , - .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_901 ( .A ( ropt_net_143 ) , - .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_903 ( .A ( ropt_net_144 ) , - .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_906 ( .A ( ropt_net_145 ) , - .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_908 ( .A ( ropt_net_146 ) , - .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_910 ( .A ( ropt_net_147 ) , - .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_mt_inst_914 ( .A ( ropt_net_148 ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_915 ( .A ( ropt_net_150 ) , - .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_916 ( .A ( ropt_net_151 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_919 ( .A ( ropt_net_152 ) , - .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_mt_inst_920 ( .A ( ropt_net_153 ) , - .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_154 ) , +sky130_fd_sc_hd__conb_1 optlc_133 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_135 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_993 ( .A ( ropt_net_157 ) , + .X ( top_width_0_height_0__pin_35_lower[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_137 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_10__9 ( .A ( aps_rename_144_ ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \clk[0]_bip531 ( .A ( clk[0] ) , + .X ( ctsbuf_net_1134 ) ) ; +sky130_fd_sc_hd__clkbuf_1 \prog_clk[0]_bip532 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_5138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_963 ( .A ( ropt_net_139 ) , + .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_995 ( .A ( ropt_net_158 ) , .X ( bottom_width_0_height_0__pin_50_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_964 ( .A ( ropt_net_140 ) , + .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_999 ( .A ( ropt_net_159 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( p_abuf15 ) , + .X ( aps_rename_154_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( aps_rename_155_ ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_92 ( .A ( aps_rename_135_ ) , + .X ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1001 ( .A ( ropt_net_160 ) , + .X ( right_width_0_height_0__pin_42_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1002 ( .A ( ropt_net_161 ) , + .X ( SC_OUT_TOP ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_965 ( .A ( ropt_net_141 ) , + .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_966 ( .A ( ropt_net_142 ) , + .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_97 ( .A ( aps_rename_140_ ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_967 ( .A ( ropt_net_143 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_1004 ( .A ( ropt_net_162 ) , + .X ( top_width_0_height_0__pin_41_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( aps_rename_145_ ) , + .X ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_364896 ( .A ( ctsbuf_net_1134 ) , + .X ( clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_102 ( .A ( aps_rename_150_ ) , + .X ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1005 ( .A ( ropt_net_163 ) , + .X ( right_width_0_height_0__pin_46_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( aps_rename_154_ ) , + .X ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_968 ( .A ( ropt_net_144 ) , + .X ( right_width_0_height_0__pin_43_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_969 ( .A ( ropt_net_145 ) , + .X ( top_width_0_height_0__pin_34_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_971 ( .A ( BUF_net_104 ) , + .X ( right_width_0_height_0__pin_49_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_973 ( .A ( ropt_net_147 ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__buf_12 cts_buf_386918 ( .A ( ctsbuf_net_5138 ) , + .X ( prog_clk__FEEDTHRU_3[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_975 ( .A ( ropt_net_148 ) , + .X ( top_width_0_height_0__pin_39_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_976 ( .A ( ropt_net_149 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_114 ( .A ( BUF_net_100 ) , + .X ( right_width_0_height_0__pin_43_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_115 ( .A ( aps_rename_148_ ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_116 ( .A ( BUF_net_102 ) , + .X ( right_width_0_height_0__pin_47_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_117 ( .A ( aps_rename_152_ ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_978 ( .A ( ropt_net_150 ) , + .X ( top_width_0_height_0__pin_35_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_119 ( .A ( BUF_net_92 ) , + .X ( top_width_0_height_0__pin_34_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_121 ( .A ( aps_rename_136_ ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1006 ( .A ( ropt_net_164 ) , + .X ( right_width_0_height_0__pin_48_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_981 ( .A ( ropt_net_151 ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_982 ( .A ( ropt_net_152 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_125 ( .A ( aps_rename_143_ ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_1007 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_984 ( .A ( ropt_net_153 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_989 ( .A ( ropt_net_154 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_991 ( .A ( ropt_net_155 ) , + .X ( ropt_net_162 ) ) ; endmodule @@ -32325,7 +33192,6 @@ wire [0:0] cby_2__1__1_right_grid_pin_0_ ; wire [0:0] direct_interc_0_out ; wire [0:0] direct_interc_1_out ; wire [0:0] direct_interc_2_out ; -wire [0:0] direct_interc_5_out ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_0_ccff_tail ; @@ -32364,7 +33230,6 @@ wire [0:0] grid_clb_0_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_1__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ; -wire [0:0] grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ; wire [0:0] grid_clb_1_bottom_width_0_height_0__pin_50_ ; wire [0:0] grid_clb_1_ccff_tail ; wire [0:0] grid_clb_1_right_width_0_height_0__pin_42_lower ; @@ -32400,7 +33265,6 @@ wire [0:0] grid_clb_1_top_width_0_height_0__pin_40_upper ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_lower ; wire [0:0] grid_clb_1_top_width_0_height_0__pin_41_upper ; wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ; -wire [0:0] grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ; wire [0:0] grid_clb_2__1__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2__2__undriven_left_width_0_height_0__pin_52_ ; wire [0:0] grid_clb_2_ccff_tail ; @@ -32546,11 +33410,45 @@ wire [0:19] sb_2__1__0_chany_top_out ; wire [0:0] sb_2__2__0_ccff_tail ; wire [0:19] sb_2__2__0_chanx_left_out ; wire [0:19] sb_2__2__0_chany_bottom_out ; +wire [0:0] prog_clk__FEEDTHRU_1 ; +wire [0:0] prog_clk__FEEDTHRU_2 ; +wire [0:0] prog_clk__FEEDTHRU_3 ; +wire [0:0] prog_clk__FEEDTHRU_4 ; +wire [0:0] prog_clk__FEEDTHRU_5 ; +wire [0:0] prog_clk__FEEDTHRU_6 ; +wire [0:0] prog_clk__FEEDTHRU_7 ; +wire [0:0] prog_clk__FEEDTHRU_8 ; +wire [0:0] prog_clk__FEEDTHRU_9 ; +wire [0:0] prog_clk__FEEDTHRU_10 ; +wire [0:0] prog_clk__FEEDTHRU_11 ; +wire [0:0] prog_clk__FEEDTHRU_12 ; +wire [0:0] prog_clk__FEEDTHRU_13 ; +wire [0:0] prog_clk__FEEDTHRU_14 ; +wire [0:0] prog_clk__FEEDTHRU_15 ; +wire [0:0] prog_clk__FEEDTHRU_16 ; +wire [0:0] prog_clk__FEEDTHRU_17 ; +wire [0:0] prog_clk__FEEDTHRU_18 ; +wire [0:0] prog_clk__FEEDTHRU_19 ; +wire [0:0] prog_clk__FEEDTHRU_20 ; +wire [0:0] Test_en__FEEDTHRU_1 ; +wire [0:0] Test_en__FEEDTHRU_2 ; +wire [0:0] Test_en__FEEDTHRU_3 ; +wire [0:0] Test_en__FEEDTHRU_4 ; +wire [0:0] Test_en__FEEDTHRU_5 ; +wire [0:0] Test_en__FEEDTHRU_6 ; +wire [0:0] clk__FEEDTHRU_1 ; +wire [0:0] clk__FEEDTHRU_2 ; +wire [0:0] clk__FEEDTHRU_3 ; +wire [0:0] clk__FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ; +wire [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ; // -grid_clb grid_clb_1__1_ ( - .prog_clk ( { ctsbuf_net_1113 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , +grid_clb grid_clb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , + .Test_en ( Test_en__FEEDTHRU_4 ) , .clk ( clk__FEEDTHRU_1 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__0_bottom_grid_pin_2_ ) , @@ -32568,7 +33466,7 @@ grid_clb grid_clb_1__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_0_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_0_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_1 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__0_left_grid_pin_18_ ) , @@ -32619,14 +33517,18 @@ grid_clb grid_clb_1__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_0_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_0_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_0_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( grid_clb_0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_3_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_1 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_2 ) , .SC_OUT_BOT ( scff_Wires_5_ ) ) ; -grid_clb grid_clb_1__2_ ( - .prog_clk ( { ctsbuf_net_1517 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_5_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_4 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_5 ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_5 } ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_5 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_2 ) ) ; +grid_clb grid_clb_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , + .Test_en ( Test_en__FEEDTHRU_6 ) , .clk ( clk__FEEDTHRU_2 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__0_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__0_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__0_bottom_grid_pin_2_ ) , @@ -32643,8 +33545,8 @@ grid_clb grid_clb_1__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__0_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__0_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__0_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , - .top_width_0_height_0__pin_33_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_33_ ) , + .top_width_0_height_0__pin_32_ ( grid_clb_1__2__undriven_top_width_0_height_0__pin_32_ ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_6 } ) , .right_width_0_height_0__pin_16_ ( cby_1__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_1__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_1__1__1_left_grid_pin_18_ ) , @@ -32696,13 +33598,18 @@ grid_clb grid_clb_1__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_1_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_1_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_0_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_7 } ) , .ccff_tail ( grid_clb_1_ccff_tail ) , .SC_IN_TOP ( scff_Wires_1_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_3 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_4 ) , .SC_OUT_BOT ( scff_Wires_2_ ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_8 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_9 ) , .SC_OUT_BOT ( scff_Wires_2_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_7 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_10 } ) , + .prog_clk__FEEDTHRU_3 ( { SYNOPSYS_UNCONNECTED_11 } ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_12 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_13 } ) ) ; grid_clb grid_clb_2__1_ ( - .prog_clk ( { ctsbuf_net_57 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_2729 } ) , + .Test_en ( Test_en__FEEDTHRU_1 ) , .clk ( clk__FEEDTHRU_3 ) , .top_width_0_height_0__pin_0_ ( cbx_1__1__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__1__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__1__1_bottom_grid_pin_2_ ) , @@ -32720,7 +33627,7 @@ grid_clb grid_clb_2__1_ ( .top_width_0_height_0__pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , .top_width_0_height_0__pin_32_ ( direct_interc_1_out ) , - .top_width_0_height_0__pin_33_ ( { sc_in_wires_1_ } ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_14 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__0_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__0_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__0_left_grid_pin_18_ ) , @@ -32771,14 +33678,19 @@ grid_clb grid_clb_2__1_ ( .right_width_0_height_0__pin_48_lower ( grid_clb_2_right_width_0_height_0__pin_48_lower ) , .right_width_0_height_0__pin_49_upper ( grid_clb_2_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_2_right_width_0_height_0__pin_49_lower ) , - .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_51_ ) , + .bottom_width_0_height_0__pin_50_ ( grid_clb_2__1__undriven_bottom_width_0_height_0__pin_50_ ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_15 } ) , .ccff_tail ( grid_clb_2_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_5 ) , .SC_IN_BOT ( scff_Wires_8_ ) , - .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_6 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_16 ) , .SC_IN_BOT ( scff_Wires_8_ ) , + .SC_OUT_TOP ( scff_Wires_9_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_17 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_18 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_18 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_20 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_2 ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_4 ) ) ; grid_clb grid_clb_2__2_ ( - .prog_clk ( { ctsbuf_net_911 } ) , - .Test_en ( Test_en ) , .clk ( clk ) , + .prog_clk ( { ctsbuf_net_1315 } ) , + .Test_en ( Test_en__FEEDTHRU_3 ) , .clk ( clk__FEEDTHRU_4 ) , .top_width_0_height_0__pin_0_ ( cbx_1__2__1_bottom_grid_pin_0_ ) , .top_width_0_height_0__pin_1_ ( cbx_1__2__1_bottom_grid_pin_1_ ) , .top_width_0_height_0__pin_2_ ( cbx_1__2__1_bottom_grid_pin_2_ ) , @@ -32795,8 +33707,8 @@ grid_clb grid_clb_2__2_ ( .top_width_0_height_0__pin_13_ ( cbx_1__2__1_bottom_grid_pin_13_ ) , .top_width_0_height_0__pin_14_ ( cbx_1__2__1_bottom_grid_pin_14_ ) , .top_width_0_height_0__pin_15_ ( cbx_1__2__1_bottom_grid_pin_15_ ) , - .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , - .top_width_0_height_0__pin_33_ ( direct_interc_5_out ) , + .top_width_0_height_0__pin_32_ ( direct_interc_2_out ) , + .top_width_0_height_0__pin_33_ ( { SYNOPSYS_UNCONNECTED_19 } ) , .right_width_0_height_0__pin_16_ ( cby_2__1__1_left_grid_pin_16_ ) , .right_width_0_height_0__pin_17_ ( cby_2__1__1_left_grid_pin_17_ ) , .right_width_0_height_0__pin_18_ ( cby_2__1__1_left_grid_pin_18_ ) , @@ -32848,12 +33760,16 @@ grid_clb grid_clb_2__2_ ( .right_width_0_height_0__pin_49_upper ( grid_clb_3_right_width_0_height_0__pin_49_upper ) , .right_width_0_height_0__pin_49_lower ( grid_clb_3_right_width_0_height_0__pin_49_lower ) , .bottom_width_0_height_0__pin_50_ ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , - .bottom_width_0_height_0__pin_51_ ( { sc_out_wires_1_ } ) , + .bottom_width_0_height_0__pin_51_ ( { SYNOPSYS_UNCONNECTED_20 } ) , .ccff_tail ( grid_clb_3_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_7 ) , .SC_IN_BOT ( scff_Wires_10_ ) , - .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_8 ) ) ; -sb_0__0_ sb_0__0_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_21 ) , .SC_IN_BOT ( scff_Wires_10_ ) , + .SC_OUT_TOP ( scff_Wires_11_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_16 ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_23 } ) , + .prog_clk__FEEDTHRU_3 ( prog_clk__FEEDTHRU_14 ) , + .Test_en__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_24 } ) , + .clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_25 } ) ) ; +sb_0__0_ sb_0__0_ ( .prog_clk ( prog_clk__FEEDTHRU_2 ) , .chany_top_in ( cby_0__1__0_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__0__0_chanx_left_out ) , @@ -32867,8 +33783,7 @@ sb_0__0_ sb_0__0_ ( .chany_top_out ( sb_0__0__0_chany_top_out ) , .chanx_right_out ( sb_0__0__0_chanx_right_out ) , .ccff_tail ( ccff_tail ) ) ; -sb_0__1_ sb_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , +sb_0__1_ sb_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_5 ) , .chany_top_in ( cby_0__1__1_chany_bottom_out ) , .top_left_grid_pin_1_ ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , .chanx_right_in ( cbx_1__1__0_chanx_left_out ) , @@ -32886,9 +33801,9 @@ sb_0__1_ sb_0__1_ ( .chany_top_out ( sb_0__1__0_chany_top_out ) , .chanx_right_out ( sb_0__1__0_chanx_right_out ) , .chany_bottom_out ( sb_0__1__0_chany_bottom_out ) , - .ccff_tail ( sb_0__1__0_ccff_tail ) ) ; -sb_0__2_ sb_0__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( sb_0__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_6 ) ) ; +sb_0__2_ sb_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_8 ) , .chanx_right_in ( cbx_1__2__0_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_1_top_width_0_height_0__pin_34_upper ) , @@ -32905,10 +33820,9 @@ sb_0__2_ sb_0__2_ ( .chanx_right_out ( sb_0__2__0_chanx_right_out ) , .chany_bottom_out ( sb_0__2__0_chany_bottom_out ) , .ccff_tail ( sb_0__2__0_ccff_tail ) , .SC_IN_TOP ( sc_head ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_9 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_10 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; -sb_1__0_ sb_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_26 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_27 ) , .SC_OUT_BOT ( scff_Wires_0_ ) ) ; +sb_1__0_ sb_1__0_ ( .prog_clk ( prog_clk ) , .chany_top_in ( cby_1__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_0_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_0_right_width_0_height_0__pin_43_lower ) , @@ -32937,10 +33851,18 @@ sb_1__0_ sb_1__0_ ( .chanx_right_out ( sb_1__0__0_chanx_right_out ) , .chanx_left_out ( sb_1__0__0_chanx_left_out ) , .ccff_tail ( sb_1__0__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_6_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_11 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_12 ) , .SC_OUT_BOT ( scff_Wires_7_ ) ) ; -sb_1__1_ sb_1__1_ ( - .prog_clk ( { ctsbuf_net_1214 } ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_28 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_OUT_BOT ( scff_Wires_7_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_1 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_9 ) , + .Test_en__FEEDTHRU_0 ( Test_en ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_4 ) , + .Test_en__FEEDTHRU_2 ( Test_en__FEEDTHRU_1 ) , .clk__FEEDTHRU_0 ( clk ) , + .clk__FEEDTHRU_1 ( clk__FEEDTHRU_3 ) , + .clk__FEEDTHRU_2 ( clk__FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ) ; +sb_1__1_ sb_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_10 ) , .chany_top_in ( cby_1__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_1_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_1_right_width_0_height_0__pin_43_lower ) , @@ -32982,9 +33904,14 @@ sb_1__1_ sb_1__1_ ( .chanx_right_out ( sb_1__1__0_chanx_right_out ) , .chany_bottom_out ( sb_1__1__0_chany_bottom_out ) , .chanx_left_out ( sb_1__1__0_chanx_left_out ) , - .ccff_tail ( sb_1__1__0_ccff_tail ) ) ; + .ccff_tail ( sb_1__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_11 ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_5 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_6 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) ) ; sb_1__2_ sb_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .prog_clk ( { ctsbuf_net_1214 } ) , .chanx_right_in ( cbx_1__2__1_chanx_left_out ) , .right_top_grid_pin_1_ ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .right_bottom_grid_pin_34_ ( grid_clb_3_top_width_0_height_0__pin_34_upper ) , @@ -33019,12 +33946,14 @@ sb_1__2_ sb_1__2_ ( .chany_bottom_out ( sb_1__2__0_chany_bottom_out ) , .chanx_left_out ( sb_1__2__0_chanx_left_out ) , .ccff_tail ( sb_1__2__0_ccff_tail ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_13 ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_14 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_15 ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_16 ) ) ; + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_30 ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_31 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_32 ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_33 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) ) ; sb_2__0_ sb_2__0_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chany_top_in ( cby_2__1__0_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_2_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_2_right_width_0_height_0__pin_43_lower ) , @@ -33046,8 +33975,7 @@ sb_2__0_ sb_2__0_ ( .chany_top_out ( sb_2__0__0_chany_top_out ) , .chanx_left_out ( sb_2__0__0_chanx_left_out ) , .ccff_tail ( sb_2__0__0_ccff_tail ) ) ; -sb_2__1_ sb_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , +sb_2__1_ sb_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_19 ) , .chany_top_in ( cby_2__1__1_chany_bottom_out ) , .top_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_lower ) , .top_left_grid_pin_43_ ( grid_clb_3_right_width_0_height_0__pin_43_lower ) , @@ -33081,9 +34009,10 @@ sb_2__1_ sb_2__1_ ( .chany_top_out ( sb_2__1__0_chany_top_out ) , .chany_bottom_out ( sb_2__1__0_chany_bottom_out ) , .chanx_left_out ( sb_2__1__0_chanx_left_out ) , - .ccff_tail ( sb_2__1__0_ccff_tail ) ) ; -sb_2__2_ sb_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .ccff_tail ( sb_2__1__0_ccff_tail ) , + .Test_en__FEEDTHRU_0 ( Test_en__FEEDTHRU_2 ) , + .Test_en__FEEDTHRU_1 ( Test_en__FEEDTHRU_3 ) ) ; +sb_2__2_ sb_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_15 ) , .chany_bottom_in ( cby_2__1__1_chany_top_out ) , .bottom_right_grid_pin_1_ ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , .bottom_left_grid_pin_42_ ( grid_clb_3_right_width_0_height_0__pin_42_upper ) , @@ -33108,10 +34037,10 @@ sb_2__2_ sb_2__2_ ( .chany_bottom_out ( sb_2__2__0_chany_bottom_out ) , .chanx_left_out ( sb_2__2__0_chanx_left_out ) , .ccff_tail ( sb_2__2__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_12_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_17 ) , .SC_OUT_TOP ( sc_tail ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_18 ) ) ; + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_34 ) , .SC_OUT_TOP ( sc_tail ) , + .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_35 ) ) ; cbx_1__0_ cbx_1__0_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .prog_clk ( { ctsbuf_net_3032 } ) , .chanx_left_in ( sb_0__0__0_chanx_right_out ) , .chanx_right_in ( sb_1__0__0_chanx_left_out ) , .ccff_head ( sb_1__0__0_ccff_tail ) , @@ -33145,10 +34074,12 @@ cbx_1__0_ cbx_1__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_0_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_0_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_0_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_19 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_20 ) , .SC_OUT_BOT ( scff_Wires_6_ ) ) ; + .SC_IN_TOP ( scff_Wires_5_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_36 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_37 ) , .SC_OUT_BOT ( scff_Wires_6_ ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_2 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_3 ) ) ; cbx_1__0_ cbx_2__0_ ( - .prog_clk ( { ctsbuf_net_35 } ) , + .prog_clk ( { ctsbuf_net_3436 } ) , .chanx_left_in ( sb_1__0__0_chanx_right_out ) , .chanx_right_in ( sb_2__0__0_chanx_left_out ) , .ccff_head ( sb_2__0__0_ccff_tail ) , @@ -33182,10 +34113,11 @@ cbx_1__0_ cbx_2__0_ ( .top_width_0_height_0__pin_9_lower ( grid_io_bottom_1_top_width_0_height_0__pin_9_lower ) , .top_width_0_height_0__pin_11_upper ( grid_io_bottom_1_top_width_0_height_0__pin_11_upper ) , .top_width_0_height_0__pin_11_lower ( grid_io_bottom_1_top_width_0_height_0__pin_11_lower ) , - .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_21 ) , - .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_22 ) ) ; -cbx_1__1_ cbx_1__1_ ( - .prog_clk ( { ctsbuf_net_1416 } ) , + .SC_IN_TOP ( scff_Wires_7_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_38 ) , + .SC_OUT_TOP ( scff_Wires_8_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_39 ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_40 } ) , + .prog_clk__FEEDTHRU_2 ( { SYNOPSYS_UNCONNECTED_41 } ) ) ; +cbx_1__1_ cbx_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_4 ) , .chanx_left_in ( sb_0__1__0_chanx_right_out ) , .chanx_right_in ( sb_1__1__0_chanx_left_out ) , .ccff_head ( sb_1__1__0_ccff_tail ) , @@ -33207,12 +34139,11 @@ cbx_1__1_ cbx_1__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__0_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__0_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__0_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__0_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_0_ ) , - .CLB_SC_OUT ( sc_in_wires_0_ ) , .SC_IN_TOP ( scff_Wires_2_ ) , - .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_23 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_24 ) , .SC_OUT_BOT ( scff_Wires_3_ ) ) ; -cbx_1__1_ cbx_2__1_ ( - .prog_clk ( { ctsbuf_net_68 } ) , + .ccff_tail ( cbx_1__1__0_ccff_tail ) , .SC_IN_TOP ( scff_Wires_2_ ) , + .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_42 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_43 ) , .SC_OUT_BOT ( scff_Wires_3_ ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_44 } ) ) ; +cbx_1__1_ cbx_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_18 ) , .chanx_left_in ( sb_1__1__0_chanx_right_out ) , .chanx_right_in ( sb_2__1__0_chanx_left_out ) , .ccff_head ( sb_2__1__0_ccff_tail ) , @@ -33234,12 +34165,11 @@ cbx_1__1_ cbx_2__1_ ( .bottom_grid_pin_13_ ( cbx_1__1__1_bottom_grid_pin_13_ ) , .bottom_grid_pin_14_ ( cbx_1__1__1_bottom_grid_pin_14_ ) , .bottom_grid_pin_15_ ( cbx_1__1__1_bottom_grid_pin_15_ ) , - .ccff_tail ( cbx_1__1__1_ccff_tail ) , .CLB_SC_IN ( sc_out_wires_1_ ) , - .CLB_SC_OUT ( sc_in_wires_1_ ) , .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_25 ) , - .SC_IN_BOT ( scff_Wires_9_ ) , .SC_OUT_TOP ( scff_Wires_10_ ) , - .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_26 ) ) ; -cbx_1__2_ cbx_1__2_ ( - .prog_clk ( { ctsbuf_net_1012 } ) , + .ccff_tail ( cbx_1__1__1_ccff_tail ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_45 ) , .SC_IN_BOT ( scff_Wires_9_ ) , + .SC_OUT_TOP ( scff_Wires_10_ ) , .SC_OUT_BOT ( SYNOPSYS_UNCONNECTED_46 ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_19 ) ) ; +cbx_1__2_ cbx_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_7 ) , .chanx_left_in ( sb_0__2__0_chanx_right_out ) , .chanx_right_in ( sb_1__2__0_chanx_left_out ) , .ccff_head ( sb_1__2__0_ccff_tail ) , @@ -33269,10 +34199,10 @@ cbx_1__2_ cbx_1__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__0_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_0_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_0_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_27 ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_28 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; + .SC_IN_TOP ( scff_Wires_0_ ) , .SC_IN_BOT ( SYNOPSYS_UNCONNECTED_47 ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_48 ) , .SC_OUT_BOT ( scff_Wires_1_ ) ) ; cbx_1__2_ cbx_2__2_ ( - .prog_clk ( { ctsbuf_net_24 } ) , + .prog_clk ( { ctsbuf_net_57 } ) , .chanx_left_in ( sb_1__2__0_chanx_right_out ) , .chanx_right_in ( sb_2__2__0_chanx_left_out ) , .ccff_head ( sb_2__2__0_ccff_tail ) , @@ -33302,10 +34232,9 @@ cbx_1__2_ cbx_2__2_ ( .bottom_width_0_height_0__pin_0_ ( cbx_1__2__1_top_grid_pin_0_ ) , .bottom_width_0_height_0__pin_1_upper ( grid_io_top_1_bottom_width_0_height_0__pin_1_upper ) , .bottom_width_0_height_0__pin_1_lower ( grid_io_top_1_bottom_width_0_height_0__pin_1_lower ) , - .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_29 ) , .SC_IN_BOT ( scff_Wires_11_ ) , - .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_30 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; -cby_0__1_ cby_0__1_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .SC_IN_TOP ( SYNOPSYS_UNCONNECTED_49 ) , .SC_IN_BOT ( scff_Wires_11_ ) , + .SC_OUT_TOP ( SYNOPSYS_UNCONNECTED_50 ) , .SC_OUT_BOT ( scff_Wires_12_ ) ) ; +cby_0__1_ cby_0__1_ ( .prog_clk ( prog_clk__FEEDTHRU_3 ) , .chany_bottom_in ( sb_0__0__0_chany_top_out ) , .chany_top_in ( sb_0__1__0_chany_bottom_out ) , .ccff_head ( sb_0__1__0_ccff_tail ) , @@ -33318,9 +34247,9 @@ cby_0__1_ cby_0__1_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[16] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__0_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_0_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) ) ; -cby_0__1_ cby_0__2_ ( - .prog_clk ( { ctsbuf_net_1315 } ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_0_right_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_51 } ) ) ; +cby_0__1_ cby_0__2_ ( .prog_clk ( prog_clk__FEEDTHRU_6 ) , .chany_bottom_in ( sb_0__1__0_chany_top_out ) , .chany_top_in ( sb_0__2__0_chany_bottom_out ) , .ccff_head ( sb_0__2__0_ccff_tail ) , @@ -33333,9 +34262,9 @@ cby_0__1_ cby_0__2_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[17] ) , .right_width_0_height_0__pin_0_ ( cby_0__1__1_left_grid_pin_0_ ) , .right_width_0_height_0__pin_1_upper ( grid_io_left_1_right_width_0_height_0__pin_1_upper ) , - .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) ) ; -cby_1__1_ cby_1__1_ ( - .prog_clk ( { ctsbuf_net_79 } ) , + .right_width_0_height_0__pin_1_lower ( grid_io_left_1_right_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_8 ) ) ; +cby_1__1_ cby_1__1_ ( .prog_clk ( prog_clk__FEEDTHRU_9 ) , .chany_bottom_in ( sb_1__0__0_chany_top_out ) , .chany_top_in ( sb_1__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_0_ccff_tail ) , @@ -33357,9 +34286,12 @@ cby_1__1_ cby_1__1_ ( .left_grid_pin_29_ ( cby_1__1__0_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__0_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__0_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__0_ccff_tail ) ) ; -cby_1__1_ cby_1__2_ ( - .prog_clk ( { ctsbuf_net_810 } ) , + .ccff_tail ( cby_1__1__0_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_17 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_10 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_2 ) ) ; +cby_1__1_ cby_1__2_ ( .prog_clk ( prog_clk__FEEDTHRU_11 ) , .chany_bottom_in ( sb_1__1__0_chany_top_out ) , .chany_top_in ( sb_1__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_1_ccff_tail ) , @@ -33381,9 +34313,12 @@ cby_1__1_ cby_1__2_ ( .left_grid_pin_29_ ( cby_1__1__1_left_grid_pin_29_ ) , .left_grid_pin_30_ ( cby_1__1__1_left_grid_pin_30_ ) , .left_grid_pin_31_ ( cby_1__1__1_left_grid_pin_31_ ) , - .ccff_tail ( cby_1__1__1_ccff_tail ) ) ; -cby_2__1_ cby_2__1_ ( - .prog_clk ( { ctsbuf_net_13 } ) , + .ccff_tail ( cby_1__1__1_ccff_tail ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_13 ) , + .prog_clk__FEEDTHRU_2 ( prog_clk__FEEDTHRU_12 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_3 ) , + .grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_4 ) ) ; +cby_2__1_ cby_2__1_ ( .prog_clk ( prog_clk__FEEDTHRU_20 ) , .chany_bottom_in ( sb_2__0__0_chany_top_out ) , .chany_top_in ( sb_2__1__0_chany_bottom_out ) , .ccff_head ( grid_clb_2_ccff_tail ) , @@ -33412,9 +34347,9 @@ cby_2__1_ cby_2__1_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__0_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_0_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) ) ; -cby_2__1_ cby_2__2_ ( - .prog_clk ( { ctsbuf_net_46 } ) , + .left_width_0_height_0__pin_1_lower ( grid_io_right_0_left_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( { SYNOPSYS_UNCONNECTED_52 } ) ) ; +cby_2__1_ cby_2__2_ ( .prog_clk ( prog_clk__FEEDTHRU_14 ) , .chany_bottom_in ( sb_2__1__0_chany_top_out ) , .chany_top_in ( sb_2__2__0_chany_bottom_out ) , .ccff_head ( grid_clb_3_ccff_tail ) , @@ -33443,7 +34378,8 @@ cby_2__1_ cby_2__2_ ( .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .left_width_0_height_0__pin_0_ ( cby_2__1__1_right_grid_pin_0_ ) , .left_width_0_height_0__pin_1_upper ( grid_io_right_1_left_width_0_height_0__pin_1_upper ) , - .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) ) ; + .left_width_0_height_0__pin_1_lower ( grid_io_right_1_left_width_0_height_0__pin_1_lower ) , + .prog_clk__FEEDTHRU_1 ( prog_clk__FEEDTHRU_15 ) ) ; direct_interc_0 direct_interc_0_ ( .in ( grid_clb_1_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_0_out ) ) ; @@ -33451,45 +34387,32 @@ direct_interc_1 direct_interc_1_ ( .in ( grid_clb_3_bottom_width_0_height_0__pin_50_ ) , .out ( direct_interc_1_out ) ) ; direct_interc_2 direct_interc_2_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_50_ ) , + .in ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_5 ) , .out ( direct_interc_2_out ) ) ; -direct_interc_5 direct_interc_5_ ( - .in ( grid_clb_0_bottom_width_0_height_0__pin_51_ ) , - .out ( direct_interc_5_out ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78798147 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_13 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78808148 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_24 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78838151 ( .A ( ctsbuf_net_1618 ) , +sky130_fd_sc_hd__clkinvlp_4 cts_inv_82258498 ( .A ( ctsbuf_net_79 ) , .Y ( ctsbuf_net_57 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78848152 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_68 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78858153 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_79 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78868154 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_810 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78878155 ( .A ( ctsbuf_net_1618 ) , - .Y ( ctsbuf_net_911 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78888156 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1012 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78898157 ( .A ( ctsbuf_net_1719 ) , - .Y ( ctsbuf_net_1113 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78918159 ( .A ( ctsbuf_net_1719 ) , +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82338506 ( + .A ( prog_clk__FEEDTHRU_16[0] ) , .Y ( ctsbuf_net_79 ) ) ; +sky130_fd_sc_hd__inv_2 cts_inv_82628535 ( .A ( ctsbuf_net_1416 ) , + .Y ( ctsbuf_net_1214 ) ) ; +sky130_fd_sc_hd__clkinv_16 cts_inv_82668539 ( .A ( ctsbuf_net_1517 ) , .Y ( ctsbuf_net_1315 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_78938161 ( .A ( ctsbuf_net_1618 ) , +sky130_fd_sc_hd__clkinvlp_2 cts_inv_82708543 ( + .A ( prog_clk__FEEDTHRU_12[0] ) , .Y ( ctsbuf_net_1416 ) ) ; +sky130_fd_sc_hd__inv_4 cts_inv_82748547 ( .A ( prog_clk__FEEDTHRU_13[0] ) , .Y ( ctsbuf_net_1517 ) ) ; -sky130_fd_sc_hd__inv_8 cts_inv_78828150_78948162 ( - .A ( SYNOPSYS_UNCONNECTED_31 ) , .Y ( SYNOPSYS_UNCONNECTED_32 ) ) ; -sky130_fd_sc_hd__inv_6 cts_inv_78818149_78958163 ( - .A ( SYNOPSYS_UNCONNECTED_33 ) , .Y ( SYNOPSYS_UNCONNECTED_34 ) ) ; -sky130_fd_sc_hd__clkinv_16 cts_inv_78908158_78968164 ( - .A ( SYNOPSYS_UNCONNECTED_35 ) , .Y ( SYNOPSYS_UNCONNECTED_36 ) ) ; -sky130_fd_sc_hd__bufinv_8 cts_inv_78928160_78978165 ( - .A ( SYNOPSYS_UNCONNECTED_37 ) , .Y ( SYNOPSYS_UNCONNECTED_38 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79058173 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1618 ) ) ; -sky130_fd_sc_hd__clkinvlp_2 cts_inv_79068174 ( .A ( prog_clk[0] ) , - .Y ( ctsbuf_net_1719 ) ) ; +sky130_fd_sc_hd__clkinv_4 cts_inv_83388611 ( .A ( ctsbuf_net_2931 ) , + .Y ( ctsbuf_net_2729 ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83468619 ( + .A ( prog_clk__FEEDTHRU_17[0] ) , .Y ( ctsbuf_net_2931 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83518624 ( .A ( ctsbuf_net_3234 ) , + .Y ( ctsbuf_net_3032 ) ) ; +sky130_fd_sc_hd__clkinvlp_4 cts_inv_83598632 ( + .A ( prog_clk__FEEDTHRU_1[0] ) , .Y ( ctsbuf_net_3234 ) ) ; +sky130_fd_sc_hd__clkinv_2 cts_inv_83688641 ( .A ( ctsbuf_net_3537 ) , + .Y ( ctsbuf_net_3436 ) ) ; +sky130_fd_sc_hd__clkinvlp_2 cts_inv_83728645 ( .A ( prog_clk[0] ) , + .Y ( ctsbuf_net_3537 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv index c8b8a00..9003771 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/module_utilization.tsv @@ -1,18 +1,18 @@ | Module | Util| Area| Sites| Insts| Std_Cells |--------------------|----------|-----------------|-------|-------|------- -| sb_0__0_ | 37.06 | 6606.336000 | 5280 | 1 | 85 -| sb_0__1_ | 61.64 | 7687.372800 | 6144 | 1 | 116 -| sb_0__2_ | 42.08 | 6606.336000 | 5280 | 1 | 85 -| sb_1__0_ | 64.92 | 7807.488000 | 6240 | 1 | 125 -| sb_1__1_ | 81.63 | 8888.524800 | 7104 | 1 | 117 -| sb_1__2_ | 69.36 | 7807.488000 | 6240 | 1 | 136 -| sb_2__0_ | 50.93 | 6606.336000 | 5280 | 1 | 94 -| sb_2__1_ | 73.86 | 7687.372800 | 6144 | 1 | 123 -| sb_2__2_ | 58.11 | 6606.336000 | 5280 | 1 | 95 -| cbx_1__0_ | 60.07 | 5044.838400 | 4032 | 2 | 130 -| cbx_1__1_ | 79.61 | 5044.838400 | 4032 | 2 | 86 -| cbx_1__2_ | 81.82 | 5044.838400 | 4032 | 2 | 82 -| cby_0__1_ | 30.11 | 5044.838400 | 4032 | 2 | 109 -| cby_1__1_ | 80.46 | 5044.838400 | 4032 | 2 | 88 -| cby_2__1_ | 67.51 | 5044.838400 | 4032 | 2 | 38 -| grid_clb_1__1_ | 75.03 | 12411.904000 | 9920 | 4 | 56 +| sb_0__0_ | 27.75 | 9068.697600 | 7248 | 1 | 95 +| sb_0__1_ | 51.68 | 9809.408000 | 7840 | 1 | 138 +| sb_0__2_ | 31.95 | 9068.697600 | 7248 | 1 | 96 +| sb_1__0_ | 46.31 | 11471.001600 | 9168 | 1 | 150 +| sb_1__1_ | 66.68 | 12211.712000 | 9760 | 1 | 185 +| sb_1__2_ | 48.12 | 11471.001600 | 9168 | 1 | 140 +| sb_2__0_ | 40.31 | 9068.697600 | 7248 | 1 | 107 +| sb_2__1_ | 60.96 | 9809.408000 | 7840 | 1 | 151 +| sb_2__2_ | 41.16 | 9068.697600 | 7248 | 1 | 89 +| cbx_1__0_ | 54.01 | 5925.683200 | 4736 | 2 | 140 +| cbx_1__1_ | 74.16 | 5925.683200 | 4736 | 2 | 112 +| cbx_1__2_ | 76.12 | 5925.683200 | 4736 | 2 | 104 +| cby_0__1_ | 29.85 | 5184.972800 | 4144 | 2 | 106 +| cby_1__1_ | 79.92 | 5184.972800 | 4144 | 2 | 95 +| cby_2__1_ | 80.91 | 5184.972800 | 4144 | 2 | 87 +| grid_clb_1__1_ | 76.73 | 12071.577600 | 9648 | 4 | 52 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv new file mode 100644 index 0000000..b071cf4 --- /dev/null +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/std_cell_utilization.tsv @@ -0,0 +1,31 @@ + Ref Name Total Area Utilization_% Instance Count + ---------------------------------------------------------------------------------------------------- + sky130_fd_sc_hd__mux2_1 33410.793600 6.86 2967 + sky130_fd_sc_hd__dfxbp_1 31285.004800 6.43 1316 + sky130_fd_sc_hd__dlymetal6s2s_1 9258.880000 1.90 740 + sky130_fd_sc_hd__dlymetal6s6s_1 9071.200000 1.86 725 + sky130_fd_sc_hd__dlygate4sd3_1 5695.462400 1.17 569 + sky130_fd_sc_hd__buf_4 2552.448000 0.52 340 + sky130_fd_sc_hd__dlygate4sd2_1 1769.196800 0.36 202 + sky130_fd_sc_hd__sdfxtp_1 1681.612800 0.35 64 + sky130_fd_sc_hd__mux2_8 1208.659200 0.25 46 + sky130_fd_sc_hd__dlygate4sd1_1 613.088000 0.13 70 + sky130_fd_sc_hd__buf_2 375.360000 0.08 75 + sky130_fd_sc_hd__inv_1 375.360000 0.08 100 + sky130_fd_sc_hd__conb_1 326.563200 0.07 87 + sky130_fd_sc_hd__or2_0 200.192000 0.04 32 + sky130_fd_sc_hd__buf_6 135.129600 0.03 12 + sky130_fd_sc_hd__buf_12 80.076800 0.02 4 + sky130_fd_sc_hd__buf_8 75.072000 0.02 5 + sky130_fd_sc_hd__clkbuf_1 60.057600 0.01 16 + sky130_fd_sc_hd__clkinv_16 30.028800 0.01 1 + sky130_fd_sc_hd__clkdlybuf4s50_2 22.521600 0.00 2 + sky130_fd_sc_hd__clkinvlp_4 22.521600 0.00 3 + sky130_fd_sc_hd__clkinvlp_2 20.019200 0.00 4 + sky130_fd_sc_hd__clkinv_4 8.758400 0.00 1 + sky130_fd_sc_hd__inv_4 6.256000 0.00 1 + sky130_fd_sc_hd__clkinv_2 5.004800 0.00 1 + sky130_fd_sc_hd__inv_2 3.753600 0.00 1 +FPGA_BBOX_AREA 229900.4928 +CORE_BBOX_AREA 486866.944 +FPGA_BBOX_UTIL 47.2203947368 diff --git a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt index 6d96902..8f16ed6 100644 --- a/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt +++ b/FPGA22_HIER_SKY_PNR/fpga_core/rpts_icc2/timing_reports.txt @@ -6,7 +6,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Fri Nov 6 22:19:36 2020 +Date : Sun Nov 8 18:28:15 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.061 0.000 -- 0.039 0.039 rp-+ nominal + grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.162 0.000 -- 0.429 0.429 rp-+ nominal --------------------------------------------------------------------------------------------------- Mode: full_chip @@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.187 0.000 -- 5.545 5.545 rp-+ nominal + sb_0__2_/mem_right_track_0/sky130_fd_sc_hd__dfxbp_1_1_/CLK 0.347 0.000 -- 4.898 4.898 rp-+ nominal --------------------------------------------------------------------------------------------------- **************************************** Report : clock timing @@ -34,7 +34,7 @@ Report : clock timing -setup Design : fpga_core Version: P-2019.03-SP4 -Date : Fri Nov 6 22:19:36 2020 +Date : Sun Nov 8 18:28:15 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - grid_clb_1__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.032 rp-+ nominal - grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.020 0.000 0.011 rp-+ nominal + grid_clb_2__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.427 rp-+ nominal + grid_clb_2__1_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfxtp_1_0_/CLK 0.026 0.000 0.401 rp-+ nominal --------------------------------------------------------------------------------------------------- @@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysi Clock Pin Latency CRP Skew Corner --------------------------------------------------------------------------------------------------- - sb_1__2_/mem_left_track_33/sky130_fd_sc_hd__dfxbp_1_2_/CLK 5.061 rp-+ nominal - cbx_1__2_/mem_bottom_ipin_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.276 0.000 1.785 rp-+ nominal + cby_2__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem/sky130_fd_sc_hd__dfxbp_1_0_/CLK 3.374 rp-+ nominal + sb_2__0_/mem_top_track_0/sky130_fd_sc_hd__dfxbp_1_0_/CLK 0.949 0.000 2.424 rp-+ nominal --------------------------------------------------------------------------------------------------- Information: Timer using 'PrimeTime Delay Calculation, SI, Timing Window Analysis, AWP, CRPR'. (TIM-050) @@ -63,7 +63,7 @@ Report : global timing -format { narrow } Design : fpga_core Version: P-2019.03-SP4 -Date : Fri Nov 6 22:19:36 2020 +Date : Sun Nov 8 18:28:15 2020 **************************************** No setup violations found. @@ -73,8 +73,8 @@ Hold violations -------------------------------------------------------------- Total reg->reg in->reg reg->out in->out -------------------------------------------------------------- -WNS -0.632 -0.632 0.000 0.000 0.000 -TNS -0.750 -0.750 0.000 0.000 0.000 +WNS -1.248 -1.248 0.000 0.000 0.000 +TNS -1.390 -1.390 0.000 0.000 0.000 NUM 2 2 0 0 0 -------------------------------------------------------------- diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds index b5d8846..9042e43 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cbx_1__0__icv_in_design.gds @@ -1,3 +1,3 @@ version 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100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cby_1__1__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cby_1__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9876a9727f1443f97ddb386f511f77a73dc7f085a5f7401e84f453f9eb381b5b -size 4440064 +oid sha256:c856f58946f08034f5a317ee687814d9cbbf4e35ff4059e175592e19b9edf7f3 +size 4442112 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds index 3a2d36a..dcbb030 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/cby_2__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:a78fb55f7c0cb8fa1b8b010733445e79b948edb606f485e0a0c492a3b79d4e10 -size 4448256 +oid sha256:8ba610a994fea55c20cce268ef93cad632093794a1ab3a5cc8107b2075c7feb5 +size 4462592 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__0__icv_in_design.gds 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--git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds index 178aed7..3a3b7f0 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_0__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:49f68d0c25b553ed40cc406d06676f9b9762e22772270aa8de0dc43dee3dffe5 -size 4382720 +oid sha256:c23bd0ba7c739bded4092def6cd2f70546716f82bf0e30bf1afef37561bb30c4 +size 4411392 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds index 707a7e7..9a44f88 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__0__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:58fa9e3ce3287711782e7590680af82516b2aa48a904308fe948600ec71c47eb -size 4524032 +oid sha256:9bd943078017d06950cfa96dec21283456778eeda161feff1b6473a867889e69 +size 4560896 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__1__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__1__icv_in_design.gds index 4f7facb..e25363a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__1__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a75524d80bdd5c176378468623af1525a1dbc7533f30df677ecd34944e87caa -size 4679680 +oid sha256:71edb34c5caaac5b3b94399becb414574d3ba04499602cdd4087a16983410778 +size 4743168 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__2__icv_in_design.gds index 7814d6f..a608b59 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_1__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid 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b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__1__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:b5a3320717997883f84b73efb84312db9bcbbc600d98fe8fc95ce7f861d52cf6 -size 4548608 +oid sha256:8a6c6106d0166613a13fe9cad825083429eab5a3c9685937725a654a7b0a309e +size 4581376 diff --git a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds index 504d806..fb6bf39 100644 --- a/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds +++ b/FPGA22_HIER_SKY_PNR/modules/gds/sb_2__2__icv_in_design.gds @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:9bc4ec1356934628f5e0e246abc9a1b49dc63923ebfbd0959a8fca566d907bae -size 4427776 +oid sha256:1455eceae4c5e5fbed3bd7000d74bb83c8e14596164ad104608ac7756187f26f +size 4444160 diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef index 2e3a72d..cb9a5d3 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 77.28 BY 65.28 ; + SIZE 68.08 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 2.23 63.92 2.37 65.28 ; + LAYER met3 ; + RECT 66.7 13.45 68.08 13.75 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 24.33 1.38 24.63 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -483,7 +483,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,15 +491,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[15] PIN chanx_left_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.99 0 5.13 1.36 ; + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -507,7 +507,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 67.85 1.38 68.15 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 58.33 77.28 58.63 ; + RECT 66.7 44.73 68.08 45.03 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 56.97 77.28 57.27 ; + RECT 66.7 56.97 68.08 57.27 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,15 +547,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 39.97 77.28 40.27 ; + RECT 66.7 59.69 68.08 59.99 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 73.07 63.92 73.21 65.28 ; + LAYER met3 ; + RECT 66.7 75.33 68.08 75.63 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.25 77.28 54.55 ; + RECT 66.7 20.25 68.08 20.55 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,15 +571,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 61.05 77.28 61.35 ; + RECT 66.7 61.05 68.08 61.35 ; END END chanx_right_in[5] PIN chanx_right_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 73.99 0 74.13 1.36 ; + LAYER met3 ; + RECT 66.7 78.73 68.08 79.03 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 59.69 77.28 59.99 ; + RECT 66.7 8.69 68.08 8.99 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,15 +595,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 31.81 77.28 32.11 ; + RECT 66.7 35.21 68.08 35.51 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 74.91 0 75.05 1.36 ; + LAYER met3 ; + RECT 66.7 52.89 68.08 53.19 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.89 77.28 19.19 ; + RECT 66.7 46.09 68.08 46.39 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 34.53 77.28 34.83 ; + RECT 66.7 82.81 68.08 83.11 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 29.09 77.28 29.39 ; + RECT 66.7 65.13 68.08 65.43 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.01 77.28 8.31 ; + RECT 66.7 16.17 68.08 16.47 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 25.69 77.28 25.99 ; + RECT 66.7 28.41 68.08 28.71 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 17.53 77.28 17.83 ; + RECT 66.7 37.93 68.08 38.23 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 33.17 77.28 33.47 ; + RECT 66.7 25.01 68.08 25.31 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.81 77.28 15.11 ; + RECT 66.7 69.21 68.08 69.51 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 27.05 77.28 27.35 ; + RECT 66.7 66.49 68.08 66.79 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.73 77.28 11.03 ; + RECT 66.7 71.25 68.08 71.55 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 13.45 77.28 13.75 ; + RECT 66.7 11.41 68.08 11.71 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 76.69 1.38 76.99 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 25.69 1.38 25.99 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -715,23 +715,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 13.45 1.38 13.75 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.15 0 3.29 1.36 ; + LAYER met3 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[3] PIN chanx_left_out[4] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + LAYER met3 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 27.05 1.38 27.35 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,15 +763,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 0 4.21 1.36 ; + LAYER met3 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -779,7 +779,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 21.61 1.38 21.91 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,7 +803,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -811,15 +811,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_out[14] PIN chanx_left_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 0 4.75 1.36 ; + LAYER met3 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 22.97 1.38 23.27 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 9.37 1.38 9.67 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -851,7 +851,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -859,7 +859,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 3.93 77.28 4.23 ; + RECT 66.7 76.69 68.08 76.99 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 55.61 77.28 55.91 ; + RECT 66.7 63.77 68.08 64.07 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 38.61 77.28 38.91 ; + RECT 66.7 58.33 68.08 58.63 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.09 77.28 12.39 ; + RECT 66.7 73.97 68.08 74.27 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.89 77.28 53.19 ; + RECT 66.7 23.65 68.08 23.95 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 16.17 77.28 16.47 ; + RECT 66.7 36.57 68.08 36.87 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,15 +907,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.25 77.28 20.55 ; + RECT 66.7 55.61 68.08 55.91 ; END END chanx_right_out[6] PIN chanx_right_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 72.15 63.92 72.29 65.28 ; + LAYER met3 ; + RECT 66.7 29.77 68.08 30.07 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 9.37 77.28 9.67 ; + RECT 66.7 26.37 68.08 26.67 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 21.61 77.28 21.91 ; + RECT 66.7 10.05 68.08 10.35 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,15 +939,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 41.33 77.28 41.63 ; + RECT 66.7 50.17 68.08 50.47 ; END END chanx_right_out[10] PIN chanx_right_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 73.99 63.92 74.13 65.28 ; + LAYER met3 ; + RECT 66.7 33.85 68.08 34.15 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,23 +955,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 5.29 77.28 5.59 ; + RECT 66.7 62.41 68.08 62.71 ; END END chanx_right_out[12] PIN chanx_right_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 72.53 63.92 72.83 65.28 ; + LAYER met3 ; + RECT 66.7 72.61 68.08 72.91 ; END END chanx_right_out[13] PIN chanx_right_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 74.91 63.92 75.05 65.28 ; + LAYER met3 ; + RECT 66.7 18.89 68.08 19.19 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.17 77.28 50.47 ; + RECT 66.7 39.29 68.08 39.59 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 47.45 77.28 47.75 ; + RECT 66.7 43.37 68.08 43.67 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 51.53 77.28 51.83 ; + RECT 66.7 32.49 68.08 32.79 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 22.97 77.28 23.27 ; + RECT 66.7 31.13 68.08 31.43 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,15 +1011,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 24.33 77.28 24.63 ; + RECT 66.7 17.53 68.08 17.83 ; END END chanx_right_out[19] PIN bottom_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 71.23 63.92 71.37 65.28 ; + LAYER met3 ; + RECT 66.7 5.97 68.08 6.27 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_2_[0] @@ -1027,23 +1027,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 63.92 23.53 65.28 ; + RECT 34.89 85.68 35.03 87.04 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_4_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + LAYER met3 ; + RECT 0 14.81 1.38 15.11 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_6_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.53 63.92 4.67 65.28 ; + LAYER met3 ; + RECT 0 16.17 1.38 16.47 ; END END bottom_grid_pin_6_[0] PIN bottom_grid_pin_8_[0] @@ -1051,15 +1051,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.57 63.92 15.71 65.28 ; + RECT 18.33 0 18.47 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_10_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 63.41 63.92 63.55 65.28 ; + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; END END bottom_grid_pin_10_[0] PIN ccff_tail[0] @@ -1067,7 +1067,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 12.09 1.38 12.39 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1075,7 +1075,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[1] @@ -1083,7 +1083,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 21.09 0 21.23 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[1] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[2] @@ -1091,7 +1091,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[2] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[3] @@ -1099,7 +1099,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[3] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[4] @@ -1107,7 +1107,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[4] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[5] @@ -1115,7 +1115,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[5] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + RECT 35.35 0 35.49 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[1] @@ -1131,7 +1131,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 4.07 0 4.21 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[1] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[2] @@ -1139,7 +1139,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 14.65 0 14.79 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[2] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[3] @@ -1147,7 +1147,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[3] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[4] @@ -1155,7 +1155,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.25 0 65.39 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[4] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[5] @@ -1163,7 +1163,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 24.31 0 24.45 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[5] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1171,7 +1171,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 36.27 0 36.41 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[1] @@ -1179,7 +1179,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[1] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[2] @@ -1187,7 +1187,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 28.91 0 29.05 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[2] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[3] @@ -1195,7 +1195,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[3] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[4] @@ -1203,7 +1203,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[4] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[5] @@ -1211,15 +1211,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 8.67 0 8.81 1.36 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[5] PIN top_width_0_height_0__pin_0_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 69.39 63.92 69.53 65.28 ; + LAYER met3 ; + RECT 66.7 7.33 68.08 7.63 ; END END top_width_0_height_0__pin_0_[0] PIN top_width_0_height_0__pin_2_[0] @@ -1227,23 +1227,23 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 63.92 22.61 65.28 ; + RECT 33.97 85.68 34.11 87.04 ; END END top_width_0_height_0__pin_2_[0] PIN top_width_0_height_0__pin_4_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; END END top_width_0_height_0__pin_4_[0] PIN top_width_0_height_0__pin_6_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 63.92 3.75 65.28 ; + LAYER met3 ; + RECT 0 20.25 1.38 20.55 ; END END top_width_0_height_0__pin_6_[0] PIN top_width_0_height_0__pin_8_[0] @@ -1251,15 +1251,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.49 63.92 16.63 65.28 ; + RECT 19.25 0 19.39 1.36 ; END END top_width_0_height_0__pin_8_[0] PIN top_width_0_height_0__pin_10_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 64.33 63.92 64.47 65.28 ; + LAYER met3 ; + RECT 0 36.57 1.38 36.87 ; END END top_width_0_height_0__pin_10_[0] PIN top_width_0_height_0__pin_1_upper[0] @@ -1267,7 +1267,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 60.37 1.38 60.67 ; END END top_width_0_height_0__pin_1_upper[0] PIN top_width_0_height_0__pin_1_lower[0] @@ -1275,7 +1275,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.05 77.28 44.35 ; + RECT 66.7 54.25 68.08 54.55 ; END END top_width_0_height_0__pin_1_lower[0] PIN top_width_0_height_0__pin_3_upper[0] @@ -1283,7 +1283,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 56.97 1.38 57.27 ; END END top_width_0_height_0__pin_3_upper[0] PIN top_width_0_height_0__pin_3_lower[0] @@ -1291,7 +1291,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 48.81 77.28 49.11 ; + RECT 66.7 51.53 68.08 51.83 ; END END top_width_0_height_0__pin_3_lower[0] PIN top_width_0_height_0__pin_5_upper[0] @@ -1299,7 +1299,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 66.49 1.38 66.79 ; END END top_width_0_height_0__pin_5_upper[0] PIN top_width_0_height_0__pin_5_lower[0] @@ -1307,7 +1307,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 36.57 77.28 36.87 ; + RECT 66.7 40.65 68.08 40.95 ; END END top_width_0_height_0__pin_5_lower[0] PIN top_width_0_height_0__pin_7_upper[0] @@ -1315,7 +1315,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 43.37 1.38 43.67 ; END END top_width_0_height_0__pin_7_upper[0] PIN top_width_0_height_0__pin_7_lower[0] @@ -1323,7 +1323,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 30.45 77.28 30.75 ; + RECT 66.7 67.85 68.08 68.15 ; END END top_width_0_height_0__pin_7_lower[0] PIN top_width_0_height_0__pin_9_upper[0] @@ -1331,7 +1331,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 69.21 1.38 69.51 ; END END top_width_0_height_0__pin_9_upper[0] PIN top_width_0_height_0__pin_9_lower[0] @@ -1339,7 +1339,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.69 77.28 42.99 ; + RECT 66.7 42.01 68.08 42.31 ; END END top_width_0_height_0__pin_9_lower[0] PIN top_width_0_height_0__pin_11_upper[0] @@ -1347,7 +1347,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 55.61 1.38 55.91 ; END END top_width_0_height_0__pin_11_upper[0] PIN top_width_0_height_0__pin_11_lower[0] @@ -1355,7 +1355,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.09 77.28 46.39 ; + RECT 66.7 48.13 68.08 48.43 ; END END top_width_0_height_0__pin_11_lower[0] PIN SC_IN_TOP @@ -1363,15 +1363,15 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 63.92 70.45 65.28 ; + RECT 53.75 85.68 53.89 87.04 ; END END SC_IN_TOP PIN SC_IN_BOT DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 37.65 63.92 37.79 65.28 ; + LAYER met3 ; + RECT 0 8.01 1.38 8.31 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1379,7 +1379,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 63.92 21.69 65.28 ; + RECT 10.97 85.68 11.11 87.04 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1387,7 +1387,7 @@ MACRO cbx_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 6.65 77.28 6.95 ; + RECT 66.7 22.29 68.08 22.59 ; END END SC_OUT_BOT PIN VDD @@ -1395,40 +1395,48 @@ MACRO cbx_1__0_ USE POWER ; PORT LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 74.08 10.64 77.28 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 74.08 51.44 77.28 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 64.88 11.32 68.08 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 64.88 52.12 68.08 55.32 ; LAYER met4 ; - RECT 23.62 0 24.22 0.6 ; - RECT 53.06 0 53.66 0.6 ; - RECT 23.62 64.68 24.22 65.28 ; - RECT 53.06 64.68 53.66 65.28 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 86.44 12.26 87.04 ; + RECT 41.1 86.44 41.7 87.04 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 76.8 2.48 77.28 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 76.8 7.92 77.28 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 76.8 13.36 77.28 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 76.8 18.8 77.28 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 76.8 24.24 77.28 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 76.8 29.68 77.28 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 76.8 35.12 77.28 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 76.8 40.56 77.28 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 76.8 46 77.28 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 76.8 51.44 77.28 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 76.8 56.88 77.28 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 76.8 62.32 77.28 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 67.6 78.64 68.08 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 67.6 84.08 68.08 84.56 ; END END VDD PIN VSS @@ -1436,409 +1444,439 @@ MACRO cbx_1__0_ USE GROUND ; PORT LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 74.08 31.04 77.28 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 64.88 31.72 68.08 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 64.88 72.52 68.08 75.72 ; LAYER met4 ; - RECT 8.9 0 9.5 0.6 ; - RECT 38.34 0 38.94 0.6 ; - RECT 67.78 0 68.38 0.6 ; - RECT 8.9 64.68 9.5 65.28 ; - RECT 38.34 64.68 38.94 65.28 ; - RECT 67.78 64.68 68.38 65.28 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 86.44 26.98 87.04 ; + RECT 55.82 86.44 56.42 87.04 ; LAYER met1 ; - RECT 0 0 77.28 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 76.8 5.2 77.28 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 76.8 10.64 77.28 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 76.8 16.08 77.28 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 76.8 21.52 77.28 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 76.8 26.96 77.28 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 76.8 32.4 77.28 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 76.8 37.84 77.28 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 76.8 43.28 77.28 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 76.8 48.72 77.28 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 76.8 54.16 77.28 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 76.8 59.6 77.28 60.08 ; - RECT 0 65.04 77.28 65.28 ; + RECT 67.6 59.6 68.08 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 67.6 75.92 68.08 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 67.6 81.36 68.08 81.84 ; + RECT 0 86.8 68.08 87.04 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 6.65 1.38 6.95 ; + END + END prog_clk__FEEDTHRU_1[0] + PIN prog_clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 2.23 85.68 2.37 87.04 ; + END + END prog_clk__FEEDTHRU_2[0] OBS LAYER li1 ; - RECT 0 65.195 77.28 65.365 ; - RECT 76.36 62.475 77.28 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 76.36 57.035 77.28 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 76.36 54.315 77.28 54.485 ; + RECT 0 86.955 68.08 87.125 ; + RECT 67.62 84.235 68.08 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 67.16 81.515 68.08 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 67.16 78.795 68.08 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 67.16 76.075 68.08 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 67.16 70.635 68.08 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 67.16 67.915 68.08 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 67.16 65.195 68.08 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 67.16 62.475 68.08 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 67.16 59.755 68.08 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 67.16 57.035 68.08 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 76.36 51.595 77.28 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 76.36 48.875 77.28 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 76.36 46.155 77.28 46.325 ; + RECT 67.16 46.155 68.08 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 76.36 43.435 77.28 43.605 ; + RECT 67.16 43.435 68.08 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 76.36 40.715 77.28 40.885 ; + RECT 67.16 40.715 68.08 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 76.36 37.995 77.28 38.165 ; + RECT 67.16 37.995 68.08 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 76.36 35.275 77.28 35.445 ; + RECT 67.16 35.275 68.08 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 76.36 32.555 77.28 32.725 ; + RECT 67.16 32.555 68.08 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 76.36 29.835 77.28 30.005 ; + RECT 67.16 29.835 68.08 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 76.36 27.115 77.28 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 76.36 24.395 77.28 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 76.36 21.675 77.28 21.845 ; + RECT 67.16 27.115 68.08 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 67.16 24.395 68.08 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 67.16 21.675 68.08 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 76.36 18.955 77.28 19.125 ; + RECT 67.16 18.955 68.08 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 76.36 16.235 77.28 16.405 ; + RECT 67.16 16.235 68.08 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 76.36 13.515 77.28 13.685 ; + RECT 67.16 13.515 68.08 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 76.36 10.795 77.28 10.965 ; + RECT 67.16 10.795 68.08 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 76.36 8.075 77.28 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 76.36 5.355 77.28 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 76.36 2.635 77.28 2.805 ; + RECT 64.4 5.355 68.08 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 64.4 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 77.28 0.085 ; - LAYER met2 ; - RECT 67.94 65.095 68.22 65.465 ; - RECT 38.5 65.095 38.78 65.465 ; - RECT 9.06 65.095 9.34 65.465 ; - RECT 64.73 1.54 64.99 1.86 ; - RECT 67.94 -0.185 68.22 0.185 ; - RECT 38.5 -0.185 38.78 0.185 ; - RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 74.41 0.28 74.41 1.64 73.71 1.64 73.71 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.41 0.28 5.41 1.64 4.71 1.64 4.71 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 15.29 65 15.29 63.64 15.99 63.64 15.99 65 16.21 65 16.21 63.64 16.91 63.64 16.91 65 21.27 65 21.27 63.64 21.97 63.64 21.97 65 22.19 65 22.19 63.64 22.89 63.64 22.89 65 23.11 65 23.11 63.64 23.81 63.64 23.81 65 37.37 65 37.37 63.64 38.07 63.64 38.07 65 63.13 65 63.13 63.64 63.83 63.64 63.83 65 64.05 65 64.05 63.64 64.75 63.64 64.75 65 69.11 65 69.11 63.64 69.81 63.64 69.81 65 70.03 65 70.03 63.64 70.73 63.64 70.73 65 70.95 65 70.95 63.64 71.65 63.64 71.65 65 71.87 65 71.87 63.64 72.57 63.64 72.57 65 72.79 65 72.79 63.64 73.49 63.64 73.49 65 73.71 65 73.71 63.64 74.41 63.64 74.41 65 74.63 65 74.63 63.64 75.33 63.64 75.33 65 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met3 ; - POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; - POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; - POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - POLYGON 4.75 59.99 4.75 59.69 1.23 59.69 1.23 59.97 1.78 59.97 1.78 59.99 ; - POLYGON 2.005 53.885 2.005 53.87 37.87 53.87 37.87 53.57 2.005 53.57 2.005 53.555 1.675 53.555 1.675 53.885 ; - POLYGON 2.005 41.645 2.005 41.63 11.65 41.63 11.65 41.33 2.005 41.33 2.005 41.315 1.675 41.315 1.675 41.33 1.23 41.33 1.23 41.63 1.675 41.63 1.675 41.645 ; - POLYGON 75.63 31.44 75.63 31.12 75.25 31.12 75.25 31.13 69.77 31.13 69.77 31.43 75.25 31.43 75.25 31.44 ; - POLYGON 9.81 25.31 9.81 25.01 1.78 25.01 1.78 25.03 1.08 25.03 1.08 25.31 ; - POLYGON 2.03 23.96 2.03 23.95 30.51 23.95 30.51 23.65 2.03 23.65 2.03 23.64 1.65 23.64 1.65 23.96 ; - POLYGON 13.95 22.59 13.95 22.29 1.78 22.29 1.78 22.31 1.23 22.31 1.23 22.59 ; - POLYGON 7.05 21.23 7.05 20.93 1.99 20.93 1.99 20.25 1.78 20.25 1.78 20.95 1.69 20.95 1.69 21.23 ; - POLYGON 76.05 15.79 76.05 15.51 75.5 15.51 75.5 15.49 38.03 15.49 38.03 15.79 ; - POLYGON 12.57 11.71 12.57 11.41 1.99 11.41 1.99 10.73 1.78 10.73 1.78 11.43 1.69 11.43 1.69 11.71 ; - POLYGON 25.91 8.99 25.91 8.69 1.78 8.69 1.78 8.71 1.23 8.71 1.23 8.99 ; - POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; - POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; - POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 44.75 75.5 44.75 75.5 43.65 76.88 43.65 76.88 43.39 75.5 43.39 75.5 42.29 76.88 42.29 76.88 42.03 75.5 42.03 75.5 40.93 76.88 40.93 76.88 40.67 75.5 40.67 75.5 39.57 76.88 39.57 76.88 39.31 75.5 39.31 75.5 38.21 76.88 38.21 76.88 37.27 75.5 37.27 75.5 36.17 76.88 36.17 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.87 75.5 33.87 75.5 32.77 76.88 32.77 76.88 32.51 75.5 32.51 75.5 31.41 76.88 31.41 76.88 31.15 75.5 31.15 75.5 30.05 76.88 30.05 76.88 29.79 75.5 29.79 75.5 28.69 76.88 28.69 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; - LAYER met4 ; - POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 72.13 64.88 72.13 63.52 73.23 63.52 73.23 64.88 ; + POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; + POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; + POLYGON 1.99 69.51 1.99 68.83 6.59 68.83 6.59 68.53 1.69 68.53 1.69 68.81 1.78 68.81 1.78 69.51 ; + POLYGON 1.545 56.605 1.545 56.59 1.99 56.59 1.99 55.61 1.78 55.61 1.78 56.31 1.215 56.31 1.215 56.605 ; + POLYGON 6.13 52.51 6.13 52.21 1.23 52.21 1.23 52.49 1.78 52.49 1.78 52.51 ; + POLYGON 1.545 47.085 1.545 47.07 11.19 47.07 11.19 46.77 1.545 46.77 1.545 46.755 1.215 46.755 1.215 47.085 ; + POLYGON 15.33 38.91 15.33 38.61 1.99 38.61 1.99 37.93 1.78 37.93 1.78 38.63 1.69 38.63 1.69 38.91 ; + POLYGON 1.545 37.565 1.545 37.55 20.39 37.55 20.39 37.25 1.545 37.25 1.545 37.235 1.215 37.235 1.215 37.565 ; + POLYGON 15.79 36.19 15.79 35.89 1.78 35.89 1.78 35.91 1.23 35.91 1.23 36.19 ; + POLYGON 13.03 30.75 13.03 30.45 1.78 30.45 1.78 30.47 1.23 30.47 1.23 30.75 ; + POLYGON 7.05 29.39 7.05 29.09 1.78 29.09 1.78 29.11 1.23 29.11 1.23 29.39 ; + POLYGON 7.05 23.95 7.05 23.65 1.99 23.65 1.99 22.97 1.78 22.97 1.78 23.67 1.69 23.67 1.69 23.95 ; + POLYGON 14.87 19.87 14.87 19.57 1.78 19.57 1.78 19.59 1.23 19.59 1.23 19.87 ; + POLYGON 66.85 17.15 66.85 16.87 66.3 16.87 66.3 16.85 47.69 16.85 47.69 17.15 ; + POLYGON 1.545 13.085 1.545 13.07 11.65 13.07 11.65 12.77 1.545 12.77 1.545 12.755 1.215 12.755 1.215 13.085 ; + POLYGON 5.67 11.71 5.67 11.41 1.99 11.41 1.99 10.73 1.78 10.73 1.78 11.43 1.69 11.43 1.69 11.71 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 86.64 67.68 83.51 66.3 83.51 66.3 82.41 67.68 82.41 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 77.39 66.3 77.39 66.3 76.29 67.68 76.29 67.68 76.03 66.3 76.03 66.3 74.93 67.68 74.93 67.68 74.67 66.3 74.67 66.3 73.57 67.68 73.57 67.68 73.31 66.3 73.31 66.3 72.21 67.68 72.21 67.68 71.95 66.3 71.95 66.3 70.85 67.68 70.85 67.68 69.91 66.3 69.91 66.3 68.81 67.68 68.81 67.68 68.55 66.3 68.55 66.3 67.45 67.68 67.45 67.68 67.19 66.3 67.19 66.3 66.09 67.68 66.09 67.68 65.83 66.3 65.83 66.3 64.73 67.68 64.73 67.68 64.47 66.3 64.47 66.3 63.37 67.68 63.37 67.68 63.11 66.3 63.11 66.3 62.01 67.68 62.01 67.68 61.75 66.3 61.75 66.3 60.65 67.68 60.65 67.68 60.39 66.3 60.39 66.3 59.29 67.68 59.29 67.68 59.03 66.3 59.03 66.3 57.93 67.68 57.93 67.68 57.67 66.3 57.67 66.3 56.57 67.68 56.57 67.68 56.31 66.3 56.31 66.3 55.21 67.68 55.21 67.68 54.95 66.3 54.95 66.3 53.85 67.68 53.85 67.68 53.59 66.3 53.59 66.3 52.49 67.68 52.49 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 50.87 66.3 50.87 66.3 49.77 67.68 49.77 67.68 48.83 66.3 48.83 66.3 47.73 67.68 47.73 67.68 46.79 66.3 46.79 66.3 45.69 67.68 45.69 67.68 45.43 66.3 45.43 66.3 44.33 67.68 44.33 67.68 44.07 66.3 44.07 66.3 42.97 67.68 42.97 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.83 66.3 31.83 66.3 30.73 67.68 30.73 67.68 30.47 66.3 30.47 66.3 29.37 67.68 29.37 67.68 29.11 66.3 29.11 66.3 28.01 67.68 28.01 67.68 27.07 66.3 27.07 66.3 25.97 67.68 25.97 67.68 25.71 66.3 25.71 66.3 24.61 67.68 24.61 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 22.99 66.3 22.99 66.3 21.89 67.68 21.89 67.68 20.95 66.3 20.95 66.3 19.85 67.68 19.85 67.68 19.59 66.3 19.59 66.3 18.49 67.68 18.49 67.68 18.23 66.3 18.23 66.3 17.13 67.68 17.13 67.68 16.87 66.3 16.87 66.3 15.77 67.68 15.77 67.68 14.15 66.3 14.15 66.3 13.05 67.68 13.05 67.68 12.11 66.3 12.11 66.3 11.01 67.68 11.01 67.68 10.75 66.3 10.75 66.3 9.65 67.68 9.65 67.68 9.39 66.3 9.39 66.3 8.29 67.68 8.29 67.68 8.03 66.3 8.03 66.3 6.93 67.68 6.93 67.68 6.67 66.3 6.67 66.3 5.57 67.68 5.57 67.68 0.4 0.4 0.4 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 ; + LAYER met2 ; + RECT 55.98 86.855 56.26 87.225 ; + RECT 26.54 86.855 26.82 87.225 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 9.09 0.28 9.09 1.64 8.39 1.64 8.39 0.28 4.49 0.28 4.49 1.64 3.79 1.64 3.79 0.28 0.28 0.28 0.28 86.76 1.95 86.76 1.95 85.4 2.65 85.4 2.65 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 33.69 86.76 33.69 85.4 34.39 85.4 34.39 86.76 34.61 86.76 34.61 85.4 35.31 85.4 35.31 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 ; LAYER met1 ; - POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; + LAYER met4 ; + POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; LAYER met5 ; - POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; + POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER li1 ; - RECT 0.17 0.17 77.11 65.11 ; + RECT 0.17 0.17 67.91 86.87 ; LAYER mcon ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 67.765 84.235 67.935 84.405 ; + RECT 67.305 84.235 67.475 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 67.765 81.515 67.935 81.685 ; + RECT 67.305 81.515 67.475 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 67.765 78.795 67.935 78.965 ; + RECT 67.305 78.795 67.475 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; RECT 67.765 65.195 67.935 65.365 ; RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 76.965 62.475 77.135 62.645 ; - RECT 76.505 62.475 76.675 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 76.965 59.755 77.135 59.925 ; - RECT 76.505 59.755 76.675 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 76.965 57.035 77.135 57.205 ; - RECT 76.505 57.035 76.675 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 76.965 54.315 77.135 54.485 ; - RECT 76.505 54.315 76.675 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 76.965 51.595 77.135 51.765 ; - RECT 76.505 51.595 76.675 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 76.965 48.875 77.135 49.045 ; - RECT 76.505 48.875 76.675 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 76.965 46.155 77.135 46.325 ; - RECT 76.505 46.155 76.675 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 76.965 43.435 77.135 43.605 ; - RECT 76.505 43.435 76.675 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 76.965 40.715 77.135 40.885 ; - RECT 76.505 40.715 76.675 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 76.965 37.995 77.135 38.165 ; - RECT 76.505 37.995 76.675 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 76.965 35.275 77.135 35.445 ; - RECT 76.505 35.275 76.675 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 76.965 32.555 77.135 32.725 ; - RECT 76.505 32.555 76.675 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 76.965 29.835 77.135 30.005 ; - RECT 76.505 29.835 76.675 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 76.965 27.115 77.135 27.285 ; - RECT 76.505 27.115 76.675 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 76.965 24.395 77.135 24.565 ; - RECT 76.505 24.395 76.675 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 76.965 21.675 77.135 21.845 ; - RECT 76.505 21.675 76.675 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 76.965 18.955 77.135 19.125 ; - RECT 76.505 18.955 76.675 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 76.965 13.515 77.135 13.685 ; - RECT 76.505 13.515 76.675 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 76.965 8.075 77.135 8.245 ; - RECT 76.505 8.075 76.675 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 76.965 5.355 77.135 5.525 ; - RECT 76.505 5.355 76.675 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 76.965 2.635 77.135 2.805 ; - RECT 76.505 2.635 76.675 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; RECT 67.765 -0.085 67.935 0.085 ; RECT 67.305 -0.085 67.475 0.085 ; RECT 66.845 -0.085 67.015 0.085 ; @@ -1988,50 +2026,35 @@ MACRO cbx_1__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 68.005 65.205 68.155 65.355 ; - RECT 38.565 65.205 38.715 65.355 ; - RECT 9.125 65.205 9.275 65.355 ; - RECT 70.305 63.505 70.455 63.655 ; - RECT 37.645 63.505 37.795 63.655 ; - RECT 71.225 1.625 71.375 1.775 ; - RECT 50.525 1.625 50.675 1.775 ; - RECT 28.445 1.625 28.595 1.775 ; - RECT 16.945 1.625 17.095 1.775 ; - RECT 2.225 1.625 2.375 1.775 ; - RECT 68.005 -0.075 68.155 0.075 ; - RECT 38.565 -0.075 38.715 0.075 ; - RECT 9.125 -0.075 9.275 0.075 ; + RECT 56.045 86.965 56.195 87.115 ; + RECT 26.605 86.965 26.755 87.115 ; + RECT 53.745 1.625 53.895 1.775 ; + RECT 19.245 1.625 19.395 1.775 ; + RECT 8.665 1.625 8.815 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 1.74 61.78 1.94 61.98 ; - RECT 75.8 59.74 76 59.94 ; - RECT 75.34 51.58 75.54 51.78 ; - RECT 75.8 47.5 76 47.7 ; - RECT 1.28 46.14 1.48 46.34 ; - RECT 75.8 41.38 76 41.58 ; - RECT 1.74 27.1 1.94 27.3 ; - RECT 75.8 23.02 76 23.22 ; - RECT 1.74 17.58 1.94 17.78 ; - RECT 1.28 13.5 1.48 13.7 ; - RECT 75.34 12.14 75.54 12.34 ; - RECT 1.74 12.14 1.94 12.34 ; - RECT 1.28 6.7 1.48 6.9 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 66.14 76.74 66.34 76.94 ; + RECT 1.28 75.38 1.48 75.58 ; + RECT 66.14 72.66 66.34 72.86 ; + RECT 1.28 66.54 1.48 66.74 ; + RECT 66.6 55.66 66.8 55.86 ; + RECT 66.6 33.9 66.8 34.1 ; + RECT 66.14 22.34 66.34 22.54 ; + RECT 1.28 21.66 1.48 21.86 ; + RECT 1.28 12.14 1.48 12.34 ; + RECT 1.28 9.42 1.48 9.62 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 75.34 58.38 75.54 58.58 ; - RECT 1.74 54.98 1.94 55.18 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; + POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; END END cbx_1__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef index e139580..231b996 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 77.28 BY 65.28 ; + SIZE 68.08 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 63.92 2.37 65.28 ; + RECT 54.67 0 54.81 1.36 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.13 1.38 48.43 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 53.57 1.38 53.87 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.93 1.38 55.23 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -475,7 +475,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.73 1.38 62.03 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -483,7 +483,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,7 +491,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.29 1.38 56.59 ; + RECT 0 31.81 1.38 32.11 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -499,7 +499,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -507,7 +507,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 49.49 1.38 49.79 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 29.09 77.28 29.39 ; + RECT 66.7 40.65 68.08 40.95 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 40.65 77.28 40.95 ; + RECT 66.7 59.69 68.08 59.99 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,7 +547,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.93 77.28 55.23 ; + RECT 66.7 71.93 68.08 72.23 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -555,7 +555,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 11.41 77.28 11.71 ; + RECT 66.7 56.29 68.08 56.59 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 32.49 77.28 32.79 ; + RECT 66.7 33.85 68.08 34.15 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,7 +571,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 30.45 77.28 30.75 ; + RECT 66.7 58.33 68.08 58.63 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -579,7 +579,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 22.29 77.28 22.59 ; + RECT 66.7 44.05 68.08 44.35 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 37.93 77.28 38.23 ; + RECT 66.7 29.77 68.08 30.07 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,7 +595,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 27.73 77.28 28.03 ; + RECT 66.7 32.49 68.08 32.79 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -603,7 +603,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 16.85 77.28 17.15 ; + RECT 66.7 46.77 68.08 47.07 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.85 77.28 51.15 ; + RECT 66.7 52.21 68.08 52.51 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 33.85 77.28 34.15 ; + RECT 66.7 54.93 68.08 55.23 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.05 77.28 10.35 ; + RECT 66.7 53.57 68.08 53.87 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 4.61 77.28 4.91 ; + RECT 66.7 62.41 68.08 62.71 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.69 77.28 8.99 ; + RECT 66.7 23.65 68.08 23.95 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 23.65 77.28 23.95 ; + RECT 66.7 66.49 68.08 66.79 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 43.37 77.28 43.67 ; + RECT 66.7 69.21 68.08 69.51 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.93 77.28 21.23 ; + RECT 66.7 28.41 68.08 28.71 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 15.49 77.28 15.79 ; + RECT 66.7 48.13 68.08 48.43 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.21 77.28 52.51 ; + RECT 66.7 67.85 68.08 68.15 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.77 77.28 47.07 ; + RECT 66.7 78.73 68.08 79.03 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -715,7 +715,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -723,7 +723,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -731,7 +731,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,7 +763,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -771,7 +771,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -779,7 +779,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 67.17 1.38 67.47 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,7 +803,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -811,7 +811,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 20.93 1.38 21.23 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -819,7 +819,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -851,7 +851,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -859,7 +859,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 35.21 77.28 35.51 ; + RECT 66.7 42.01 68.08 42.31 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 7.33 77.28 7.63 ; + RECT 66.7 61.05 68.08 61.35 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 26.37 77.28 26.67 ; + RECT 66.7 74.65 68.08 74.95 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.21 77.28 18.51 ; + RECT 66.7 25.69 68.08 25.99 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 19.57 77.28 19.87 ; + RECT 66.7 31.13 68.08 31.43 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.13 77.28 14.43 ; + RECT 66.7 36.57 68.08 36.87 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,7 +907,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 5.97 77.28 6.27 ; + RECT 66.7 80.09 68.08 80.39 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -915,7 +915,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 49.49 77.28 49.79 ; + RECT 66.7 49.49 68.08 49.79 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 53.57 77.28 53.87 ; + RECT 66.7 45.41 68.08 45.71 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.73 77.28 45.03 ; + RECT 66.7 73.29 68.08 73.59 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,7 +939,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 25.01 77.28 25.31 ; + RECT 66.7 77.37 68.08 77.67 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -947,7 +947,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.01 77.28 42.31 ; + RECT 66.7 76.01 68.08 76.31 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,7 +955,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 48.13 77.28 48.43 ; + RECT 66.7 35.21 68.08 35.51 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -963,7 +963,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 39.29 77.28 39.59 ; + RECT 66.7 37.93 68.08 38.23 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -971,7 +971,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 61.05 77.28 61.35 ; + RECT 66.7 50.85 68.08 51.15 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 36.57 77.28 36.87 ; + RECT 66.7 65.13 68.08 65.43 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 56.97 77.28 57.27 ; + RECT 66.7 70.57 68.08 70.87 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 58.33 77.28 58.63 ; + RECT 66.7 39.29 68.08 39.59 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 59.69 77.28 59.99 ; + RECT 66.7 63.77 68.08 64.07 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,7 +1011,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.77 77.28 13.07 ; + RECT 66.7 27.05 68.08 27.35 ; END END chanx_right_out[19] PIN bottom_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_1_[0] @@ -1027,7 +1027,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END bottom_grid_pin_1_[0] PIN bottom_grid_pin_2_[0] @@ -1035,7 +1035,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 0 4.67 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_3_[0] @@ -1043,7 +1043,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END bottom_grid_pin_3_[0] PIN bottom_grid_pin_4_[0] @@ -1051,7 +1051,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_5_[0] @@ -1059,7 +1059,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END bottom_grid_pin_5_[0] PIN bottom_grid_pin_6_[0] @@ -1075,7 +1075,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 22.47 0 22.61 1.36 ; END END bottom_grid_pin_7_[0] PIN bottom_grid_pin_8_[0] @@ -1083,7 +1083,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_9_[0] @@ -1091,7 +1091,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END bottom_grid_pin_9_[0] PIN bottom_grid_pin_10_[0] @@ -1099,7 +1099,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + RECT 24.31 0 24.45 1.36 ; END END bottom_grid_pin_10_[0] PIN bottom_grid_pin_11_[0] @@ -1107,7 +1107,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 23.39 0 23.53 1.36 ; END END bottom_grid_pin_11_[0] PIN bottom_grid_pin_12_[0] @@ -1115,7 +1115,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 16.95 0 17.09 1.36 ; END END bottom_grid_pin_12_[0] PIN bottom_grid_pin_13_[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END bottom_grid_pin_13_[0] PIN bottom_grid_pin_14_[0] @@ -1131,7 +1131,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; + RECT 5.45 0 5.59 1.36 ; END END bottom_grid_pin_14_[0] PIN bottom_grid_pin_15_[0] @@ -1139,7 +1139,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END bottom_grid_pin_15_[0] PIN ccff_tail[0] @@ -1147,31 +1147,15 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 76.01 1.38 76.31 ; END END ccff_tail[0] - PIN CLB_SC_IN - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 58.81 63.92 58.95 65.28 ; - END - END CLB_SC_IN - PIN CLB_SC_OUT - DIRECTION OUTPUT ; - USE SIGNAL ; - PORT - LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; - END - END CLB_SC_OUT PIN SC_IN_TOP DIRECTION INPUT ; USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 63.92 70.45 65.28 ; + RECT 53.75 85.68 53.89 87.04 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1179,7 +1163,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1187,7 +1171,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 63.92 21.69 65.28 ; + RECT 10.97 85.68 11.11 87.04 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1195,7 +1179,7 @@ MACRO cbx_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 21.55 0 21.69 1.36 ; END END SC_OUT_BOT PIN VDD @@ -1203,40 +1187,48 @@ MACRO cbx_1__1_ USE POWER ; PORT LAYER met4 ; - RECT 23.62 0 24.22 0.6 ; - RECT 53.06 0 53.66 0.6 ; - RECT 23.62 64.68 24.22 65.28 ; - RECT 53.06 64.68 53.66 65.28 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 86.44 12.26 87.04 ; + RECT 41.1 86.44 41.7 87.04 ; LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 74.08 10.64 77.28 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 74.08 51.44 77.28 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 64.88 11.32 68.08 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 64.88 52.12 68.08 55.32 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 76.8 2.48 77.28 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 76.8 7.92 77.28 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 76.8 13.36 77.28 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 76.8 18.8 77.28 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 76.8 24.24 77.28 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 76.8 29.68 77.28 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 76.8 35.12 77.28 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 76.8 40.56 77.28 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 76.8 46 77.28 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 76.8 51.44 77.28 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 76.8 56.88 77.28 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 76.8 62.32 77.28 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 67.6 78.64 68.08 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 67.6 84.08 68.08 84.56 ; END END VDD PIN VSS @@ -1244,403 +1236,427 @@ MACRO cbx_1__1_ USE GROUND ; PORT LAYER met4 ; - RECT 8.9 0 9.5 0.6 ; - RECT 38.34 0 38.94 0.6 ; - RECT 67.78 0 68.38 0.6 ; - RECT 8.9 64.68 9.5 65.28 ; - RECT 38.34 64.68 38.94 65.28 ; - RECT 67.78 64.68 68.38 65.28 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 86.44 26.98 87.04 ; + RECT 55.82 86.44 56.42 87.04 ; LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 74.08 31.04 77.28 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 64.88 31.72 68.08 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 64.88 72.52 68.08 75.72 ; LAYER met1 ; - RECT 0 0 77.28 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 76.8 5.2 77.28 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 76.8 10.64 77.28 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 76.8 16.08 77.28 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 76.8 21.52 77.28 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 76.8 26.96 77.28 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 76.8 32.4 77.28 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 76.8 37.84 77.28 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 76.8 43.28 77.28 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 76.8 48.72 77.28 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 76.8 54.16 77.28 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 76.8 59.6 77.28 60.08 ; - RECT 0 65.04 77.28 65.28 ; + RECT 67.6 59.6 68.08 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 67.6 75.92 68.08 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 67.6 81.36 68.08 81.84 ; + RECT 0 86.8 68.08 87.04 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 66.7 6.65 68.08 6.95 ; + END + END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 65.195 77.28 65.365 ; - RECT 76.36 62.475 77.28 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 76.36 57.035 77.28 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 76.36 54.315 77.28 54.485 ; + RECT 0 86.955 68.08 87.125 ; + RECT 67.16 84.235 68.08 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 67.16 81.515 68.08 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 67.16 78.795 68.08 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 67.16 76.075 68.08 76.245 ; + RECT 0 76.075 3.68 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 67.16 70.635 68.08 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 67.16 67.915 68.08 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 67.16 65.195 68.08 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 67.16 62.475 68.08 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 67.16 59.755 68.08 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 67.16 57.035 68.08 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 76.36 51.595 77.28 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 76.36 48.875 77.28 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 76.36 46.155 77.28 46.325 ; + RECT 67.16 46.155 68.08 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 76.36 43.435 77.28 43.605 ; + RECT 67.16 43.435 68.08 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 76.36 40.715 77.28 40.885 ; - RECT 0 40.715 1.84 40.885 ; - RECT 76.36 37.995 77.28 38.165 ; + RECT 67.16 40.715 68.08 40.885 ; + RECT 0 40.715 3.68 40.885 ; + RECT 67.16 37.995 68.08 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 76.36 35.275 77.28 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 76.36 32.555 77.28 32.725 ; + RECT 67.16 35.275 68.08 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 67.16 32.555 68.08 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 76.36 29.835 77.28 30.005 ; + RECT 67.16 29.835 68.08 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 76.36 27.115 77.28 27.285 ; + RECT 67.16 27.115 68.08 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 73.6 24.395 77.28 24.565 ; + RECT 67.16 24.395 68.08 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 73.6 21.675 77.28 21.845 ; + RECT 67.16 21.675 68.08 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 76.36 18.955 77.28 19.125 ; + RECT 67.16 18.955 68.08 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 76.36 16.235 77.28 16.405 ; + RECT 67.16 16.235 68.08 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 76.36 13.515 77.28 13.685 ; + RECT 67.16 13.515 68.08 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 76.36 10.795 77.28 10.965 ; + RECT 67.16 10.795 68.08 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 76.36 8.075 77.28 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 76.36 5.355 77.28 5.525 ; + RECT 67.16 5.355 68.08 5.525 ; RECT 0 5.355 1.84 5.525 ; - RECT 76.36 2.635 77.28 2.805 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 77.28 0.085 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 67.94 65.095 68.22 65.465 ; - RECT 38.5 65.095 38.78 65.465 ; - RECT 9.06 65.095 9.34 65.465 ; - RECT 20.11 1.54 20.37 1.86 ; - RECT 67.94 -0.185 68.22 0.185 ; - RECT 38.5 -0.185 38.78 0.185 ; - RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 21.27 65 21.27 63.64 21.97 63.64 21.97 65 58.53 65 58.53 63.64 59.23 63.64 59.23 65 70.03 65 70.03 63.64 70.73 63.64 70.73 65 ; + RECT 55.98 86.855 56.26 87.225 ; + RECT 26.54 86.855 26.82 87.225 ; + RECT 9.53 1.54 9.79 1.86 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 55.09 0.28 55.09 1.64 54.39 1.64 54.39 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 0.28 0.28 0.28 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 ; LAYER met3 ; - POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; - POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; - POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - POLYGON 76.065 53.205 76.065 52.875 75.735 52.875 75.735 52.89 44.93 52.89 44.93 53.19 75.735 53.19 75.735 53.205 ; - POLYGON 75.59 44.35 75.59 44.07 75.5 44.07 75.5 43.355 75.275 43.355 75.275 43.685 75.29 43.685 75.29 44.05 61.49 44.05 61.49 44.35 ; - POLYGON 31.43 41.63 31.43 41.33 1.23 41.33 1.23 41.61 1.78 41.61 1.78 41.63 ; - POLYGON 75.63 40.28 75.63 39.96 75.25 39.96 75.25 39.97 62.87 39.97 62.87 40.27 75.25 40.27 75.25 40.28 ; - POLYGON 17.63 38.91 17.63 38.61 1.78 38.61 1.78 38.63 1.23 38.63 1.23 38.91 ; - POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; - POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; - POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 55.63 75.5 55.63 75.5 54.53 76.88 54.53 76.88 54.27 75.5 54.27 75.5 53.17 76.88 53.17 76.88 52.91 75.5 52.91 75.5 51.81 76.88 51.81 76.88 51.55 75.5 51.55 75.5 50.45 76.88 50.45 76.88 50.19 75.5 50.19 75.5 49.09 76.88 49.09 76.88 48.83 75.5 48.83 75.5 47.73 76.88 47.73 76.88 47.47 75.5 47.47 75.5 46.37 76.88 46.37 76.88 45.43 75.5 45.43 75.5 44.33 76.88 44.33 76.88 44.07 75.5 44.07 75.5 42.97 76.88 42.97 76.88 42.71 75.5 42.71 75.5 41.61 76.88 41.61 76.88 41.35 75.5 41.35 75.5 40.25 76.88 40.25 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 38.63 75.5 38.63 75.5 37.53 76.88 37.53 76.88 37.27 75.5 37.27 75.5 36.17 76.88 36.17 76.88 35.91 75.5 35.91 75.5 34.81 76.88 34.81 76.88 34.55 75.5 34.55 75.5 33.45 76.88 33.45 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.15 75.5 31.15 75.5 30.05 76.88 30.05 76.88 29.79 75.5 29.79 75.5 28.69 76.88 28.69 76.88 28.43 75.5 28.43 75.5 27.33 76.88 27.33 76.88 27.07 75.5 27.07 75.5 25.97 76.88 25.97 76.88 25.71 75.5 25.71 75.5 24.61 76.88 24.61 76.88 24.35 75.5 24.35 75.5 23.25 76.88 23.25 76.88 22.99 75.5 22.99 75.5 21.89 76.88 21.89 76.88 21.63 75.5 21.63 75.5 20.53 76.88 20.53 76.88 20.27 75.5 20.27 75.5 19.17 76.88 19.17 76.88 18.91 75.5 18.91 75.5 17.81 76.88 17.81 76.88 17.55 75.5 17.55 75.5 16.45 76.88 16.45 76.88 16.19 75.5 16.19 75.5 15.09 76.88 15.09 76.88 14.83 75.5 14.83 75.5 13.73 76.88 13.73 76.88 13.47 75.5 13.47 75.5 12.37 76.88 12.37 76.88 12.11 75.5 12.11 75.5 11.01 76.88 11.01 76.88 10.75 75.5 10.75 75.5 9.65 76.88 9.65 76.88 9.39 75.5 9.39 75.5 8.29 76.88 8.29 76.88 8.03 75.5 8.03 75.5 6.93 76.88 6.93 76.88 6.67 75.5 6.67 75.5 5.57 76.88 5.57 76.88 5.31 75.5 5.31 75.5 4.21 76.88 4.21 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.09 1.78 49.09 1.78 50.19 0.4 50.19 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 64.88 ; + POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; + POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; + POLYGON 2.03 77 2.03 76.99 53.51 76.99 53.51 76.69 2.03 76.69 2.03 76.68 1.65 76.68 1.65 77 ; + POLYGON 6.13 75.63 6.13 75.33 1.53 75.33 1.53 74.67 1.23 74.67 1.23 75.63 ; + POLYGON 66.3 72.91 66.3 72.89 67.77 72.89 67.77 72.61 65.63 72.61 65.63 72.91 ; + POLYGON 2.03 64.08 2.03 64.07 8.43 64.07 8.43 63.77 2.03 63.77 2.03 63.76 1.65 63.76 1.65 64.08 ; + POLYGON 1.99 63.39 1.99 62.71 5.67 62.71 5.67 62.41 1.69 62.41 1.69 62.69 1.78 62.69 1.78 63.39 ; + POLYGON 6.59 61.35 6.59 61.05 1.23 61.05 1.23 61.33 1.78 61.33 1.78 61.35 ; + POLYGON 2.005 57.965 2.005 57.96 2.03 57.96 2.03 57.64 2.005 57.64 2.005 57.635 1.275 57.635 1.275 57.965 ; + POLYGON 1.99 45.03 1.99 44.365 2.005 44.365 2.005 44.035 1.675 44.035 1.675 44.33 1.78 44.33 1.78 45.03 ; + POLYGON 66.43 34.84 66.43 34.52 66.05 34.52 66.05 34.53 43.09 34.53 43.09 34.83 66.05 34.83 66.05 34.84 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 86.64 67.68 80.79 66.3 80.79 66.3 79.69 67.68 79.69 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 78.07 66.3 78.07 66.3 76.97 67.68 76.97 67.68 76.71 66.3 76.71 66.3 75.61 67.68 75.61 67.68 75.35 66.3 75.35 66.3 74.25 67.68 74.25 67.68 73.99 66.3 73.99 66.3 72.89 67.68 72.89 67.68 72.63 66.3 72.63 66.3 71.53 67.68 71.53 67.68 71.27 66.3 71.27 66.3 70.17 67.68 70.17 67.68 69.91 66.3 69.91 66.3 68.81 67.68 68.81 67.68 68.55 66.3 68.55 66.3 67.45 67.68 67.45 67.68 67.19 66.3 67.19 66.3 66.09 67.68 66.09 67.68 65.83 66.3 65.83 66.3 64.73 67.68 64.73 67.68 64.47 66.3 64.47 66.3 63.37 67.68 63.37 67.68 63.11 66.3 63.11 66.3 62.01 67.68 62.01 67.68 61.75 66.3 61.75 66.3 60.65 67.68 60.65 67.68 60.39 66.3 60.39 66.3 59.29 67.68 59.29 67.68 59.03 66.3 59.03 66.3 57.93 67.68 57.93 67.68 56.99 66.3 56.99 66.3 55.89 67.68 55.89 67.68 55.63 66.3 55.63 66.3 54.53 67.68 54.53 67.68 54.27 66.3 54.27 66.3 53.17 67.68 53.17 67.68 52.91 66.3 52.91 66.3 51.81 67.68 51.81 67.68 51.55 66.3 51.55 66.3 50.45 67.68 50.45 67.68 50.19 66.3 50.19 66.3 49.09 67.68 49.09 67.68 48.83 66.3 48.83 66.3 47.73 67.68 47.73 67.68 47.47 66.3 47.47 66.3 46.37 67.68 46.37 67.68 46.11 66.3 46.11 66.3 45.01 67.68 45.01 67.68 44.75 66.3 44.75 66.3 43.65 67.68 43.65 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.83 66.3 31.83 66.3 30.73 67.68 30.73 67.68 30.47 66.3 30.47 66.3 29.37 67.68 29.37 67.68 29.11 66.3 29.11 66.3 28.01 67.68 28.01 67.68 27.75 66.3 27.75 66.3 26.65 67.68 26.65 67.68 26.39 66.3 26.39 66.3 25.29 67.68 25.29 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 7.35 66.3 7.35 66.3 6.25 67.68 6.25 67.68 0.4 0.4 0.4 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 86.64 ; LAYER met1 ; - POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER met5 ; - POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; + POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; LAYER met4 ; - POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; + POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; LAYER li1 ; - RECT 0.17 0.17 77.11 65.11 ; + RECT 0.17 0.17 67.91 86.87 ; LAYER mcon ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 67.765 84.235 67.935 84.405 ; + RECT 67.305 84.235 67.475 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 67.765 81.515 67.935 81.685 ; + RECT 67.305 81.515 67.475 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 67.765 78.795 67.935 78.965 ; + RECT 67.305 78.795 67.475 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; RECT 67.765 65.195 67.935 65.365 ; RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 76.965 62.475 77.135 62.645 ; - RECT 76.505 62.475 76.675 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 76.965 59.755 77.135 59.925 ; - RECT 76.505 59.755 76.675 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 76.965 57.035 77.135 57.205 ; - RECT 76.505 57.035 76.675 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 76.965 54.315 77.135 54.485 ; - RECT 76.505 54.315 76.675 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 76.965 51.595 77.135 51.765 ; - RECT 76.505 51.595 76.675 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 76.965 48.875 77.135 49.045 ; - RECT 76.505 48.875 76.675 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 76.965 46.155 77.135 46.325 ; - RECT 76.505 46.155 76.675 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 76.965 43.435 77.135 43.605 ; - RECT 76.505 43.435 76.675 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 76.965 40.715 77.135 40.885 ; - RECT 76.505 40.715 76.675 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 76.965 37.995 77.135 38.165 ; - RECT 76.505 37.995 76.675 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 76.965 35.275 77.135 35.445 ; - RECT 76.505 35.275 76.675 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 76.965 32.555 77.135 32.725 ; - RECT 76.505 32.555 76.675 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 76.965 29.835 77.135 30.005 ; - RECT 76.505 29.835 76.675 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 76.965 27.115 77.135 27.285 ; - RECT 76.505 27.115 76.675 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 76.965 24.395 77.135 24.565 ; - RECT 76.505 24.395 76.675 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 76.965 21.675 77.135 21.845 ; - RECT 76.505 21.675 76.675 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 76.965 18.955 77.135 19.125 ; - RECT 76.505 18.955 76.675 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 76.965 13.515 77.135 13.685 ; - RECT 76.505 13.515 76.675 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 76.965 8.075 77.135 8.245 ; - RECT 76.505 8.075 76.675 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 76.965 5.355 77.135 5.525 ; - RECT 76.505 5.355 76.675 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 76.965 2.635 77.135 2.805 ; - RECT 76.505 2.635 76.675 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; RECT 67.765 -0.085 67.935 0.085 ; RECT 67.305 -0.085 67.475 0.085 ; RECT 66.845 -0.085 67.015 0.085 ; @@ -1790,43 +1806,39 @@ MACRO cbx_1__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 68.005 65.205 68.155 65.355 ; - RECT 38.565 65.205 38.715 65.355 ; - RECT 9.125 65.205 9.275 65.355 ; - RECT 23.385 1.625 23.535 1.775 ; - RECT 22.465 1.625 22.615 1.775 ; - RECT 68.005 -0.075 68.155 0.075 ; - RECT 38.565 -0.075 38.715 0.075 ; - RECT 9.125 -0.075 9.275 0.075 ; + RECT 56.045 86.965 56.195 87.115 ; + RECT 26.605 86.965 26.755 87.115 ; + RECT 33.045 1.625 33.195 1.775 ; + RECT 11.885 1.625 12.035 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 1.74 57.7 1.94 57.9 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 1.28 76.06 1.48 76.26 ; + RECT 1.74 69.94 1.94 70.14 ; + RECT 66.6 69.26 66.8 69.46 ; + RECT 1.28 67.22 1.48 67.42 ; + RECT 66.6 65.18 66.8 65.38 ; RECT 1.74 53.62 1.94 53.82 ; - RECT 75.34 43.42 75.54 43.62 ; - RECT 75.8 39.34 76 39.54 ; - RECT 1.28 39.34 1.48 39.54 ; - RECT 75.34 36.62 75.54 36.82 ; - RECT 75.8 33.9 76 34.1 ; - RECT 1.74 23.7 1.94 23.9 ; - RECT 75.34 14.18 75.54 14.38 ; - RECT 1.74 6.7 1.94 6.9 ; - RECT 75.8 6.02 76 6.22 ; - RECT 1.28 3.98 1.48 4.18 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 66.14 52.26 66.34 52.46 ; + RECT 1.74 33.22 1.94 33.42 ; + RECT 1.74 29.14 1.94 29.34 ; + RECT 1.28 26.42 1.48 26.62 ; + RECT 66.6 25.74 66.8 25.94 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 75.34 10.1 75.54 10.3 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 1.74 71.3 1.94 71.5 ; + RECT 1.74 68.58 1.94 68.78 ; + RECT 1.74 31.86 1.94 32.06 ; + RECT 66.14 28.46 66.34 28.66 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; + POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; END END cbx_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef index 2527f95..cf227be 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cbx_1__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cbx_1__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 77.28 BY 65.28 ; + SIZE 68.08 BY 87.04 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + RECT 54.67 0 54.81 1.36 ; END END prog_clk[0] PIN chanx_left_in[0] @@ -371,7 +371,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 20.93 1.38 21.23 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -379,7 +379,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.77 1.38 13.07 ; + RECT 0 22.29 1.38 22.59 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -387,7 +387,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 18.21 1.38 18.51 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -395,7 +395,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 15.49 1.38 15.79 ; + RECT 0 19.57 1.38 19.87 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -403,7 +403,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -411,7 +411,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 8.69 1.38 8.99 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -419,7 +419,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -427,7 +427,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 16.85 1.38 17.15 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -435,7 +435,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.21 1.38 18.51 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -443,7 +443,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 13.45 1.38 13.75 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -451,7 +451,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -459,7 +459,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.13 1.38 14.43 ; + RECT 0 12.09 1.38 12.39 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -467,7 +467,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 45.41 1.38 45.71 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -475,7 +475,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; + RECT 0 15.49 1.38 15.79 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -483,7 +483,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -491,7 +491,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -499,7 +499,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -507,7 +507,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -515,7 +515,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -523,7 +523,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 10.73 1.38 11.03 ; END END chanx_left_in[19] PIN chanx_right_in[0] @@ -531,7 +531,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 41.33 77.28 41.63 ; + RECT 66.7 60.37 68.08 60.67 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -539,7 +539,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 50.17 77.28 50.47 ; + RECT 66.7 78.73 68.08 79.03 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -547,7 +547,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 39.29 77.28 39.59 ; + RECT 66.7 57.65 68.08 57.95 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -555,7 +555,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 31.13 77.28 31.43 ; + RECT 66.7 40.65 68.08 40.95 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -563,7 +563,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 34.53 77.28 34.83 ; + RECT 66.7 64.45 68.08 64.75 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -571,7 +571,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 12.09 77.28 12.39 ; + RECT 66.7 35.21 68.08 35.51 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -579,7 +579,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 27.05 77.28 27.35 ; + RECT 66.7 43.37 68.08 43.67 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -587,7 +587,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 14.81 77.28 15.11 ; + RECT 66.7 39.29 68.08 39.59 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -595,15 +595,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 56.97 77.28 57.27 ; + RECT 66.7 63.09 68.08 63.39 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 74.91 0 75.05 1.36 ; + LAYER met3 ; + RECT 66.7 26.37 68.08 26.67 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -611,7 +611,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 58.33 77.28 58.63 ; + RECT 66.7 61.73 68.08 62.03 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -619,7 +619,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 18.89 77.28 19.19 ; + RECT 66.7 19.57 68.08 19.87 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -627,7 +627,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 55.61 77.28 55.91 ; + RECT 66.7 59.01 68.08 59.31 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -635,7 +635,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 37.25 77.28 37.55 ; + RECT 66.7 37.93 68.08 38.23 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -643,7 +643,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 25.69 77.28 25.99 ; + RECT 66.7 42.01 68.08 42.31 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -651,7 +651,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 32.49 77.28 32.79 ; + RECT 66.7 51.53 68.08 51.83 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -659,7 +659,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 17.53 77.28 17.83 ; + RECT 66.7 32.49 68.08 32.79 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -667,7 +667,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 16.17 77.28 16.47 ; + RECT 66.7 15.49 68.08 15.79 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -675,7 +675,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 28.41 77.28 28.71 ; + RECT 66.7 48.81 68.08 49.11 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -683,7 +683,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 22.97 77.28 23.27 ; + RECT 66.7 16.85 68.08 17.15 ; END END chanx_right_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 5.29 77.28 5.59 ; + RECT 66.7 20.93 68.08 21.23 ; END END ccff_head[0] PIN chanx_left_out[0] @@ -699,7 +699,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -707,7 +707,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -715,7 +715,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -723,7 +723,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.05 1.38 10.35 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -731,7 +731,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -739,7 +739,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 6.65 1.38 6.95 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -747,7 +747,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.85 1.38 17.15 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -755,7 +755,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -763,7 +763,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -771,15 +771,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_out[9] PIN chanx_left_out[10] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 0 3.75 1.36 ; + LAYER met3 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -787,7 +787,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -795,7 +795,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 46.77 1.38 47.07 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -803,15 +803,15 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_out[13] PIN chanx_left_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 0 4.75 1.36 ; + LAYER met3 ; + RECT 0 44.05 1.38 44.35 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -819,7 +819,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -827,7 +827,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -835,7 +835,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -843,7 +843,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -851,7 +851,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[19] PIN chanx_right_out[0] @@ -859,7 +859,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 10.73 77.28 11.03 ; + RECT 66.7 33.85 68.08 34.15 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -867,7 +867,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 51.53 77.28 51.83 ; + RECT 66.7 50.17 68.08 50.47 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -875,7 +875,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 54.25 77.28 54.55 ; + RECT 66.7 29.09 68.08 29.39 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -883,7 +883,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 52.89 77.28 53.19 ; + RECT 66.7 12.77 68.08 13.07 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -891,7 +891,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 21.61 77.28 21.91 ; + RECT 66.7 18.21 68.08 18.51 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -899,7 +899,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 6.65 77.28 6.95 ; + RECT 66.7 14.13 68.08 14.43 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -907,7 +907,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 48.81 77.28 49.11 ; + RECT 66.7 30.45 68.08 30.75 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -915,7 +915,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 9.37 77.28 9.67 ; + RECT 66.7 25.01 68.08 25.31 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -923,7 +923,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 29.77 77.28 30.07 ; + RECT 66.7 22.29 68.08 22.59 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -931,7 +931,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 44.05 77.28 44.35 ; + RECT 66.7 54.25 68.08 54.55 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -939,7 +939,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 47.45 77.28 47.75 ; + RECT 66.7 36.57 68.08 36.87 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -947,7 +947,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 20.25 77.28 20.55 ; + RECT 66.7 9.37 68.08 9.67 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -955,7 +955,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 13.45 77.28 13.75 ; + RECT 66.7 6.65 68.08 6.95 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -963,7 +963,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 3.93 77.28 4.23 ; + RECT 66.7 11.41 68.08 11.71 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -971,7 +971,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 61.05 77.28 61.35 ; + RECT 66.7 8.01 68.08 8.31 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -979,7 +979,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 59.69 77.28 59.99 ; + RECT 66.7 23.65 68.08 23.95 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -987,7 +987,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 42.69 77.28 42.99 ; + RECT 66.7 47.45 68.08 47.75 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -995,7 +995,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 35.89 77.28 36.19 ; + RECT 66.7 52.89 68.08 53.19 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1003,7 +1003,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 24.33 77.28 24.63 ; + RECT 66.7 46.09 68.08 46.39 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1011,7 +1011,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 8.01 77.28 8.31 ; + RECT 66.7 27.73 68.08 28.03 ; END END chanx_right_out[19] PIN top_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 46.85 85.68 46.99 87.04 ; END END top_grid_pin_0_[0] PIN bottom_grid_pin_0_[0] @@ -1027,7 +1027,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END bottom_grid_pin_0_[0] PIN bottom_grid_pin_1_[0] @@ -1035,7 +1035,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.71 0 19.85 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END bottom_grid_pin_1_[0] PIN bottom_grid_pin_2_[0] @@ -1043,7 +1043,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 0 4.67 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END bottom_grid_pin_2_[0] PIN bottom_grid_pin_3_[0] @@ -1051,7 +1051,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END bottom_grid_pin_3_[0] PIN bottom_grid_pin_4_[0] @@ -1059,7 +1059,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END bottom_grid_pin_4_[0] PIN bottom_grid_pin_5_[0] @@ -1067,7 +1067,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END bottom_grid_pin_5_[0] PIN bottom_grid_pin_6_[0] @@ -1083,7 +1083,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 0 24.45 1.36 ; + RECT 22.47 0 22.61 1.36 ; END END bottom_grid_pin_7_[0] PIN bottom_grid_pin_8_[0] @@ -1091,7 +1091,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END bottom_grid_pin_8_[0] PIN bottom_grid_pin_9_[0] @@ -1099,7 +1099,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 33.05 0 33.19 1.36 ; END END bottom_grid_pin_9_[0] PIN bottom_grid_pin_10_[0] @@ -1107,7 +1107,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + RECT 24.31 0 24.45 1.36 ; END END bottom_grid_pin_10_[0] PIN bottom_grid_pin_11_[0] @@ -1115,7 +1115,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 0 58.95 1.36 ; + RECT 23.39 0 23.53 1.36 ; END END bottom_grid_pin_11_[0] PIN bottom_grid_pin_12_[0] @@ -1123,7 +1123,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 0 23.53 1.36 ; + RECT 16.95 0 17.09 1.36 ; END END bottom_grid_pin_12_[0] PIN bottom_grid_pin_13_[0] @@ -1131,7 +1131,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 17.87 0 18.01 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END bottom_grid_pin_13_[0] PIN bottom_grid_pin_14_[0] @@ -1139,7 +1139,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.79 0 18.93 1.36 ; + RECT 5.45 0 5.59 1.36 ; END END bottom_grid_pin_14_[0] PIN bottom_grid_pin_15_[0] @@ -1147,7 +1147,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END bottom_grid_pin_15_[0] PIN ccff_tail[0] @@ -1155,7 +1155,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 31.81 1.38 32.11 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1163,7 +1163,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 73.07 63.92 73.21 65.28 ; + RECT 53.75 85.68 53.89 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1171,7 +1171,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.09 63.92 67.23 65.28 ; + RECT 59.27 85.68 59.41 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1179,7 +1179,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.83 63.92 6.97 65.28 ; + RECT 6.83 85.68 6.97 87.04 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN bottom_width_0_height_0__pin_0_[0] @@ -1187,7 +1187,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 45.93 85.68 46.07 87.04 ; END END bottom_width_0_height_0__pin_0_[0] PIN bottom_width_0_height_0__pin_1_upper[0] @@ -1195,7 +1195,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + RECT 0 26.37 1.38 26.67 ; END END bottom_width_0_height_0__pin_1_upper[0] PIN bottom_width_0_height_0__pin_1_lower[0] @@ -1203,7 +1203,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 75.9 46.09 77.28 46.39 ; + RECT 66.7 44.73 68.08 45.03 ; END END bottom_width_0_height_0__pin_1_lower[0] PIN SC_IN_TOP @@ -1211,7 +1211,7 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 67.85 1.38 68.15 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1219,23 +1219,23 @@ MACRO cbx_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END SC_IN_BOT PIN SC_OUT_TOP DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 37.65 63.92 37.79 65.28 ; + LAYER met3 ; + RECT 0 74.65 1.38 74.95 ; END END SC_OUT_TOP PIN SC_OUT_BOT DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + LAYER met3 ; + RECT 66.7 3.25 68.08 3.55 ; END END SC_OUT_BOT PIN VDD @@ -1243,40 +1243,48 @@ MACRO cbx_1__2_ USE POWER ; PORT LAYER met4 ; - RECT 23.62 0 24.22 0.6 ; - RECT 53.06 0 53.66 0.6 ; - RECT 23.62 64.68 24.22 65.28 ; - RECT 53.06 64.68 53.66 65.28 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 86.44 12.26 87.04 ; + RECT 41.1 86.44 41.7 87.04 ; LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 74.08 10.64 77.28 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 74.08 51.44 77.28 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 64.88 11.32 68.08 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 64.88 52.12 68.08 55.32 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 76.8 2.48 77.28 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 76.8 7.92 77.28 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 76.8 13.36 77.28 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 76.8 18.8 77.28 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 76.8 24.24 77.28 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 76.8 29.68 77.28 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 76.8 35.12 77.28 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 76.8 40.56 77.28 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 76.8 46 77.28 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 76.8 51.44 77.28 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 76.8 56.88 77.28 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 76.8 62.32 77.28 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 67.6 78.64 68.08 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 67.6 84.08 68.08 84.56 ; END END VDD PIN VSS @@ -1284,405 +1292,415 @@ MACRO cbx_1__2_ USE GROUND ; PORT LAYER met4 ; - RECT 8.9 0 9.5 0.6 ; - RECT 38.34 0 38.94 0.6 ; - RECT 67.78 0 68.38 0.6 ; - RECT 8.9 64.68 9.5 65.28 ; - RECT 38.34 64.68 38.94 65.28 ; - RECT 67.78 64.68 68.38 65.28 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 86.44 26.98 87.04 ; + RECT 55.82 86.44 56.42 87.04 ; LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 74.08 31.04 77.28 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 64.88 31.72 68.08 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 64.88 72.52 68.08 75.72 ; LAYER met1 ; - RECT 0 0 77.28 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 76.8 5.2 77.28 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 76.8 10.64 77.28 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 76.8 16.08 77.28 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 76.8 21.52 77.28 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 76.8 26.96 77.28 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 76.8 32.4 77.28 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 76.8 37.84 77.28 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 76.8 43.28 77.28 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 76.8 48.72 77.28 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 76.8 54.16 77.28 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 76.8 59.6 77.28 60.08 ; - RECT 0 65.04 77.28 65.28 ; + RECT 67.6 59.6 68.08 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 67.6 75.92 68.08 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 67.6 81.36 68.08 81.84 ; + RECT 0 86.8 68.08 87.04 ; END END VSS OBS LAYER li1 ; - RECT 0 65.195 77.28 65.365 ; - RECT 76.36 62.475 77.28 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 76.36 59.755 77.28 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 76.36 57.035 77.28 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 76.36 54.315 77.28 54.485 ; + RECT 0 86.955 68.08 87.125 ; + RECT 67.16 84.235 68.08 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 67.16 81.515 68.08 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 67.62 78.795 68.08 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 67.16 76.075 68.08 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 64.4 70.635 68.08 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 64.4 67.915 68.08 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 67.16 65.195 68.08 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 67.16 62.475 68.08 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 67.16 59.755 68.08 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 67.16 57.035 68.08 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 76.36 51.595 77.28 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 76.36 48.875 77.28 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 76.36 46.155 77.28 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 76.36 43.435 77.28 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 76.36 40.715 77.28 40.885 ; + RECT 67.16 46.155 68.08 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 67.16 43.435 68.08 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 66.24 40.715 68.08 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 76.36 37.995 77.28 38.165 ; + RECT 66.24 37.995 68.08 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 73.6 35.275 77.28 35.445 ; + RECT 67.16 35.275 68.08 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 73.6 32.555 77.28 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 76.36 29.835 77.28 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 76.36 27.115 77.28 27.285 ; + RECT 67.16 32.555 68.08 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 67.16 29.835 68.08 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 67.16 27.115 68.08 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 76.36 24.395 77.28 24.565 ; + RECT 67.16 24.395 68.08 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 76.36 21.675 77.28 21.845 ; + RECT 67.16 21.675 68.08 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 76.36 18.955 77.28 19.125 ; - RECT 0 18.955 1.84 19.125 ; - RECT 76.36 16.235 77.28 16.405 ; - RECT 0 16.235 1.84 16.405 ; - RECT 76.36 13.515 77.28 13.685 ; + RECT 67.16 18.955 68.08 19.125 ; + RECT 0 18.955 3.68 19.125 ; + RECT 67.16 16.235 68.08 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 67.16 13.515 68.08 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 76.36 10.795 77.28 10.965 ; - RECT 0 10.795 3.68 10.965 ; - RECT 76.36 8.075 77.28 8.245 ; - RECT 0 8.075 3.68 8.245 ; - RECT 76.36 5.355 77.28 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 76.36 2.635 77.28 2.805 ; + RECT 67.16 10.795 68.08 10.965 ; + RECT 0 10.795 1.84 10.965 ; + RECT 67.16 8.075 68.08 8.245 ; + RECT 0 8.075 1.84 8.245 ; + RECT 67.16 5.355 68.08 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 77.28 0.085 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 67.94 65.095 68.22 65.465 ; - RECT 38.5 65.095 38.78 65.465 ; - RECT 9.06 65.095 9.34 65.465 ; - RECT 41.73 1.54 41.99 1.86 ; - RECT 67.94 -0.185 68.22 0.185 ; - RECT 38.5 -0.185 38.78 0.185 ; - RECT 9.06 -0.185 9.34 0.185 ; - POLYGON 77 65 77 0.28 75.33 0.28 75.33 1.64 74.63 1.64 74.63 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 4.03 0.28 4.03 1.64 3.33 1.64 3.33 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 6.55 65 6.55 63.64 7.25 63.64 7.25 65 37.37 65 37.37 63.64 38.07 63.64 38.07 65 66.81 65 66.81 63.64 67.51 63.64 67.51 65 72.79 65 72.79 63.64 73.49 63.64 73.49 65 ; + RECT 55.98 86.855 56.26 87.225 ; + RECT 26.54 86.855 26.82 87.225 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 86.76 67.8 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 55.09 0.28 55.09 1.64 54.39 1.64 54.39 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 0.28 0.28 0.28 86.76 6.55 86.76 6.55 85.4 7.25 85.4 7.25 86.76 45.65 86.76 45.65 85.4 46.35 85.4 46.35 86.76 46.57 86.76 46.57 85.4 47.27 85.4 47.27 86.76 53.47 86.76 53.47 85.4 54.17 85.4 54.17 86.76 58.99 86.76 58.99 85.4 59.69 85.4 59.69 86.76 ; LAYER met3 ; - POLYGON 68.245 65.445 68.245 65.44 68.46 65.44 68.46 65.12 68.245 65.12 68.245 65.115 67.915 65.115 67.915 65.12 67.7 65.12 67.7 65.44 67.915 65.44 67.915 65.445 ; - POLYGON 38.805 65.445 38.805 65.44 39.02 65.44 39.02 65.12 38.805 65.12 38.805 65.115 38.475 65.115 38.475 65.12 38.26 65.12 38.26 65.44 38.475 65.44 38.475 65.445 ; - POLYGON 9.365 65.445 9.365 65.44 9.58 65.44 9.58 65.12 9.365 65.12 9.365 65.115 9.035 65.115 9.035 65.12 8.82 65.12 8.82 65.44 9.035 65.44 9.035 65.445 ; - POLYGON 21.31 57.95 21.31 57.65 1.23 57.65 1.23 57.93 1.78 57.93 1.78 57.95 ; - POLYGON 2.03 44.36 2.03 44.35 6.13 44.35 6.13 44.05 2.03 44.05 2.03 44.04 1.65 44.04 1.65 44.36 ; - POLYGON 75.63 29.4 75.63 29.08 75.25 29.08 75.25 29.09 71.61 29.09 71.61 29.39 75.25 29.39 75.25 29.4 ; - POLYGON 76.05 28.03 76.05 27.75 75.5 27.75 75.5 27.73 58.73 27.73 58.73 28.03 ; - POLYGON 2.03 12.4 2.03 12.39 31.89 12.39 31.89 12.09 2.03 12.09 2.03 12.08 1.65 12.08 1.65 12.4 ; - POLYGON 76.05 6.27 76.05 5.99 75.5 5.99 75.5 5.97 64.25 5.97 64.25 6.27 ; - POLYGON 9.81 4.91 9.81 4.61 1.99 4.61 1.99 3.93 1.78 3.93 1.78 4.63 1.69 4.63 1.69 4.91 ; - POLYGON 68.245 0.165 68.245 0.16 68.46 0.16 68.46 -0.16 68.245 -0.16 68.245 -0.165 67.915 -0.165 67.915 -0.16 67.7 -0.16 67.7 0.16 67.915 0.16 67.915 0.165 ; - POLYGON 38.805 0.165 38.805 0.16 39.02 0.16 39.02 -0.16 38.805 -0.16 38.805 -0.165 38.475 -0.165 38.475 -0.16 38.26 -0.16 38.26 0.16 38.475 0.16 38.475 0.165 ; - POLYGON 9.365 0.165 9.365 0.16 9.58 0.16 9.58 -0.16 9.365 -0.16 9.365 -0.165 9.035 -0.165 9.035 -0.16 8.82 -0.16 8.82 0.16 9.035 0.16 9.035 0.165 ; - POLYGON 76.88 64.88 76.88 61.75 75.5 61.75 75.5 60.65 76.88 60.65 76.88 60.39 75.5 60.39 75.5 59.29 76.88 59.29 76.88 59.03 75.5 59.03 75.5 57.93 76.88 57.93 76.88 57.67 75.5 57.67 75.5 56.57 76.88 56.57 76.88 56.31 75.5 56.31 75.5 55.21 76.88 55.21 76.88 54.95 75.5 54.95 75.5 53.85 76.88 53.85 76.88 53.59 75.5 53.59 75.5 52.49 76.88 52.49 76.88 52.23 75.5 52.23 75.5 51.13 76.88 51.13 76.88 50.87 75.5 50.87 75.5 49.77 76.88 49.77 76.88 49.51 75.5 49.51 75.5 48.41 76.88 48.41 76.88 48.15 75.5 48.15 75.5 47.05 76.88 47.05 76.88 46.79 75.5 46.79 75.5 45.69 76.88 45.69 76.88 44.75 75.5 44.75 75.5 43.65 76.88 43.65 76.88 43.39 75.5 43.39 75.5 42.29 76.88 42.29 76.88 42.03 75.5 42.03 75.5 40.93 76.88 40.93 76.88 39.99 75.5 39.99 75.5 38.89 76.88 38.89 76.88 37.95 75.5 37.95 75.5 36.85 76.88 36.85 76.88 36.59 75.5 36.59 75.5 35.49 76.88 35.49 76.88 35.23 75.5 35.23 75.5 34.13 76.88 34.13 76.88 33.19 75.5 33.19 75.5 32.09 76.88 32.09 76.88 31.83 75.5 31.83 75.5 30.73 76.88 30.73 76.88 30.47 75.5 30.47 75.5 29.37 76.88 29.37 76.88 29.11 75.5 29.11 75.5 28.01 76.88 28.01 76.88 27.75 75.5 27.75 75.5 26.65 76.88 26.65 76.88 26.39 75.5 26.39 75.5 25.29 76.88 25.29 76.88 25.03 75.5 25.03 75.5 23.93 76.88 23.93 76.88 23.67 75.5 23.67 75.5 22.57 76.88 22.57 76.88 22.31 75.5 22.31 75.5 21.21 76.88 21.21 76.88 20.95 75.5 20.95 75.5 19.85 76.88 19.85 76.88 19.59 75.5 19.59 75.5 18.49 76.88 18.49 76.88 18.23 75.5 18.23 75.5 17.13 76.88 17.13 76.88 16.87 75.5 16.87 75.5 15.77 76.88 15.77 76.88 15.51 75.5 15.51 75.5 14.41 76.88 14.41 76.88 14.15 75.5 14.15 75.5 13.05 76.88 13.05 76.88 12.79 75.5 12.79 75.5 11.69 76.88 11.69 76.88 11.43 75.5 11.43 75.5 10.33 76.88 10.33 76.88 10.07 75.5 10.07 75.5 8.97 76.88 8.97 76.88 8.71 75.5 8.71 75.5 7.61 76.88 7.61 76.88 7.35 75.5 7.35 75.5 6.25 76.88 6.25 76.88 5.99 75.5 5.99 75.5 4.89 76.88 4.89 76.88 4.63 75.5 4.63 75.5 3.53 76.88 3.53 76.88 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 ; - LAYER met4 ; - POLYGON 76.88 64.88 76.88 0.4 68.78 0.4 68.78 1 67.38 1 67.38 0.4 54.06 0.4 54.06 1 52.66 1 52.66 0.4 39.34 0.4 39.34 1 37.94 1 37.94 0.4 24.62 0.4 24.62 1 23.22 1 23.22 0.4 9.9 0.4 9.9 1 8.5 1 8.5 0.4 5.15 0.4 5.15 1.76 4.05 1.76 4.05 0.4 0.4 0.4 0.4 64.88 8.5 64.88 8.5 64.28 9.9 64.28 9.9 64.88 23.22 64.88 23.22 64.28 24.62 64.28 24.62 64.88 37.94 64.88 37.94 64.28 39.34 64.28 39.34 64.88 52.66 64.88 52.66 64.28 54.06 64.28 54.06 64.88 67.38 64.88 67.38 64.28 68.78 64.28 68.78 64.88 ; + POLYGON 56.285 87.205 56.285 87.2 56.5 87.2 56.5 86.88 56.285 86.88 56.285 86.875 55.955 86.875 55.955 86.88 55.74 86.88 55.74 87.2 55.955 87.2 55.955 87.205 ; + POLYGON 26.845 87.205 26.845 87.2 27.06 87.2 27.06 86.88 26.845 86.88 26.845 86.875 26.515 86.875 26.515 86.88 26.3 86.88 26.3 87.2 26.515 87.2 26.515 87.205 ; + POLYGON 66.43 53.88 66.43 53.56 66.05 53.56 66.05 53.57 51.37 53.57 51.37 53.87 66.05 53.87 66.05 53.88 ; + POLYGON 20.39 41.63 20.39 41.33 1.99 41.33 1.99 40.65 1.78 40.65 1.78 41.35 1.69 41.35 1.69 41.63 ; + POLYGON 66.43 33.48 66.43 33.16 66.05 33.16 66.05 33.17 53.21 33.17 53.21 33.47 66.05 33.47 66.05 33.48 ; + POLYGON 66.865 17.845 66.865 17.515 66.535 17.515 66.535 17.53 60.57 17.53 60.57 17.83 66.535 17.83 66.535 17.845 ; + POLYGON 2.005 11.725 2.005 11.71 28.21 11.71 28.21 11.41 2.005 11.41 2.005 11.395 1.99 11.395 1.99 10.73 1.78 10.73 1.78 11.43 1.675 11.43 1.675 11.725 ; + POLYGON 2.03 6.28 2.03 6.27 60.87 6.27 60.87 5.97 2.03 5.97 2.03 5.96 1.65 5.96 1.65 6.28 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 86.64 67.68 79.43 66.3 79.43 66.3 78.33 67.68 78.33 67.68 65.15 66.3 65.15 66.3 64.05 67.68 64.05 67.68 63.79 66.3 63.79 66.3 62.69 67.68 62.69 67.68 62.43 66.3 62.43 66.3 61.33 67.68 61.33 67.68 61.07 66.3 61.07 66.3 59.97 67.68 59.97 67.68 59.71 66.3 59.71 66.3 58.61 67.68 58.61 67.68 58.35 66.3 58.35 66.3 57.25 67.68 57.25 67.68 54.95 66.3 54.95 66.3 53.85 67.68 53.85 67.68 53.59 66.3 53.59 66.3 52.49 67.68 52.49 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 50.87 66.3 50.87 66.3 49.77 67.68 49.77 67.68 49.51 66.3 49.51 66.3 48.41 67.68 48.41 67.68 48.15 66.3 48.15 66.3 47.05 67.68 47.05 67.68 46.79 66.3 46.79 66.3 45.69 67.68 45.69 67.68 45.43 66.3 45.43 66.3 44.33 67.68 44.33 67.68 44.07 66.3 44.07 66.3 42.97 67.68 42.97 67.68 42.71 66.3 42.71 66.3 41.61 67.68 41.61 67.68 41.35 66.3 41.35 66.3 40.25 67.68 40.25 67.68 39.99 66.3 39.99 66.3 38.89 67.68 38.89 67.68 38.63 66.3 38.63 66.3 37.53 67.68 37.53 67.68 37.27 66.3 37.27 66.3 36.17 67.68 36.17 67.68 35.91 66.3 35.91 66.3 34.81 67.68 34.81 67.68 34.55 66.3 34.55 66.3 33.45 67.68 33.45 67.68 33.19 66.3 33.19 66.3 32.09 67.68 32.09 67.68 31.15 66.3 31.15 66.3 30.05 67.68 30.05 67.68 29.79 66.3 29.79 66.3 28.69 67.68 28.69 67.68 28.43 66.3 28.43 66.3 27.33 67.68 27.33 67.68 27.07 66.3 27.07 66.3 25.97 67.68 25.97 67.68 25.71 66.3 25.71 66.3 24.61 67.68 24.61 67.68 24.35 66.3 24.35 66.3 23.25 67.68 23.25 67.68 22.99 66.3 22.99 66.3 21.89 67.68 21.89 67.68 21.63 66.3 21.63 66.3 20.53 67.68 20.53 67.68 20.27 66.3 20.27 66.3 19.17 67.68 19.17 67.68 18.91 66.3 18.91 66.3 17.81 67.68 17.81 67.68 17.55 66.3 17.55 66.3 16.45 67.68 16.45 67.68 16.19 66.3 16.19 66.3 15.09 67.68 15.09 67.68 14.83 66.3 14.83 66.3 13.73 67.68 13.73 67.68 13.47 66.3 13.47 66.3 12.37 67.68 12.37 67.68 12.11 66.3 12.11 66.3 11.01 67.68 11.01 67.68 10.07 66.3 10.07 66.3 8.97 67.68 8.97 67.68 8.71 66.3 8.71 66.3 7.61 67.68 7.61 67.68 7.35 66.3 7.35 66.3 6.25 67.68 6.25 67.68 3.95 66.3 3.95 66.3 2.85 67.68 2.85 67.68 0.4 0.4 0.4 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.09 1.78 15.09 1.78 16.19 0.4 16.19 0.4 16.45 1.78 16.45 1.78 17.55 0.4 17.55 0.4 17.81 1.78 17.81 1.78 18.91 0.4 18.91 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 86.64 ; LAYER met1 ; - POLYGON 77 64.76 77 63.08 76.52 63.08 76.52 62.04 77 62.04 77 60.36 76.52 60.36 76.52 59.32 77 59.32 77 57.64 76.52 57.64 76.52 56.6 77 56.6 77 54.92 76.52 54.92 76.52 53.88 77 53.88 77 52.2 76.52 52.2 76.52 51.16 77 51.16 77 49.48 76.52 49.48 76.52 48.44 77 48.44 77 46.76 76.52 46.76 76.52 45.72 77 45.72 77 44.04 76.52 44.04 76.52 43 77 43 77 41.32 76.52 41.32 76.52 40.28 77 40.28 77 38.6 76.52 38.6 76.52 37.56 77 37.56 77 35.88 76.52 35.88 76.52 34.84 77 34.84 77 33.16 76.52 33.16 76.52 32.12 77 32.12 77 30.44 76.52 30.44 76.52 29.4 77 29.4 77 27.72 76.52 27.72 76.52 26.68 77 26.68 77 25 76.52 25 76.52 23.96 77 23.96 77 22.28 76.52 22.28 76.52 21.24 77 21.24 77 19.56 76.52 19.56 76.52 18.52 77 18.52 77 16.84 76.52 16.84 76.52 15.8 77 15.8 77 14.12 76.52 14.12 76.52 13.08 77 13.08 77 11.4 76.52 11.4 76.52 10.36 77 10.36 77 8.68 76.52 8.68 76.52 7.64 77 7.64 77 5.96 76.52 5.96 76.52 4.92 77 4.92 77 3.24 76.52 3.24 76.52 2.2 77 2.2 77 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 67.8 86.52 67.8 84.84 67.32 84.84 67.32 83.8 67.8 83.8 67.8 82.12 67.32 82.12 67.32 81.08 67.8 81.08 67.8 79.4 67.32 79.4 67.32 78.36 67.8 78.36 67.8 76.68 67.32 76.68 67.32 75.64 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER met5 ; - POLYGON 75.68 63.68 75.68 56.24 72.48 56.24 72.48 49.84 75.68 49.84 75.68 35.84 72.48 35.84 72.48 29.44 75.68 29.44 75.68 15.44 72.48 15.44 72.48 9.04 75.68 9.04 75.68 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 ; + POLYGON 66.48 85.44 66.48 77.32 63.28 77.32 63.28 70.92 66.48 70.92 66.48 56.92 63.28 56.92 63.28 50.52 66.48 50.52 66.48 36.52 63.28 36.52 63.28 30.12 66.48 30.12 66.48 16.12 63.28 16.12 63.28 9.72 66.48 9.72 66.48 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 ; + LAYER met4 ; + POLYGON 67.68 86.64 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 86.64 11.26 86.64 11.26 86.04 12.66 86.04 12.66 86.64 25.98 86.64 25.98 86.04 27.38 86.04 27.38 86.64 40.7 86.64 40.7 86.04 42.1 86.04 42.1 86.64 55.42 86.64 55.42 86.04 56.82 86.04 56.82 86.64 ; LAYER li1 ; - RECT 0.17 0.17 77.11 65.11 ; + RECT 0.17 0.17 67.91 86.87 ; LAYER mcon ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 67.765 84.235 67.935 84.405 ; + RECT 67.305 84.235 67.475 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 67.765 81.515 67.935 81.685 ; + RECT 67.305 81.515 67.475 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 67.765 78.795 67.935 78.965 ; + RECT 67.305 78.795 67.475 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; RECT 67.765 65.195 67.935 65.365 ; RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 76.965 62.475 77.135 62.645 ; - RECT 76.505 62.475 76.675 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 76.965 59.755 77.135 59.925 ; - RECT 76.505 59.755 76.675 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 76.965 57.035 77.135 57.205 ; - RECT 76.505 57.035 76.675 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 76.965 54.315 77.135 54.485 ; - RECT 76.505 54.315 76.675 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 76.965 51.595 77.135 51.765 ; - RECT 76.505 51.595 76.675 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 76.965 48.875 77.135 49.045 ; - RECT 76.505 48.875 76.675 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 76.965 46.155 77.135 46.325 ; - RECT 76.505 46.155 76.675 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 76.965 43.435 77.135 43.605 ; - RECT 76.505 43.435 76.675 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 76.965 40.715 77.135 40.885 ; - RECT 76.505 40.715 76.675 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 76.965 37.995 77.135 38.165 ; - RECT 76.505 37.995 76.675 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 76.965 35.275 77.135 35.445 ; - RECT 76.505 35.275 76.675 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 76.965 32.555 77.135 32.725 ; - RECT 76.505 32.555 76.675 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 76.965 29.835 77.135 30.005 ; - RECT 76.505 29.835 76.675 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 76.965 27.115 77.135 27.285 ; - RECT 76.505 27.115 76.675 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 76.965 24.395 77.135 24.565 ; - RECT 76.505 24.395 76.675 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 76.965 21.675 77.135 21.845 ; - RECT 76.505 21.675 76.675 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 76.965 18.955 77.135 19.125 ; - RECT 76.505 18.955 76.675 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 76.965 13.515 77.135 13.685 ; - RECT 76.505 13.515 76.675 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 76.965 10.795 77.135 10.965 ; - RECT 76.505 10.795 76.675 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 76.965 8.075 77.135 8.245 ; - RECT 76.505 8.075 76.675 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 76.965 5.355 77.135 5.525 ; - RECT 76.505 5.355 76.675 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 76.965 2.635 77.135 2.805 ; - RECT 76.505 2.635 76.675 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; - RECT 76.965 -0.085 77.135 0.085 ; - RECT 76.505 -0.085 76.675 0.085 ; - RECT 76.045 -0.085 76.215 0.085 ; - RECT 75.585 -0.085 75.755 0.085 ; - RECT 75.125 -0.085 75.295 0.085 ; - RECT 74.665 -0.085 74.835 0.085 ; - RECT 74.205 -0.085 74.375 0.085 ; - RECT 73.745 -0.085 73.915 0.085 ; - RECT 73.285 -0.085 73.455 0.085 ; - RECT 72.825 -0.085 72.995 0.085 ; - RECT 72.365 -0.085 72.535 0.085 ; - RECT 71.905 -0.085 72.075 0.085 ; - RECT 71.445 -0.085 71.615 0.085 ; - RECT 70.985 -0.085 71.155 0.085 ; - RECT 70.525 -0.085 70.695 0.085 ; - RECT 70.065 -0.085 70.235 0.085 ; - RECT 69.605 -0.085 69.775 0.085 ; - RECT 69.145 -0.085 69.315 0.085 ; - RECT 68.685 -0.085 68.855 0.085 ; - RECT 68.225 -0.085 68.395 0.085 ; RECT 67.765 -0.085 67.935 0.085 ; RECT 67.305 -0.085 67.475 0.085 ; RECT 66.845 -0.085 67.015 0.085 ; @@ -1832,44 +1850,52 @@ MACRO cbx_1__2_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 68.005 65.205 68.155 65.355 ; - RECT 38.565 65.205 38.715 65.355 ; - RECT 9.125 65.205 9.275 65.355 ; - RECT 37.645 63.505 37.795 63.655 ; - RECT 58.805 1.625 58.955 1.775 ; - RECT 16.945 1.625 17.095 1.775 ; - RECT 68.005 -0.075 68.155 0.075 ; - RECT 38.565 -0.075 38.715 0.075 ; - RECT 9.125 -0.075 9.275 0.075 ; + RECT 56.045 86.965 56.195 87.115 ; + RECT 26.605 86.965 26.755 87.115 ; + RECT 59.265 85.265 59.415 85.415 ; + RECT 45.925 85.265 46.075 85.415 ; + RECT 11.885 1.625 12.035 1.775 ; + RECT 10.965 1.625 11.115 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 1.74 59.74 1.94 59.94 ; - RECT 75.8 48.86 76 49.06 ; - RECT 1.28 47.5 1.48 47.7 ; - RECT 75.8 42.74 76 42.94 ; - RECT 1.74 40.02 1.94 40.22 ; - RECT 75.34 31.18 75.54 31.38 ; - RECT 75.8 29.82 76 30.02 ; - RECT 1.28 20.98 1.48 21.18 ; - RECT 1.74 19.62 1.94 19.82 ; - RECT 75.8 8.06 76 8.26 ; - RECT 1.28 5.34 1.48 5.54 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 1.28 70.62 1.48 70.82 ; + RECT 1.28 64.5 1.48 64.7 ; + RECT 1.28 61.78 1.48 61.98 ; + RECT 66.6 60.42 66.8 60.62 ; + RECT 1.74 60.42 1.94 60.62 ; + RECT 1.28 57.02 1.48 57.22 ; + RECT 1.28 51.58 1.48 51.78 ; + RECT 1.28 50.22 1.48 50.42 ; + RECT 66.6 48.86 66.8 49.06 ; + RECT 1.28 44.1 1.48 44.3 ; + RECT 1.28 42.06 1.48 42.26 ; + RECT 1.74 39.34 1.94 39.54 ; + RECT 66.6 36.62 66.8 36.82 ; + RECT 1.74 31.86 1.94 32.06 ; + RECT 66.6 30.5 66.8 30.7 ; + RECT 1.28 29.82 1.48 30.02 ; + RECT 66.14 27.78 66.34 27.98 ; + RECT 1.74 26.42 1.94 26.62 ; + RECT 1.74 23.7 1.94 23.9 ; + RECT 66.14 22.34 66.34 22.54 ; + RECT 66.6 15.54 66.8 15.74 ; + RECT 1.28 15.54 1.48 15.74 ; + RECT 66.6 12.82 66.8 13.02 ; + RECT 66.14 3.3 66.34 3.5 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 67.98 65.18 68.18 65.38 ; - RECT 38.54 65.18 38.74 65.38 ; - RECT 9.1 65.18 9.3 65.38 ; - RECT 1.74 36.62 1.94 36.82 ; - RECT 1.74 14.18 1.94 14.38 ; - RECT 67.98 -0.1 68.18 0.1 ; - RECT 38.54 -0.1 38.74 0.1 ; - RECT 9.1 -0.1 9.3 0.1 ; + RECT 56.02 86.94 56.22 87.14 ; + RECT 26.58 86.94 26.78 87.14 ; + RECT 1.74 74.7 1.94 74.9 ; + RECT 66.14 51.58 66.34 51.78 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 65.28 77.28 65.28 77.28 0 ; + POLYGON 0 0 0 87.04 68.08 87.04 68.08 0 ; END END cbx_1__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef index 36f257d..0e2544b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_0__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cby_0__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; + SIZE 68.08 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met3 ; - RECT 0 3.25 1.38 3.55 ; + LAYER met2 ; + RECT 48.23 0 48.37 1.36 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -371,7 +371,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 14.65 0 14.79 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,15 +387,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 65.71 0 65.85 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 20.09 0 20.39 1.36 ; + LAYER met2 ; + RECT 16.49 0 16.63 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,47 +403,47 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 64.33 0 64.47 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 43.09 0 43.39 1.36 ; + LAYER met2 ; + RECT 35.81 0 35.95 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; + LAYER met2 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 50.45 0 50.75 1.36 ; + LAYER met2 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 0 45.23 1.36 ; + LAYER met2 ; + RECT 15.57 0 15.71 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; + LAYER met2 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; + RECT 61.49 0 61.79 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; + RECT 39.41 0 39.71 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 0 29.59 1.36 ; + RECT 15.49 0 15.79 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 21.93 0 22.23 1.36 ; + RECT 35.73 0 36.03 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; + RECT 59.65 0 59.95 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; + RECT 57.81 0 58.11 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 0 24.07 1.36 ; + RECT 37.57 0 37.87 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,7 +531,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 74.8 54.35 76.16 ; + RECT 53.75 74.8 53.89 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -539,7 +539,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 74.8 48.37 76.16 ; + RECT 55.13 74.8 55.27 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,7 +547,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 74.8 57.57 76.16 ; + RECT 65.25 74.8 65.39 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -555,7 +555,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; + RECT 61.11 74.8 61.25 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,7 +563,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; + RECT 52.83 74.8 52.97 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -571,7 +571,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 17.41 74.8 17.55 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -579,7 +579,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 74.8 26.75 76.16 ; + RECT 39.95 74.8 40.09 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -587,7 +587,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; + RECT 60.19 74.8 60.33 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,7 +595,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 74.8 47.45 76.16 ; + RECT 59.27 74.8 59.41 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -603,7 +603,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 35.35 74.8 35.49 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,15 +611,15 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 74.8 62.17 76.16 ; + RECT 62.95 74.8 63.09 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 74.8 45.23 76.16 ; + LAYER met2 ; + RECT 39.03 74.8 39.17 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,31 +627,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 74.8 49.29 76.16 ; + RECT 41.79 74.8 41.93 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 74.8 9.35 76.16 ; + LAYER met2 ; + RECT 14.65 74.8 14.79 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 48.61 74.8 48.91 76.16 ; + LAYER met2 ; + RECT 16.49 74.8 16.63 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 74.8 47.07 76.16 ; + LAYER met2 ; + RECT 36.27 74.8 36.41 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,31 +659,31 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 74.8 41.01 76.16 ; + RECT 43.63 74.8 43.77 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 74.8 5.67 76.16 ; + LAYER met2 ; + RECT 57.43 74.8 57.57 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 23.77 74.8 24.07 76.16 ; + LAYER met2 ; + RECT 15.57 74.8 15.71 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 7.21 74.8 7.51 76.16 ; + LAYER met2 ; + RECT 58.35 74.8 58.49 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 74.8 43.77 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -699,7 +699,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -707,7 +707,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -715,7 +715,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,7 +723,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -731,7 +731,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; + RECT 18.33 0 18.47 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,7 +771,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 36.65 0 36.95 1.36 ; + RECT 17.33 0 17.63 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -779,7 +779,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 38.49 0 38.79 1.36 ; + RECT 54.13 0 54.43 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,7 +787,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -795,7 +795,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 54.21 0 54.35 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; + RECT 13.73 0 13.87 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,7 +819,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 17.41 0 17.55 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -827,7 +827,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; + RECT 33.97 0 34.11 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 56.89 0 57.19 1.36 ; + RECT 63.33 0 63.63 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 52.29 0 52.59 1.36 ; + RECT 33.89 0 34.19 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,7 +851,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] @@ -867,7 +867,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 74.8 45.61 76.16 ; + RECT 48.23 74.8 48.37 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -875,7 +875,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; + RECT 63.87 74.8 64.01 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; + RECT 62.03 74.8 62.17 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; + RECT 46.39 74.8 46.53 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 74.8 50.21 76.16 ; + RECT 44.55 74.8 44.69 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; + RECT 19.25 74.8 19.39 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + RECT 34.43 74.8 34.57 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; + RECT 12.81 74.8 12.95 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 18.33 74.8 18.47 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 74.8 33.65 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; + RECT 32.59 74.8 32.73 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -955,7 +955,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; + RECT 45.47 74.8 45.61 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -963,7 +963,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; + RECT 33.51 74.8 33.65 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; + RECT 40.87 74.8 41.01 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 13.73 74.8 13.87 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.27 74.8 36.41 76.16 ; + RECT 25.69 74.8 25.83 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 74.8 6.51 76.16 ; + RECT 10.97 74.8 11.11 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 74.8 31.35 76.16 ; + RECT 11.89 74.8 12.03 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,7 +1011,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 74.8 7.43 76.16 ; + RECT 10.05 74.8 10.19 76.16 ; END END chany_top_out[19] PIN left_grid_pin_0_[0] @@ -1019,7 +1019,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 24.31 0 24.45 1.36 ; END END left_grid_pin_0_[0] PIN ccff_tail[0] @@ -1027,7 +1027,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 40.65 66.24 40.95 ; + RECT 66.7 51.53 68.08 51.83 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1043,7 +1043,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 64.45 1.38 64.75 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1051,7 +1051,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 57.65 1.38 57.95 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN right_width_0_height_0__pin_0_[0] @@ -1059,7 +1059,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 23.39 0 23.53 1.36 ; END END right_width_0_height_0__pin_0_[0] PIN right_width_0_height_0__pin_1_upper[0] @@ -1067,7 +1067,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 74.8 64.01 76.16 ; + RECT 50.99 74.8 51.13 76.16 ; END END right_width_0_height_0__pin_1_upper[0] PIN right_width_0_height_0__pin_1_lower[0] @@ -1075,7 +1075,7 @@ MACRO cby_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END right_width_0_height_0__pin_1_lower[0] PIN VDD @@ -1083,42 +1083,44 @@ MACRO cby_0__1_ USE POWER ; PORT LAYER met5 ; - RECT 0 36.48 3.2 39.68 ; - RECT 63.04 36.48 66.24 39.68 ; + RECT 0 5.88 3.2 9.08 ; + RECT 64.88 5.88 68.08 9.08 ; + RECT 0 46.68 3.2 49.88 ; + RECT 64.88 46.68 68.08 49.88 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 75.56 12.26 76.16 ; + RECT 41.1 75.56 41.7 76.16 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; END END VDD PIN VSS @@ -1126,125 +1128,139 @@ MACRO cby_0__1_ USE GROUND ; PORT LAYER met5 ; - RECT 0 16.08 3.2 19.28 ; - RECT 63.04 16.08 66.24 19.28 ; - RECT 0 56.88 3.2 60.08 ; - RECT 63.04 56.88 66.24 60.08 ; + RECT 0 26.28 3.2 29.48 ; + RECT 64.88 26.28 68.08 29.48 ; + RECT 0 67.08 3.2 70.28 ; + RECT 64.88 67.08 68.08 70.28 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 75.56 26.98 76.16 ; + RECT 55.82 75.56 56.42 76.16 ; LAYER met1 ; - RECT 0 0 66.24 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; + RECT 67.6 59.6 68.08 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 68.08 76.16 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 37.65 74.8 37.79 76.16 ; + END + END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; + RECT 0 76.075 68.08 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; + RECT 67.16 70.635 68.08 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; + RECT 67.16 67.915 68.08 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; + RECT 67.16 65.195 68.08 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 65.78 62.475 66.24 62.645 ; + RECT 67.16 62.475 68.08 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 65.78 59.755 66.24 59.925 ; + RECT 67.16 59.755 68.08 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 65.78 57.035 66.24 57.205 ; + RECT 67.16 57.035 68.08 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 65.78 54.315 66.24 54.485 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 62.56 46.155 66.24 46.325 ; + RECT 67.16 46.155 68.08 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 62.56 43.435 66.24 43.605 ; + RECT 66.24 43.435 68.08 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; + RECT 66.24 40.715 68.08 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 64.4 37.995 66.24 38.165 ; + RECT 67.62 37.995 68.08 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 64.4 35.275 66.24 35.445 ; + RECT 66.24 35.275 68.08 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 65.78 32.555 66.24 32.725 ; + RECT 66.24 32.555 68.08 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 65.78 29.835 66.24 30.005 ; + RECT 67.16 29.835 68.08 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 65.78 27.115 66.24 27.285 ; + RECT 67.16 27.115 68.08 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 65.78 24.395 66.24 24.565 ; + RECT 67.16 24.395 68.08 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 64.4 21.675 66.24 21.845 ; + RECT 64.4 21.675 68.08 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 64.4 18.955 66.24 19.125 ; + RECT 64.4 18.955 68.08 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 62.56 16.235 66.24 16.405 ; + RECT 66.24 16.235 68.08 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 62.56 13.515 66.24 13.685 ; + RECT 66.24 13.515 68.08 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; + RECT 67.16 10.795 68.08 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.78 5.355 66.24 5.525 ; + RECT 67.16 5.355 68.08 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 65.78 2.635 66.24 2.805 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 75.76 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 63.59 75.88 63.59 74.52 64.29 74.52 64.29 75.88 ; + RECT 55.98 75.975 56.26 76.345 ; + RECT 26.54 75.975 26.82 76.345 ; + POLYGON 45.61 74.53 45.61 69.97 45.47 69.97 45.47 74.39 44.55 74.39 44.55 74.52 44.97 74.52 44.97 74.53 ; + RECT 24.71 1.54 24.97 1.86 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 75.88 67.8 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 0.28 0.28 0.28 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.29 75.88 15.29 74.52 15.99 74.52 15.99 75.88 16.21 75.88 16.21 74.52 16.91 74.52 16.91 75.88 17.13 75.88 17.13 74.52 17.83 74.52 17.83 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 25.41 75.88 25.41 74.52 26.11 74.52 26.11 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 35.07 75.88 35.07 74.52 35.77 74.52 35.77 75.88 35.99 75.88 35.99 74.52 36.69 74.52 36.69 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 57.15 75.88 57.15 74.52 57.85 74.52 57.85 75.88 58.07 75.88 58.07 74.52 58.77 74.52 58.77 75.88 58.99 75.88 58.99 74.52 59.69 74.52 59.69 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 62.67 75.88 62.67 74.52 63.37 74.52 63.37 75.88 63.59 75.88 63.59 74.52 64.29 74.52 64.29 75.88 64.97 75.88 64.97 74.52 65.67 74.52 65.67 75.88 ; LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 57.59 0.4 57.59 1.76 56.49 1.76 56.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 43.79 0.4 43.79 1.76 42.69 1.76 42.69 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 37.35 0.4 37.35 1.76 36.25 1.76 36.25 0.4 29.99 0.4 29.99 1.76 28.89 1.76 28.89 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 20.79 0.4 20.79 1.76 19.69 1.76 19.69 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 75.76 4.97 75.76 4.97 74.4 6.07 74.4 6.07 75.76 6.81 75.76 6.81 74.4 7.91 74.4 7.91 75.76 8.65 75.76 8.65 74.4 9.75 74.4 9.75 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 23.37 75.76 23.37 74.4 24.47 74.4 24.47 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 44.53 75.76 44.53 74.4 45.63 74.4 45.63 75.76 46.37 75.76 46.37 74.4 47.47 74.4 47.47 75.76 48.21 75.76 48.21 74.4 49.31 74.4 49.31 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; + POLYGON 67.68 75.76 67.68 0.4 64.03 0.4 64.03 1.76 62.93 1.76 62.93 0.4 62.19 0.4 62.19 1.76 61.09 1.76 61.09 0.4 60.35 0.4 60.35 1.76 59.25 1.76 59.25 0.4 58.51 0.4 58.51 1.76 57.41 1.76 57.41 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 54.83 0.4 54.83 1.76 53.73 1.76 53.73 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 40.11 0.4 40.11 1.76 39.01 1.76 39.01 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 36.43 0.4 36.43 1.76 35.33 1.76 35.33 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 18.03 0.4 18.03 1.76 16.93 1.76 16.93 0.4 16.19 0.4 16.19 1.76 15.09 1.76 15.09 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; + LAYER met3 ; + POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; + POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 75.76 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 0.4 0.4 0.4 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 75.76 ; LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER met5 ; - POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; + RECT 0.17 0.17 67.91 75.99 ; LAYER mcon ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1389,114 +1405,118 @@ MACRO cby_0__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; + RECT 67.765 65.195 67.935 65.365 ; + RECT 67.305 65.195 67.475 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1642,26 +1662,22 @@ MACRO cby_0__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 31.205 74.385 31.355 74.535 ; - RECT 51.445 1.625 51.595 1.775 ; - RECT 7.285 1.625 7.435 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 76.085 56.195 76.235 ; + RECT 26.605 76.085 26.755 76.235 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.74 3.3 1.94 3.5 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; + POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; END END cby_0__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef index 0740927..8f98901 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cby_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; + SIZE 68.08 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met3 ; - RECT 0 3.25 1.38 3.55 ; + LAYER met2 ; + RECT 29.83 0 29.97 1.36 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -371,7 +371,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 27.99 0 28.13 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,7 +387,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.07 0 27.21 1.36 ; + RECT 32.13 0 32.27 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 21.55 0 21.69 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 37.19 0 37.33 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 0 53.43 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 0 44.23 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 7.29 0 7.43 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 9.13 0 9.27 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,7 +531,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 74.8 53.89 76.16 ; + RECT 30.29 74.8 30.43 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -539,7 +539,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 74.8 36.87 76.16 ; + RECT 34.89 74.8 35.03 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,7 +547,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 74.8 28.59 76.16 ; + RECT 31.21 74.8 31.35 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -555,7 +555,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 74.8 45.15 76.16 ; + RECT 51.91 74.8 52.05 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,7 +563,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 74.8 27.67 76.16 ; + RECT 25.23 74.8 25.37 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -571,7 +571,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 74.8 52.05 76.16 ; + RECT 60.19 74.8 60.33 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -579,7 +579,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.11 74.8 15.25 76.16 ; + RECT 22.47 74.8 22.61 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -587,7 +587,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; + RECT 50.07 74.8 50.21 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,7 +595,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 74.8 41.01 76.16 ; + RECT 57.89 74.8 58.03 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -603,7 +603,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 74.8 47.45 76.16 ; + RECT 45.47 74.8 45.61 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,7 +611,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 24.31 74.8 24.45 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -619,7 +619,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 74.8 48.37 76.16 ; + RECT 49.15 74.8 49.29 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,7 +627,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 16.03 74.8 16.17 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -635,7 +635,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 74.8 49.29 76.16 ; + RECT 61.11 74.8 61.25 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -643,7 +643,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 23.39 74.8 23.53 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -651,7 +651,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 74.8 62.63 76.16 ; + RECT 62.03 74.8 62.17 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,7 +659,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + RECT 56.97 74.8 57.11 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -667,7 +667,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 74.8 50.21 76.16 ; + RECT 44.55 74.8 44.69 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -675,7 +675,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 74.8 26.75 76.16 ; + RECT 29.37 74.8 29.51 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -683,7 +683,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 74.8 51.13 76.16 ; + RECT 62.95 74.8 63.09 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 54.25 1.38 54.55 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -699,7 +699,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -707,7 +707,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.89 0 35.03 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -715,7 +715,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 0 34.11 1.36 ; + RECT 38.11 0 38.25 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,15 +723,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 42.17 0 42.47 1.36 ; + LAYER met2 ; + RECT 33.05 0 33.19 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 31.21 0 31.35 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,7 +771,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -779,7 +779,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 37.57 0 37.87 1.36 ; + RECT 38.49 0 38.79 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,7 +787,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 22.93 0 23.07 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -795,7 +795,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 58.81 0 58.95 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 0 35.95 1.36 ; + RECT 35.35 0 35.49 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,15 +819,15 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.01 0 44.31 1.36 ; + LAYER met2 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + RECT 47.31 0 47.45 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,7 +851,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 23.85 0 23.99 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] @@ -859,7 +859,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 74.8 32.27 76.16 ; + RECT 40.87 74.8 41.01 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -867,7 +867,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 74.8 39.63 76.16 ; + RECT 41.79 74.8 41.93 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -875,7 +875,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 74.8 38.71 76.16 ; + RECT 52.83 74.8 52.97 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.09 74.8 44.23 76.16 ; + RECT 42.71 74.8 42.85 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 74.8 30.43 76.16 ; + RECT 33.05 74.8 33.19 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 74.8 41.93 76.16 ; + RECT 36.73 74.8 36.87 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.81 74.8 58.95 76.16 ; + RECT 33.97 74.8 34.11 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 74.8 34.11 76.16 ; + RECT 46.85 74.8 46.99 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 74.8 42.85 76.16 ; + RECT 39.95 74.8 40.09 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 55.13 74.8 55.27 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 74.8 37.79 76.16 ; + RECT 43.63 74.8 43.77 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 74.8 31.35 76.16 ; + RECT 47.77 74.8 47.91 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -955,7 +955,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 74.8 29.51 76.16 ; + RECT 39.03 74.8 39.17 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -963,7 +963,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 74.8 52.97 76.16 ; + RECT 20.63 74.8 20.77 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 74.8 57.11 76.16 ; + RECT 53.75 74.8 53.89 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.19 74.8 14.33 76.16 ; + RECT 21.55 74.8 21.69 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 74.8 33.19 76.16 ; + RECT 32.13 74.8 32.27 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 74.8 56.19 76.16 ; + RECT 35.81 74.8 35.95 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 74.8 58.03 76.16 ; + RECT 38.11 74.8 38.25 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,7 +1011,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.81 74.8 35.95 76.16 ; + RECT 50.99 74.8 51.13 76.16 ; END END chany_top_out[19] PIN left_grid_pin_16_[0] @@ -1019,7 +1019,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 31.13 1.38 31.43 ; END END left_grid_pin_16_[0] PIN left_grid_pin_17_[0] @@ -1027,7 +1027,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 28.41 1.38 28.71 ; END END left_grid_pin_17_[0] PIN left_grid_pin_18_[0] @@ -1035,7 +1035,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 27.05 1.38 27.35 ; END END left_grid_pin_18_[0] PIN left_grid_pin_19_[0] @@ -1043,7 +1043,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 32.49 1.38 32.79 ; END END left_grid_pin_19_[0] PIN left_grid_pin_20_[0] @@ -1051,7 +1051,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 12.77 1.38 13.07 ; END END left_grid_pin_20_[0] PIN left_grid_pin_21_[0] @@ -1059,7 +1059,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 4.61 1.38 4.91 ; END END left_grid_pin_21_[0] PIN left_grid_pin_22_[0] @@ -1067,7 +1067,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 25.69 1.38 25.99 ; END END left_grid_pin_22_[0] PIN left_grid_pin_23_[0] @@ -1075,7 +1075,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 24.33 1.38 24.63 ; END END left_grid_pin_23_[0] PIN left_grid_pin_24_[0] @@ -1083,7 +1083,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 5.97 1.38 6.27 ; END END left_grid_pin_24_[0] PIN left_grid_pin_25_[0] @@ -1091,7 +1091,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 8.69 1.38 8.99 ; END END left_grid_pin_25_[0] PIN left_grid_pin_26_[0] @@ -1099,7 +1099,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 7.33 1.38 7.63 ; END END left_grid_pin_26_[0] PIN left_grid_pin_27_[0] @@ -1107,7 +1107,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 29.77 1.38 30.07 ; END END left_grid_pin_27_[0] PIN left_grid_pin_28_[0] @@ -1115,7 +1115,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 50.17 1.38 50.47 ; END END left_grid_pin_28_[0] PIN left_grid_pin_29_[0] @@ -1123,7 +1123,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 52.89 1.38 53.19 ; END END left_grid_pin_29_[0] PIN left_grid_pin_30_[0] @@ -1131,7 +1131,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 48.81 1.38 49.11 ; END END left_grid_pin_30_[0] PIN left_grid_pin_31_[0] @@ -1139,7 +1139,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 51.53 1.38 51.83 ; END END left_grid_pin_31_[0] PIN ccff_tail[0] @@ -1147,7 +1147,7 @@ MACRO cby_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 40.65 66.24 40.95 ; + RECT 66.7 51.53 68.08 51.83 ; END END ccff_tail[0] PIN VDD @@ -1156,41 +1156,43 @@ MACRO cby_1__1_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; LAYER met5 ; - RECT 0 36.48 3.2 39.68 ; - RECT 63.04 36.48 66.24 39.68 ; + RECT 0 5.88 3.2 9.08 ; + RECT 64.88 5.88 68.08 9.08 ; + RECT 0 46.68 3.2 49.88 ; + RECT 64.88 46.68 68.08 49.88 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 75.56 12.26 76.16 ; + RECT 41.1 75.56 41.7 76.16 ; END END VDD PIN VSS @@ -1198,129 +1200,165 @@ MACRO cby_1__1_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 66.24 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; + RECT 67.6 59.6 68.08 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 68.08 76.16 ; LAYER met5 ; - RECT 0 16.08 3.2 19.28 ; - RECT 63.04 16.08 66.24 19.28 ; - RECT 0 56.88 3.2 60.08 ; - RECT 63.04 56.88 66.24 60.08 ; + RECT 0 26.28 3.2 29.48 ; + RECT 64.88 26.28 68.08 29.48 ; + RECT 0 67.08 3.2 70.28 ; + RECT 64.88 67.08 68.08 70.28 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 75.56 26.98 76.16 ; + RECT 55.82 75.56 56.42 76.16 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 66.7 9.37 68.08 9.67 ; + END + END prog_clk__FEEDTHRU_1[0] + PIN prog_clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 27.99 74.8 28.13 76.16 ; + END + END prog_clk__FEEDTHRU_2[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.21 0 8.35 1.36 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 8.21 74.8 8.35 76.16 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; + RECT 0 76.075 68.08 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; + RECT 67.16 70.635 68.08 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; + RECT 67.16 67.915 68.08 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 65.32 65.195 66.24 65.365 ; + RECT 67.16 65.195 68.08 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; + RECT 67.16 62.475 68.08 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; + RECT 67.16 59.755 68.08 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; + RECT 67.16 57.035 68.08 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 65.32 43.435 66.24 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; + RECT 67.16 46.155 68.08 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 67.16 43.435 68.08 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 67.16 40.715 68.08 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; + RECT 67.16 37.995 68.08 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; - RECT 0 35.275 3.68 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; - RECT 0 32.555 3.68 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; + RECT 67.16 35.275 68.08 35.445 ; + RECT 0 35.275 1.84 35.445 ; + RECT 67.16 32.555 68.08 32.725 ; + RECT 0 32.555 1.84 32.725 ; + RECT 67.16 29.835 68.08 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; + RECT 67.16 27.115 68.08 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; + RECT 67.16 24.395 68.08 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 67.16 21.675 68.08 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 67.16 18.955 68.08 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; + RECT 67.16 16.235 68.08 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; + RECT 64.4 13.515 68.08 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; + RECT 64.4 10.795 68.08 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; + RECT 67.16 5.355 68.08 5.525 ; RECT 0 5.355 1.84 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 41.35 64.46 41.35 64.46 40.25 65.84 40.25 65.84 0.4 0.4 0.4 0.4 2.85 1.78 2.85 1.78 3.95 0.4 3.95 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 75.76 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 56.45 74.3 56.71 74.62 ; - RECT 45.41 74.3 45.67 74.62 ; - RECT 23.33 74.3 23.59 74.62 ; - RECT 34.37 1.54 34.63 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.51 0.28 44.51 1.64 43.81 1.64 43.81 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 34.39 0.28 34.39 1.64 33.69 1.64 33.69 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 0.28 0.28 0.28 75.88 13.91 75.88 13.91 74.52 14.61 74.52 14.61 75.88 14.83 75.88 14.83 74.52 15.53 74.52 15.53 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.33 75.88 26.33 74.52 27.03 74.52 27.03 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.17 75.88 28.17 74.52 28.87 74.52 28.87 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.29 75.88 38.29 74.52 38.99 74.52 38.99 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 44.73 75.88 44.73 74.52 45.43 74.52 45.43 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 47.03 75.88 47.03 74.52 47.73 74.52 47.73 75.88 47.95 75.88 47.95 74.52 48.65 74.52 48.65 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 55.77 75.88 55.77 74.52 56.47 74.52 56.47 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 57.61 75.88 57.61 74.52 58.31 74.52 58.31 75.88 58.53 75.88 58.53 74.52 59.23 74.52 59.23 75.88 62.21 75.88 62.21 74.52 62.91 74.52 62.91 75.88 ; + RECT 55.98 75.975 56.26 76.345 ; + RECT 26.54 75.975 26.82 76.345 ; + RECT 48.17 74.3 48.43 74.62 ; + RECT 22.87 74.3 23.13 74.62 ; + RECT 41.73 1.54 41.99 1.86 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 75.88 67.8 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 37.61 0.28 37.61 1.64 36.91 1.64 36.91 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 0.28 0.28 0.28 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 20.35 75.88 20.35 74.52 21.05 74.52 21.05 75.88 21.27 75.88 21.27 74.52 21.97 74.52 21.97 75.88 22.19 75.88 22.19 74.52 22.89 74.52 22.89 75.88 23.11 75.88 23.11 74.52 23.81 74.52 23.81 75.88 24.03 75.88 24.03 74.52 24.73 74.52 24.73 75.88 24.95 75.88 24.95 74.52 25.65 74.52 25.65 75.88 27.71 75.88 27.71 74.52 28.41 74.52 28.41 75.88 29.09 75.88 29.09 74.52 29.79 74.52 29.79 75.88 30.01 75.88 30.01 74.52 30.71 74.52 30.71 75.88 30.93 75.88 30.93 74.52 31.63 74.52 31.63 75.88 31.85 75.88 31.85 74.52 32.55 74.52 32.55 75.88 32.77 75.88 32.77 74.52 33.47 74.52 33.47 75.88 33.69 75.88 33.69 74.52 34.39 74.52 34.39 75.88 34.61 75.88 34.61 74.52 35.31 74.52 35.31 75.88 35.53 75.88 35.53 74.52 36.23 74.52 36.23 75.88 36.45 75.88 36.45 74.52 37.15 74.52 37.15 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 40.59 75.88 40.59 74.52 41.29 74.52 41.29 75.88 41.51 75.88 41.51 74.52 42.21 74.52 42.21 75.88 42.43 75.88 42.43 74.52 43.13 74.52 43.13 75.88 43.35 75.88 43.35 74.52 44.05 74.52 44.05 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.57 75.88 46.57 74.52 47.27 74.52 47.27 75.88 47.49 75.88 47.49 74.52 48.19 74.52 48.19 75.88 48.87 75.88 48.87 74.52 49.57 74.52 49.57 75.88 49.79 75.88 49.79 74.52 50.49 74.52 50.49 75.88 50.71 75.88 50.71 74.52 51.41 74.52 51.41 75.88 51.63 75.88 51.63 74.52 52.33 74.52 52.33 75.88 52.55 75.88 52.55 74.52 53.25 74.52 53.25 75.88 53.47 75.88 53.47 74.52 54.17 74.52 54.17 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 57.61 75.88 57.61 74.52 58.31 74.52 58.31 75.88 59.91 75.88 59.91 74.52 60.61 74.52 60.61 75.88 60.83 75.88 60.83 74.52 61.53 74.52 61.53 75.88 61.75 75.88 61.75 74.52 62.45 74.52 62.45 75.88 62.67 75.88 62.67 74.52 63.37 74.52 63.37 75.88 ; + LAYER met3 ; + POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; + POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; + POLYGON 3.83 52.51 3.83 52.21 1.23 52.21 1.23 52.49 1.78 52.49 1.78 52.51 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 75.76 67.68 52.23 66.3 52.23 66.3 51.13 67.68 51.13 67.68 10.07 66.3 10.07 66.3 8.97 67.68 8.97 67.68 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 75.76 ; LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 44.71 0.4 44.71 1.76 43.61 1.76 43.61 0.4 42.87 0.4 42.87 1.76 41.77 1.76 41.77 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 38.27 0.4 38.27 1.76 37.17 1.76 37.17 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; + POLYGON 67.68 75.76 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; LAYER met5 ; - POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; + RECT 0.17 0.17 67.91 75.99 ; LAYER mcon ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1465,114 +1503,118 @@ MACRO cby_1__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; + RECT 67.765 65.195 67.935 65.365 ; + RECT 67.305 65.195 67.475 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1718,30 +1760,33 @@ MACRO cby_1__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 50.985 74.385 51.135 74.535 ; - RECT 48.225 74.385 48.375 74.535 ; - RECT 33.045 74.385 33.195 74.535 ; - RECT 40.865 1.625 41.015 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 76.085 56.195 76.235 ; + RECT 26.605 76.085 26.755 76.235 ; + RECT 62.025 74.385 62.175 74.535 ; + RECT 52.825 74.385 52.975 74.535 ; + RECT 29.365 74.385 29.515 74.535 ; + RECT 22.925 1.625 23.075 1.775 ; + RECT 8.205 1.625 8.355 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.74 58.38 1.94 58.58 ; - RECT 1.74 21.66 1.94 21.86 ; - RECT 1.28 16.22 1.48 16.42 ; - RECT 1.28 13.5 1.48 13.7 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 1.28 54.3 1.48 54.5 ; + RECT 66.14 51.58 66.34 51.78 ; + RECT 1.74 48.86 1.94 49.06 ; + RECT 1.28 25.74 1.48 25.94 ; + RECT 1.28 6.02 1.48 6.22 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 1.74 29.82 1.94 30.02 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; + POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; END END cby_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef index 6b8d7ab..e70b66d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/cby_2__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO cby_2__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 66.24 BY 76.16 ; + SIZE 68.08 BY 76.16 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + LAYER met3 ; + RECT 0 10.73 1.38 11.03 ; END END prog_clk[0] PIN chany_bottom_in[0] @@ -371,7 +371,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,7 +379,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 15.57 0 15.71 1.36 ; + RECT 23.39 0 23.53 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -387,7 +387,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 0 28.13 1.36 ; + RECT 27.53 0 27.67 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 11.43 0 11.57 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 14.19 0 14.33 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; + RECT 12.35 0 12.49 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.95 0 17.09 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 0 29.05 1.36 ; + RECT 10.51 0 10.65 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 0 19.39 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 0 18.47 1.36 ; + RECT 20.63 0 20.77 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 0 35.49 1.36 ; + RECT 9.59 0 9.73 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 0 11.11 1.36 ; + RECT 22.47 0 22.61 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 19.71 0 19.85 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.07 0 27.21 1.36 ; + RECT 15.11 0 15.25 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 0 6.51 1.36 ; + RECT 16.03 0 16.17 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 0 10.19 1.36 ; + RECT 13.27 0 13.41 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 18.79 0 18.93 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.13 0 9.27 1.36 ; + RECT 17.87 0 18.01 1.36 ; END END chany_bottom_in[19] PIN chany_top_in[0] @@ -531,7 +531,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 74.8 13.87 76.16 ; + RECT 27.53 74.8 27.67 76.16 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -539,7 +539,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 74.8 60.79 76.16 ; + RECT 51.45 74.8 51.59 76.16 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -547,7 +547,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 74.8 59.87 76.16 ; + RECT 49.61 74.8 49.75 76.16 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -555,7 +555,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 19.25 74.8 19.39 76.16 ; + RECT 11.89 74.8 12.03 76.16 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -563,7 +563,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 74.8 11.11 76.16 ; + RECT 13.73 74.8 13.87 76.16 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -571,7 +571,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 74.8 4.67 76.16 ; + RECT 10.97 74.8 11.11 76.16 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -579,7 +579,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 74.8 5.59 76.16 ; + RECT 30.75 74.8 30.89 76.16 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -587,7 +587,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.99 74.8 28.13 76.16 ; + RECT 21.09 74.8 21.23 76.16 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -595,7 +595,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 74.8 24.91 76.16 ; + RECT 9.13 74.8 9.27 76.16 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -603,7 +603,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 74.8 31.81 76.16 ; + RECT 7.29 74.8 7.43 76.16 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -611,7 +611,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 16.03 74.8 16.17 76.16 ; + RECT 25.69 74.8 25.83 76.16 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -619,7 +619,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.05 74.8 10.19 76.16 ; + RECT 20.17 74.8 20.31 76.16 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -627,7 +627,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 74.8 8.35 76.16 ; + RECT 18.33 74.8 18.47 76.16 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -635,7 +635,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 74.8 6.51 76.16 ; + RECT 12.81 74.8 12.95 76.16 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -643,7 +643,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 11.89 74.8 12.03 76.16 ; + RECT 50.53 74.8 50.67 76.16 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -651,7 +651,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.91 74.8 29.05 76.16 ; + RECT 38.57 74.8 38.71 76.16 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -659,7 +659,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.13 74.8 9.27 76.16 ; + RECT 16.95 74.8 17.09 76.16 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -667,7 +667,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 14.65 74.8 14.79 76.16 ; + RECT 22.93 74.8 23.07 76.16 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -675,7 +675,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 74.8 29.97 76.16 ; + RECT 19.25 74.8 19.39 76.16 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -683,7 +683,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.07 74.8 27.21 76.16 ; + RECT 16.03 74.8 16.17 76.16 ; END END chany_top_in[19] PIN ccff_head[0] @@ -691,7 +691,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 54.25 1.38 54.55 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -699,15 +699,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.11 0 38.25 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 14.65 0 14.79 1.36 ; + LAYER met4 ; + RECT 35.73 0 36.03 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -715,7 +715,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 38.49 0 38.79 1.36 ; + RECT 33.89 0 34.19 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -723,7 +723,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.73 0 13.87 1.36 ; + RECT 24.31 0 24.45 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -731,7 +731,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 0 4.67 1.36 ; + RECT 29.83 0 29.97 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -739,7 +739,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 0 30.89 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -747,7 +747,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -755,7 +755,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 0 39.17 1.36 ; + RECT 21.55 0 21.69 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -763,7 +763,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -771,7 +771,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 0 27.75 1.36 ; + RECT 18.25 0 18.55 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -779,7 +779,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 30.21 0 30.51 1.36 ; + RECT 16.41 0 16.71 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -787,7 +787,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.83 0 29.97 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -795,7 +795,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 30.75 0 30.89 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -803,7 +803,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 31.67 0 31.81 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -811,7 +811,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 43.17 0 43.31 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -819,7 +819,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -827,7 +827,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.67 0 31.81 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -835,7 +835,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -843,7 +843,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 0 40.09 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -851,15 +851,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.79 0 41.93 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_out[19] PIN chany_top_out[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 22.93 74.8 23.07 76.16 ; + LAYER met4 ; + RECT 24.69 74.8 24.99 76.16 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -867,15 +867,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.75 74.8 30.89 76.16 ; + RECT 8.21 74.8 8.35 76.16 ; END END chany_top_out[1] PIN chany_top_out[2] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 32.59 74.8 32.73 76.16 ; + LAYER met4 ; + RECT 22.85 74.8 23.15 76.16 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -883,7 +883,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 74.8 23.99 76.16 ; + RECT 22.01 74.8 22.15 76.16 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -891,7 +891,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 74.8 3.75 76.16 ; + RECT 10.05 74.8 10.19 76.16 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -899,7 +899,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 74.8 20.31 76.16 ; + RECT 24.77 74.8 24.91 76.16 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -907,7 +907,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 74.8 21.23 76.16 ; + RECT 39.49 74.8 39.63 76.16 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -915,7 +915,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 74.8 44.69 76.16 ; + RECT 52.37 74.8 52.51 76.16 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -923,7 +923,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 74.8 43.31 76.16 ; + RECT 56.97 74.8 57.11 76.16 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -931,7 +931,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 74.8 46.53 76.16 ; + RECT 37.65 74.8 37.79 76.16 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -939,7 +939,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 18.33 74.8 18.47 76.16 ; + RECT 5.91 74.8 6.05 76.16 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -947,7 +947,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 74.8 39.17 76.16 ; + RECT 28.91 74.8 29.05 76.16 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -955,7 +955,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 74.8 22.15 76.16 ; + RECT 23.85 74.8 23.99 76.16 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -963,7 +963,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 12.81 74.8 12.95 76.16 ; + RECT 34.43 74.8 34.57 76.16 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -971,7 +971,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 74.8 33.65 76.16 ; + RECT 40.41 74.8 40.55 76.16 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -979,7 +979,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 74.8 41.47 76.16 ; + RECT 44.09 74.8 44.23 76.16 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -987,7 +987,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 74.8 40.09 76.16 ; + RECT 29.83 74.8 29.97 76.16 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -995,7 +995,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 74.8 42.39 76.16 ; + RECT 54.21 74.8 54.35 76.16 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1003,7 +1003,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 74.8 45.61 76.16 ; + RECT 55.13 74.8 55.27 76.16 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1011,15 +1011,15 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.11 74.8 38.25 76.16 ; + RECT 53.29 74.8 53.43 76.16 ; END END chany_top_out[19] PIN right_grid_pin_0_[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 17.41 74.8 17.55 76.16 ; + LAYER met4 ; + RECT 21.93 0 22.23 1.36 ; END END right_grid_pin_0_[0] PIN left_grid_pin_16_[0] @@ -1027,7 +1027,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 31.13 1.38 31.43 ; END END left_grid_pin_16_[0] PIN left_grid_pin_17_[0] @@ -1035,7 +1035,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 28.41 1.38 28.71 ; END END left_grid_pin_17_[0] PIN left_grid_pin_18_[0] @@ -1043,7 +1043,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 27.05 1.38 27.35 ; END END left_grid_pin_18_[0] PIN left_grid_pin_19_[0] @@ -1051,7 +1051,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 32.49 1.38 32.79 ; END END left_grid_pin_19_[0] PIN left_grid_pin_20_[0] @@ -1059,7 +1059,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 12.77 1.38 13.07 ; END END left_grid_pin_20_[0] PIN left_grid_pin_21_[0] @@ -1067,7 +1067,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 4.61 1.38 4.91 ; END END left_grid_pin_21_[0] PIN left_grid_pin_22_[0] @@ -1075,7 +1075,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 25.69 1.38 25.99 ; END END left_grid_pin_22_[0] PIN left_grid_pin_23_[0] @@ -1083,7 +1083,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 24.33 1.38 24.63 ; END END left_grid_pin_23_[0] PIN left_grid_pin_24_[0] @@ -1091,7 +1091,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 5.97 1.38 6.27 ; END END left_grid_pin_24_[0] PIN left_grid_pin_25_[0] @@ -1099,7 +1099,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 8.69 1.38 8.99 ; END END left_grid_pin_25_[0] PIN left_grid_pin_26_[0] @@ -1107,7 +1107,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 7.33 1.38 7.63 ; END END left_grid_pin_26_[0] PIN left_grid_pin_27_[0] @@ -1115,7 +1115,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 29.77 1.38 30.07 ; END END left_grid_pin_27_[0] PIN left_grid_pin_28_[0] @@ -1123,7 +1123,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 50.17 1.38 50.47 ; END END left_grid_pin_28_[0] PIN left_grid_pin_29_[0] @@ -1131,7 +1131,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 52.89 1.38 53.19 ; END END left_grid_pin_29_[0] PIN left_grid_pin_30_[0] @@ -1139,7 +1139,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 48.81 1.38 49.11 ; END END left_grid_pin_30_[0] PIN left_grid_pin_31_[0] @@ -1147,7 +1147,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 51.53 1.38 51.83 ; END END left_grid_pin_31_[0] PIN ccff_tail[0] @@ -1155,7 +1155,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 7.75 0 7.89 1.36 ; END END ccff_tail[0] PIN gfpga_pad_EMBEDDED_IO_SOC_IN[0] @@ -1163,7 +1163,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 38.61 66.24 38.91 ; + RECT 66.7 38.61 68.08 38.91 ; END END gfpga_pad_EMBEDDED_IO_SOC_IN[0] PIN gfpga_pad_EMBEDDED_IO_SOC_OUT[0] @@ -1171,7 +1171,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 8.69 66.24 8.99 ; + RECT 66.7 18.89 68.08 19.19 ; END END gfpga_pad_EMBEDDED_IO_SOC_OUT[0] PIN gfpga_pad_EMBEDDED_IO_SOC_DIR[0] @@ -1179,7 +1179,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 64.86 3.25 66.24 3.55 ; + RECT 66.7 17.53 68.08 17.83 ; END END gfpga_pad_EMBEDDED_IO_SOC_DIR[0] PIN left_width_0_height_0__pin_0_[0] @@ -1187,7 +1187,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 21.93 74.8 22.23 76.16 ; + RECT 20.09 0 20.39 1.36 ; END END left_width_0_height_0__pin_0_[0] PIN left_width_0_height_0__pin_1_upper[0] @@ -1195,7 +1195,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 74.8 7.43 76.16 ; + RECT 14.65 74.8 14.79 76.16 ; END END left_width_0_height_0__pin_1_upper[0] PIN left_width_0_height_0__pin_1_lower[0] @@ -1203,7 +1203,7 @@ MACRO cby_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 0 5.59 1.36 ; + RECT 16.95 0 17.09 1.36 ; END END left_width_0_height_0__pin_1_lower[0] PIN VDD @@ -1211,42 +1211,44 @@ MACRO cby_2__1_ USE POWER ; PORT LAYER met5 ; - RECT 0 36.48 3.2 39.68 ; - RECT 63.04 36.48 66.24 39.68 ; + RECT 0 5.88 3.2 9.08 ; + RECT 64.88 5.88 68.08 9.08 ; + RECT 0 46.68 3.2 49.88 ; + RECT 64.88 46.68 68.08 49.88 ; LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; + RECT 67.6 13.36 68.08 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 65.76 18.8 66.24 19.28 ; + RECT 67.6 18.8 68.08 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 65.76 24.24 66.24 24.72 ; + RECT 67.6 24.24 68.08 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 65.76 29.68 66.24 30.16 ; + RECT 67.6 29.68 68.08 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 65.76 35.12 66.24 35.6 ; + RECT 67.6 35.12 68.08 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 65.76 40.56 66.24 41.04 ; + RECT 67.6 40.56 68.08 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 65.76 46 66.24 46.48 ; + RECT 67.6 46 68.08 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 65.76 51.44 66.24 51.92 ; + RECT 67.6 51.44 68.08 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 65.76 56.88 66.24 57.36 ; + RECT 67.6 56.88 68.08 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 65.76 62.32 66.24 62.8 ; + RECT 67.6 62.32 68.08 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; + RECT 67.6 67.76 68.08 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; + RECT 67.6 73.2 68.08 73.68 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 75.56 11.34 76.16 ; - RECT 40.18 75.56 40.78 76.16 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 11.66 75.56 12.26 76.16 ; + RECT 41.1 75.56 41.7 76.16 ; END END VDD PIN VSS @@ -1254,129 +1256,140 @@ MACRO cby_2__1_ USE GROUND ; PORT LAYER met5 ; - RECT 0 16.08 3.2 19.28 ; - RECT 63.04 16.08 66.24 19.28 ; - RECT 0 56.88 3.2 60.08 ; - RECT 63.04 56.88 66.24 60.08 ; + RECT 0 26.28 3.2 29.48 ; + RECT 64.88 26.28 68.08 29.48 ; + RECT 0 67.08 3.2 70.28 ; + RECT 64.88 67.08 68.08 70.28 ; LAYER met1 ; - RECT 0 0 66.24 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; + RECT 67.6 5.2 68.08 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; + RECT 67.6 10.64 68.08 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 65.76 16.08 66.24 16.56 ; + RECT 67.6 16.08 68.08 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 65.76 21.52 66.24 22 ; + RECT 67.6 21.52 68.08 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 65.76 26.96 66.24 27.44 ; + RECT 67.6 26.96 68.08 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 65.76 32.4 66.24 32.88 ; + RECT 67.6 32.4 68.08 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 65.76 37.84 66.24 38.32 ; + RECT 67.6 37.84 68.08 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 65.76 43.28 66.24 43.76 ; + RECT 67.6 43.28 68.08 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 65.76 48.72 66.24 49.2 ; + RECT 67.6 48.72 68.08 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 65.76 54.16 66.24 54.64 ; + RECT 67.6 54.16 68.08 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 65.76 59.6 66.24 60.08 ; + RECT 67.6 59.6 68.08 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 65.76 65.04 66.24 65.52 ; + RECT 67.6 65.04 68.08 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; - RECT 0 75.92 66.24 76.16 ; + RECT 67.6 70.48 68.08 70.96 ; + RECT 0 75.92 68.08 76.16 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 75.56 26.06 76.16 ; - RECT 54.9 75.56 55.5 76.16 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 75.56 26.98 76.16 ; + RECT 55.82 75.56 56.42 76.16 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 3.15 74.8 3.29 76.16 ; + END + END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 76.075 66.24 76.245 ; - RECT 65.78 73.355 66.24 73.525 ; + RECT 0 76.075 68.08 76.245 ; + RECT 67.16 73.355 68.08 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.32 70.635 66.24 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 62.56 67.915 66.24 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 62.56 65.195 66.24 65.365 ; - RECT 0 65.195 1.84 65.365 ; - RECT 65.32 62.475 66.24 62.645 ; + RECT 67.16 70.635 68.08 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 67.16 67.915 68.08 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 67.16 65.195 68.08 65.365 ; + RECT 0 65.195 3.68 65.365 ; + RECT 67.16 62.475 68.08 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 65.32 59.755 66.24 59.925 ; + RECT 67.16 59.755 68.08 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 65.32 57.035 66.24 57.205 ; + RECT 67.16 57.035 68.08 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 65.32 54.315 66.24 54.485 ; + RECT 67.16 54.315 68.08 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 65.32 51.595 66.24 51.765 ; + RECT 67.16 51.595 68.08 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 65.32 48.875 66.24 49.045 ; + RECT 67.16 48.875 68.08 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 65.32 46.155 66.24 46.325 ; + RECT 67.16 46.155 68.08 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 65.32 43.435 66.24 43.605 ; + RECT 67.16 43.435 68.08 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 65.32 40.715 66.24 40.885 ; + RECT 67.16 40.715 68.08 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 65.32 37.995 66.24 38.165 ; + RECT 67.16 37.995 68.08 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 65.32 35.275 66.24 35.445 ; + RECT 67.16 35.275 68.08 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 65.32 32.555 66.24 32.725 ; + RECT 67.16 32.555 68.08 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 65.32 29.835 66.24 30.005 ; + RECT 67.16 29.835 68.08 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 65.32 27.115 66.24 27.285 ; + RECT 67.16 27.115 68.08 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 65.32 24.395 66.24 24.565 ; + RECT 67.16 24.395 68.08 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 65.32 21.675 66.24 21.845 ; + RECT 67.16 21.675 68.08 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 65.32 18.955 66.24 19.125 ; + RECT 67.16 18.955 68.08 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 65.32 16.235 66.24 16.405 ; + RECT 67.16 16.235 68.08 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; + RECT 67.16 13.515 68.08 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; + RECT 67.16 10.795 68.08 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; + RECT 67.16 5.355 68.08 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met2 ; - RECT 55.06 75.975 55.34 76.345 ; - RECT 25.62 75.975 25.9 76.345 ; - RECT 4.93 74.3 5.19 74.62 ; - RECT 23.33 1.54 23.59 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 75.88 65.96 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.53 0.28 38.53 1.64 37.83 1.64 37.83 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 29.33 0.28 29.33 1.64 28.63 1.64 28.63 0.28 28.41 0.28 28.41 1.64 27.71 1.64 27.71 0.28 27.49 0.28 27.49 1.64 26.79 1.64 26.79 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 9.55 0.28 9.55 1.64 8.85 1.64 8.85 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 5.87 0.28 5.87 1.64 5.17 1.64 5.17 0.28 4.95 0.28 4.95 1.64 4.25 1.64 4.25 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 75.88 3.33 75.88 3.33 74.52 4.03 74.52 4.03 75.88 4.25 75.88 4.25 74.52 4.95 74.52 4.95 75.88 5.17 75.88 5.17 74.52 5.87 74.52 5.87 75.88 6.09 75.88 6.09 74.52 6.79 74.52 6.79 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 17.13 75.88 17.13 74.52 17.83 74.52 17.83 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 26.79 75.88 26.79 74.52 27.49 74.52 27.49 75.88 27.71 75.88 27.71 74.52 28.41 74.52 28.41 75.88 28.63 75.88 28.63 74.52 29.33 74.52 29.33 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 31.39 75.88 31.39 74.52 32.09 74.52 32.09 75.88 32.31 75.88 32.31 74.52 33.01 74.52 33.01 75.88 33.23 75.88 33.23 74.52 33.93 74.52 33.93 75.88 37.83 75.88 37.83 74.52 38.53 74.52 38.53 75.88 38.75 75.88 38.75 74.52 39.45 74.52 39.45 75.88 39.67 75.88 39.67 74.52 40.37 74.52 40.37 75.88 41.05 75.88 41.05 74.52 41.75 74.52 41.75 75.88 41.97 75.88 41.97 74.52 42.67 74.52 42.67 75.88 42.89 75.88 42.89 74.52 43.59 74.52 43.59 75.88 44.27 75.88 44.27 74.52 44.97 74.52 44.97 75.88 45.19 75.88 45.19 74.52 45.89 74.52 45.89 75.88 46.11 75.88 46.11 74.52 46.81 74.52 46.81 75.88 59.45 75.88 59.45 74.52 60.15 74.52 60.15 75.88 60.37 75.88 60.37 74.52 61.07 74.52 61.07 75.88 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met3 ; - POLYGON 55.365 76.325 55.365 76.32 55.58 76.32 55.58 76 55.365 76 55.365 75.995 55.035 75.995 55.035 76 54.82 76 54.82 76.32 55.035 76.32 55.035 76.325 ; - POLYGON 25.925 76.325 25.925 76.32 26.14 76.32 26.14 76 25.925 76 25.925 75.995 25.595 75.995 25.595 76 25.38 76 25.38 76.32 25.595 76.32 25.595 76.325 ; - POLYGON 3.83 41.63 3.83 41.33 1.78 41.33 1.78 41.35 1.23 41.35 1.23 41.63 ; - POLYGON 1.545 4.925 1.545 4.91 19.47 4.91 19.47 4.61 1.545 4.61 1.545 4.595 1.215 4.595 1.215 4.925 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 75.76 65.84 39.31 64.46 39.31 64.46 38.21 65.84 38.21 65.84 9.39 64.46 9.39 64.46 8.29 65.84 8.29 65.84 3.95 64.46 3.95 64.46 2.85 65.84 2.85 65.84 0.4 0.4 0.4 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 75.76 ; + POLYGON 56.285 76.325 56.285 76.32 56.5 76.32 56.5 76 56.285 76 56.285 75.995 55.955 75.995 55.955 76 55.74 76 55.74 76.32 55.955 76.32 55.955 76.325 ; + POLYGON 26.845 76.325 26.845 76.32 27.06 76.32 27.06 76 26.845 76 26.845 75.995 26.515 75.995 26.515 76 26.3 76 26.3 76.32 26.515 76.32 26.515 76.325 ; + POLYGON 3.83 29.39 3.83 29.09 1.99 29.09 1.99 28.41 1.78 28.41 1.78 29.11 1.69 29.11 1.69 29.39 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 75.76 67.68 39.31 66.3 39.31 66.3 38.21 67.68 38.21 67.68 19.59 66.3 19.59 66.3 18.49 67.68 18.49 67.68 18.23 66.3 18.23 66.3 17.13 67.68 17.13 67.68 0.4 0.4 0.4 0.4 4.21 1.78 4.21 1.78 5.31 0.4 5.31 0.4 5.57 1.78 5.57 1.78 6.67 0.4 6.67 0.4 6.93 1.78 6.93 1.78 8.03 0.4 8.03 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 12.37 1.78 12.37 1.78 13.47 0.4 13.47 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 75.76 ; + LAYER met2 ; + RECT 55.98 75.975 56.26 76.345 ; + RECT 26.54 75.975 26.82 76.345 ; + RECT 40.81 74.3 41.07 74.62 ; + RECT 34.83 1.54 35.09 1.86 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 75.88 67.8 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 32.09 0.28 32.09 1.64 31.39 1.64 31.39 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 30.25 0.28 30.25 1.64 29.55 1.64 29.55 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 24.73 0.28 24.73 1.64 24.03 1.64 24.03 0.28 23.81 0.28 23.81 1.64 23.11 1.64 23.11 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 20.13 0.28 20.13 1.64 19.43 1.64 19.43 0.28 19.21 0.28 19.21 1.64 18.51 1.64 18.51 0.28 18.29 0.28 18.29 1.64 17.59 1.64 17.59 0.28 17.37 0.28 17.37 1.64 16.67 1.64 16.67 0.28 16.45 0.28 16.45 1.64 15.75 1.64 15.75 0.28 15.53 0.28 15.53 1.64 14.83 1.64 14.83 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 13.69 0.28 13.69 1.64 12.99 1.64 12.99 0.28 12.77 0.28 12.77 1.64 12.07 1.64 12.07 0.28 11.85 0.28 11.85 1.64 11.15 1.64 11.15 0.28 10.93 0.28 10.93 1.64 10.23 1.64 10.23 0.28 10.01 0.28 10.01 1.64 9.31 1.64 9.31 0.28 8.17 0.28 8.17 1.64 7.47 1.64 7.47 0.28 0.28 0.28 0.28 75.88 2.87 75.88 2.87 74.52 3.57 74.52 3.57 75.88 5.63 75.88 5.63 74.52 6.33 74.52 6.33 75.88 7.01 75.88 7.01 74.52 7.71 74.52 7.71 75.88 7.93 75.88 7.93 74.52 8.63 74.52 8.63 75.88 8.85 75.88 8.85 74.52 9.55 74.52 9.55 75.88 9.77 75.88 9.77 74.52 10.47 74.52 10.47 75.88 10.69 75.88 10.69 74.52 11.39 74.52 11.39 75.88 11.61 75.88 11.61 74.52 12.31 74.52 12.31 75.88 12.53 75.88 12.53 74.52 13.23 74.52 13.23 75.88 13.45 75.88 13.45 74.52 14.15 74.52 14.15 75.88 14.37 75.88 14.37 74.52 15.07 74.52 15.07 75.88 15.75 75.88 15.75 74.52 16.45 74.52 16.45 75.88 16.67 75.88 16.67 74.52 17.37 74.52 17.37 75.88 18.05 75.88 18.05 74.52 18.75 74.52 18.75 75.88 18.97 75.88 18.97 74.52 19.67 74.52 19.67 75.88 19.89 75.88 19.89 74.52 20.59 74.52 20.59 75.88 20.81 75.88 20.81 74.52 21.51 74.52 21.51 75.88 21.73 75.88 21.73 74.52 22.43 74.52 22.43 75.88 22.65 75.88 22.65 74.52 23.35 74.52 23.35 75.88 23.57 75.88 23.57 74.52 24.27 74.52 24.27 75.88 24.49 75.88 24.49 74.52 25.19 74.52 25.19 75.88 25.41 75.88 25.41 74.52 26.11 74.52 26.11 75.88 27.25 75.88 27.25 74.52 27.95 74.52 27.95 75.88 28.63 75.88 28.63 74.52 29.33 74.52 29.33 75.88 29.55 75.88 29.55 74.52 30.25 74.52 30.25 75.88 30.47 75.88 30.47 74.52 31.17 74.52 31.17 75.88 34.15 75.88 34.15 74.52 34.85 74.52 34.85 75.88 37.37 75.88 37.37 74.52 38.07 74.52 38.07 75.88 38.29 75.88 38.29 74.52 38.99 74.52 38.99 75.88 39.21 75.88 39.21 74.52 39.91 74.52 39.91 75.88 40.13 75.88 40.13 74.52 40.83 74.52 40.83 75.88 43.81 75.88 43.81 74.52 44.51 74.52 44.51 75.88 49.33 75.88 49.33 74.52 50.03 74.52 50.03 75.88 50.25 75.88 50.25 74.52 50.95 74.52 50.95 75.88 51.17 75.88 51.17 74.52 51.87 74.52 51.87 75.88 52.09 75.88 52.09 74.52 52.79 74.52 52.79 75.88 53.01 75.88 53.01 74.52 53.71 74.52 53.71 75.88 53.93 75.88 53.93 74.52 54.63 74.52 54.63 75.88 54.85 75.88 54.85 74.52 55.55 74.52 55.55 75.88 56.69 75.88 56.69 74.52 57.39 74.52 57.39 75.88 ; LAYER met4 ; - POLYGON 65.84 75.76 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 39.19 0.4 39.19 1.76 38.09 1.76 38.09 0.4 30.91 0.4 30.91 1.76 29.81 1.76 29.81 0.4 28.15 0.4 28.15 1.76 27.05 1.76 27.05 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 75.76 10.34 75.76 10.34 75.16 11.74 75.16 11.74 75.76 21.53 75.76 21.53 74.4 22.63 74.4 22.63 75.76 25.06 75.76 25.06 75.16 26.46 75.16 26.46 75.76 39.78 75.76 39.78 75.16 41.18 75.16 41.18 75.76 54.5 75.76 54.5 75.16 55.9 75.16 55.9 75.76 ; + POLYGON 67.68 75.76 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 36.43 0.4 36.43 1.76 35.33 1.76 35.33 0.4 34.59 0.4 34.59 1.76 33.49 1.76 33.49 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 22.63 0.4 22.63 1.76 21.53 1.76 21.53 0.4 20.79 0.4 20.79 1.76 19.69 1.76 19.69 0.4 18.95 0.4 18.95 1.76 17.85 1.76 17.85 0.4 17.11 0.4 17.11 1.76 16.01 1.76 16.01 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 75.76 11.26 75.76 11.26 75.16 12.66 75.16 12.66 75.76 22.45 75.76 22.45 74.4 23.55 74.4 23.55 75.76 24.29 75.76 24.29 74.4 25.39 74.4 25.39 75.76 25.98 75.76 25.98 75.16 27.38 75.16 27.38 75.76 40.7 75.76 40.7 75.16 42.1 75.16 42.1 75.76 55.42 75.76 55.42 75.16 56.82 75.16 56.82 75.76 ; LAYER met1 ; - POLYGON 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 65.48 65.8 65.48 64.76 65.96 64.76 65.96 63.08 65.48 63.08 65.48 62.04 65.96 62.04 65.96 60.36 65.48 60.36 65.48 59.32 65.96 59.32 65.96 57.64 65.48 57.64 65.48 56.6 65.96 56.6 65.96 54.92 65.48 54.92 65.48 53.88 65.96 53.88 65.96 52.2 65.48 52.2 65.48 51.16 65.96 51.16 65.96 49.48 65.48 49.48 65.48 48.44 65.96 48.44 65.96 46.76 65.48 46.76 65.48 45.72 65.96 45.72 65.96 44.04 65.48 44.04 65.48 43 65.96 43 65.96 41.32 65.48 41.32 65.48 40.28 65.96 40.28 65.96 38.6 65.48 38.6 65.48 37.56 65.96 37.56 65.96 35.88 65.48 35.88 65.48 34.84 65.96 34.84 65.96 33.16 65.48 33.16 65.48 32.12 65.96 32.12 65.96 30.44 65.48 30.44 65.48 29.4 65.96 29.4 65.96 27.72 65.48 27.72 65.48 26.68 65.96 26.68 65.96 25 65.48 25 65.48 23.96 65.96 23.96 65.96 22.28 65.48 22.28 65.48 21.24 65.96 21.24 65.96 19.56 65.48 19.56 65.48 18.52 65.96 18.52 65.96 16.84 65.48 16.84 65.48 15.8 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; + POLYGON 67.8 75.64 67.8 73.96 67.32 73.96 67.32 72.92 67.8 72.92 67.8 71.24 67.32 71.24 67.32 70.2 67.8 70.2 67.8 68.52 67.32 68.52 67.32 67.48 67.8 67.48 67.8 65.8 67.32 65.8 67.32 64.76 67.8 64.76 67.8 63.08 67.32 63.08 67.32 62.04 67.8 62.04 67.8 60.36 67.32 60.36 67.32 59.32 67.8 59.32 67.8 57.64 67.32 57.64 67.32 56.6 67.8 56.6 67.8 54.92 67.32 54.92 67.32 53.88 67.8 53.88 67.8 52.2 67.32 52.2 67.32 51.16 67.8 51.16 67.8 49.48 67.32 49.48 67.32 48.44 67.8 48.44 67.8 46.76 67.32 46.76 67.32 45.72 67.8 45.72 67.8 44.04 67.32 44.04 67.32 43 67.8 43 67.8 41.32 67.32 41.32 67.32 40.28 67.8 40.28 67.8 38.6 67.32 38.6 67.32 37.56 67.8 37.56 67.8 35.88 67.32 35.88 67.32 34.84 67.8 34.84 67.8 33.16 67.32 33.16 67.32 32.12 67.8 32.12 67.8 30.44 67.32 30.44 67.32 29.4 67.8 29.4 67.8 27.72 67.32 27.72 67.32 26.68 67.8 26.68 67.8 25 67.32 25 67.32 23.96 67.8 23.96 67.8 22.28 67.32 22.28 67.32 21.24 67.8 21.24 67.8 19.56 67.32 19.56 67.32 18.52 67.8 18.52 67.8 16.84 67.32 16.84 67.32 15.8 67.8 15.8 67.8 14.12 67.32 14.12 67.32 13.08 67.8 13.08 67.8 11.4 67.32 11.4 67.32 10.36 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 ; LAYER met5 ; - POLYGON 64.64 74.56 64.64 61.68 61.44 61.68 61.44 55.28 64.64 55.28 64.64 41.28 61.44 41.28 61.44 34.88 64.64 34.88 64.64 20.88 61.44 20.88 61.44 14.48 64.64 14.48 64.64 1.6 1.6 1.6 1.6 14.48 4.8 14.48 4.8 20.88 1.6 20.88 1.6 34.88 4.8 34.88 4.8 41.28 1.6 41.28 1.6 55.28 4.8 55.28 4.8 61.68 1.6 61.68 1.6 74.56 ; + POLYGON 66.48 74.56 66.48 71.88 63.28 71.88 63.28 65.48 66.48 65.48 66.48 51.48 63.28 51.48 63.28 45.08 66.48 45.08 66.48 31.08 63.28 31.08 63.28 24.68 66.48 24.68 66.48 10.68 63.28 10.68 63.28 4.28 66.48 4.28 66.48 1.6 1.6 1.6 1.6 4.28 4.8 4.28 4.8 10.68 1.6 10.68 1.6 24.68 4.8 24.68 4.8 31.08 1.6 31.08 1.6 45.08 4.8 45.08 4.8 51.48 1.6 51.48 1.6 65.48 4.8 65.48 4.8 71.88 1.6 71.88 1.6 74.56 ; LAYER li1 ; - RECT 0.17 0.17 66.07 75.99 ; + RECT 0.17 0.17 67.91 75.99 ; LAYER mcon ; + RECT 67.765 76.075 67.935 76.245 ; + RECT 67.305 76.075 67.475 76.245 ; + RECT 66.845 76.075 67.015 76.245 ; + RECT 66.385 76.075 66.555 76.245 ; RECT 65.925 76.075 66.095 76.245 ; RECT 65.465 76.075 65.635 76.245 ; RECT 65.005 76.075 65.175 76.245 ; @@ -1521,114 +1534,118 @@ MACRO cby_2__1_ RECT 1.065 76.075 1.235 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; + RECT 67.765 73.355 67.935 73.525 ; + RECT 67.305 73.355 67.475 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; + RECT 67.765 70.635 67.935 70.805 ; + RECT 67.305 70.635 67.475 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; + RECT 67.765 67.915 67.935 68.085 ; + RECT 67.305 67.915 67.475 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; + RECT 67.765 65.195 67.935 65.365 ; + RECT 67.305 65.195 67.475 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 65.925 62.475 66.095 62.645 ; - RECT 65.465 62.475 65.635 62.645 ; + RECT 67.765 62.475 67.935 62.645 ; + RECT 67.305 62.475 67.475 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 65.925 59.755 66.095 59.925 ; - RECT 65.465 59.755 65.635 59.925 ; + RECT 67.765 59.755 67.935 59.925 ; + RECT 67.305 59.755 67.475 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 65.925 57.035 66.095 57.205 ; - RECT 65.465 57.035 65.635 57.205 ; + RECT 67.765 57.035 67.935 57.205 ; + RECT 67.305 57.035 67.475 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 65.925 54.315 66.095 54.485 ; - RECT 65.465 54.315 65.635 54.485 ; + RECT 67.765 54.315 67.935 54.485 ; + RECT 67.305 54.315 67.475 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 65.925 51.595 66.095 51.765 ; - RECT 65.465 51.595 65.635 51.765 ; + RECT 67.765 51.595 67.935 51.765 ; + RECT 67.305 51.595 67.475 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 65.925 48.875 66.095 49.045 ; - RECT 65.465 48.875 65.635 49.045 ; + RECT 67.765 48.875 67.935 49.045 ; + RECT 67.305 48.875 67.475 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 65.925 46.155 66.095 46.325 ; - RECT 65.465 46.155 65.635 46.325 ; + RECT 67.765 46.155 67.935 46.325 ; + RECT 67.305 46.155 67.475 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 65.925 43.435 66.095 43.605 ; - RECT 65.465 43.435 65.635 43.605 ; + RECT 67.765 43.435 67.935 43.605 ; + RECT 67.305 43.435 67.475 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 65.925 40.715 66.095 40.885 ; - RECT 65.465 40.715 65.635 40.885 ; + RECT 67.765 40.715 67.935 40.885 ; + RECT 67.305 40.715 67.475 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 65.925 37.995 66.095 38.165 ; - RECT 65.465 37.995 65.635 38.165 ; + RECT 67.765 37.995 67.935 38.165 ; + RECT 67.305 37.995 67.475 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 65.925 35.275 66.095 35.445 ; - RECT 65.465 35.275 65.635 35.445 ; + RECT 67.765 35.275 67.935 35.445 ; + RECT 67.305 35.275 67.475 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 65.925 32.555 66.095 32.725 ; - RECT 65.465 32.555 65.635 32.725 ; + RECT 67.765 32.555 67.935 32.725 ; + RECT 67.305 32.555 67.475 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 65.925 29.835 66.095 30.005 ; - RECT 65.465 29.835 65.635 30.005 ; + RECT 67.765 29.835 67.935 30.005 ; + RECT 67.305 29.835 67.475 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 65.925 27.115 66.095 27.285 ; - RECT 65.465 27.115 65.635 27.285 ; + RECT 67.765 27.115 67.935 27.285 ; + RECT 67.305 27.115 67.475 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 65.925 24.395 66.095 24.565 ; - RECT 65.465 24.395 65.635 24.565 ; + RECT 67.765 24.395 67.935 24.565 ; + RECT 67.305 24.395 67.475 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 65.925 21.675 66.095 21.845 ; - RECT 65.465 21.675 65.635 21.845 ; + RECT 67.765 21.675 67.935 21.845 ; + RECT 67.305 21.675 67.475 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 65.925 18.955 66.095 19.125 ; - RECT 65.465 18.955 65.635 19.125 ; + RECT 67.765 18.955 67.935 19.125 ; + RECT 67.305 18.955 67.475 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; + RECT 67.765 16.235 67.935 16.405 ; + RECT 67.305 16.235 67.475 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; + RECT 67.765 13.515 67.935 13.685 ; + RECT 67.305 13.515 67.475 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 65.925 10.795 66.095 10.965 ; - RECT 65.465 10.795 65.635 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1774,28 +1791,29 @@ MACRO cby_2__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 76.085 55.275 76.235 ; - RECT 25.685 76.085 25.835 76.235 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 76.085 56.195 76.235 ; + RECT 26.605 76.085 26.755 76.235 ; + RECT 53.285 74.385 53.435 74.535 ; + RECT 38.565 74.385 38.715 74.535 ; + RECT 15.105 1.625 15.255 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.28 58.38 1.48 58.58 ; - RECT 1.28 20.3 1.48 20.5 ; - RECT 1.28 14.86 1.48 15.06 ; - RECT 64.76 8.74 64.96 8.94 ; - RECT 64.76 3.3 64.96 3.5 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 1.28 54.3 1.48 54.5 ; + RECT 1.28 48.86 1.48 49.06 ; + RECT 1.74 29.82 1.94 30.02 ; + RECT 1.28 7.38 1.48 7.58 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 76.06 55.3 76.26 ; - RECT 25.66 76.06 25.86 76.26 ; - RECT 1.74 21.66 1.94 21.86 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 76.06 56.22 76.26 ; + RECT 26.58 76.06 26.78 76.26 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 76.16 66.24 76.16 66.24 0 ; + POLYGON 0 0 0 76.16 68.08 76.16 68.08 0 ; END END cby_2__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef index a4cfe9a..6c35862 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 81.6 ; + SIZE 95.68 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 14.19 80.24 14.33 81.6 ; + LAYER met3 ; + RECT 94.3 6.65 95.68 6.95 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 80.24 51.59 81.6 ; + RECT 41.33 96.56 41.47 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 80.24 44.69 81.6 ; + RECT 61.11 96.56 61.25 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 80.24 42.85 81.6 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 80.24 22.15 81.6 ; + RECT 60.19 96.56 60.33 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 80.24 45.61 81.6 ; + RECT 44.55 96.56 44.69 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 80.24 27.67 81.6 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 80.24 29.51 81.6 ; + RECT 18.33 96.56 18.47 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 80.24 23.07 81.6 ; + RECT 40.41 96.56 40.55 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 80.24 23.99 81.6 ; + RECT 39.49 96.56 39.63 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 36.65 80.24 36.95 81.6 ; + RECT 17.33 96.56 17.63 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 38.49 80.24 38.79 81.6 ; + RECT 54.13 96.56 54.43 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 80.24 47.45 81.6 ; + RECT 57.43 96.56 57.57 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 80.24 43.77 81.6 ; + RECT 54.21 96.56 54.35 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 80.24 62.17 81.6 ; + RECT 62.95 96.56 63.09 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 80.24 7.43 81.6 ; + RECT 13.73 96.56 13.87 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 80.24 26.75 81.6 ; + RECT 17.41 96.56 17.55 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 80.24 30.43 81.6 ; + RECT 33.97 96.56 34.11 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 56.89 80.24 57.19 81.6 ; + RECT 63.33 96.56 63.63 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 52.29 80.24 52.59 81.6 ; + RECT 33.89 96.56 34.19 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 80.24 28.59 81.6 ; + RECT 34.89 96.56 35.03 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 80.24 58.03 81.6 ; + RECT 51.45 96.56 51.59 97.92 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -539,7 +539,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 36.57 84.64 36.87 ; + RECT 94.3 76.69 95.68 76.99 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -547,7 +547,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 18.89 84.64 19.19 ; + RECT 94.3 25.69 95.68 25.99 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -555,23 +555,23 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 17.53 84.64 17.83 ; + RECT 94.3 13.45 95.68 13.75 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 81.35 0 81.49 1.36 ; + LAYER met3 ; + RECT 94.3 39.29 95.68 39.59 ; END END chanx_right_in[3] PIN chanx_right_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 82.27 0 82.41 1.36 ; + LAYER met3 ; + RECT 94.3 37.93 95.68 38.23 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -579,7 +579,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 10.73 84.64 11.03 ; + RECT 94.3 40.65 95.68 40.95 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -587,7 +587,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.29 84.64 39.59 ; + RECT 94.3 27.05 95.68 27.35 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -595,7 +595,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 94.3 52.89 95.68 53.19 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -603,15 +603,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 43.37 84.64 43.67 ; + RECT 94.3 75.33 95.68 75.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 80.43 0 80.57 1.36 ; + LAYER met3 ; + RECT 94.3 46.09 95.68 46.39 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -619,7 +619,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 3.93 84.64 4.23 ; + RECT 94.3 44.73 95.68 45.03 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -627,7 +627,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.01 84.64 42.31 ; + RECT 94.3 21.61 95.68 21.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -635,7 +635,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.93 84.64 38.23 ; + RECT 94.3 10.73 95.68 11.03 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -643,7 +643,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 46.09 84.64 46.39 ; + RECT 94.3 70.57 95.68 70.87 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -651,15 +651,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 40.65 84.64 40.95 ; + RECT 94.3 61.73 95.68 62.03 ; END END chanx_right_in[14] PIN chanx_right_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 79.89 0 80.19 1.36 ; + LAYER met3 ; + RECT 94.3 71.93 95.68 72.23 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -667,7 +667,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 25.69 84.64 25.99 ; + RECT 94.3 22.97 95.68 23.27 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -675,7 +675,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 6.65 84.64 6.95 ; + RECT 94.3 9.37 95.68 9.67 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -683,7 +683,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 12.09 84.64 12.39 ; + RECT 94.3 31.13 95.68 31.43 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -691,7 +691,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 13.45 84.64 13.75 ; + RECT 94.3 28.41 95.68 28.71 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_1_[0] @@ -699,7 +699,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 94.3 60.37 95.68 60.67 ; END END right_bottom_grid_pin_1_[0] PIN right_bottom_grid_pin_3_[0] @@ -707,7 +707,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 48.81 84.64 49.11 ; + RECT 94.3 56.97 95.68 57.27 ; END END right_bottom_grid_pin_3_[0] PIN right_bottom_grid_pin_5_[0] @@ -715,7 +715,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 94.3 66.49 95.68 66.79 ; END END right_bottom_grid_pin_5_[0] PIN right_bottom_grid_pin_7_[0] @@ -723,7 +723,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 30.45 84.64 30.75 ; + RECT 94.3 43.37 95.68 43.67 ; END END right_bottom_grid_pin_7_[0] PIN right_bottom_grid_pin_9_[0] @@ -731,7 +731,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 94.3 69.21 95.68 69.51 ; END END right_bottom_grid_pin_9_[0] PIN right_bottom_grid_pin_11_[0] @@ -739,7 +739,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 24.33 84.64 24.63 ; + RECT 94.3 55.61 95.68 55.91 ; END END right_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -747,7 +747,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.05 84.64 27.35 ; + RECT 94.3 12.09 95.68 12.39 ; END END ccff_head[0] PIN chany_top_out[0] @@ -755,7 +755,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 80.24 56.19 81.6 ; + RECT 53.29 96.56 53.43 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -763,7 +763,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 80.24 24.91 81.6 ; + RECT 14.65 96.56 14.79 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -771,15 +771,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 80.24 50.67 81.6 ; + RECT 65.71 96.56 65.85 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 20.09 80.24 20.39 81.6 ; + LAYER met2 ; + RECT 16.49 96.56 16.63 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -787,47 +787,47 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 80.24 49.75 81.6 ; + RECT 64.33 96.56 64.47 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 43.09 80.24 43.39 81.6 ; + LAYER met2 ; + RECT 35.81 96.56 35.95 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 80.24 9.35 81.6 ; + LAYER met2 ; + RECT 38.57 96.56 38.71 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 50.45 80.24 50.75 81.6 ; + LAYER met2 ; + RECT 36.73 96.56 36.87 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 80.24 45.23 81.6 ; + LAYER met2 ; + RECT 15.57 96.56 15.71 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 80.24 5.67 81.6 ; + LAYER met2 ; + RECT 37.65 96.56 37.79 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -835,7 +835,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 80.24 46.53 81.6 ; + RECT 55.13 96.56 55.27 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -843,7 +843,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 48.61 80.24 48.91 81.6 ; + RECT 61.49 96.56 61.79 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -851,7 +851,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 80.24 52.51 81.6 ; + RECT 58.35 96.56 58.49 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -859,7 +859,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 46.77 80.24 47.07 81.6 ; + RECT 39.41 96.56 39.71 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -867,7 +867,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 80.24 29.59 81.6 ; + RECT 15.49 96.56 15.79 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -875,7 +875,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 21.93 80.24 22.23 81.6 ; + RECT 35.73 96.56 36.03 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -883,7 +883,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 80.24 48.83 81.6 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -891,7 +891,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 80.24 27.75 81.6 ; + RECT 59.65 96.56 59.95 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -899,7 +899,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 7.21 80.24 7.51 81.6 ; + RECT 57.81 96.56 58.11 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -907,7 +907,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 80.24 24.07 81.6 ; + RECT 37.57 96.56 37.87 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -915,7 +915,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 60.37 84.64 60.67 ; + RECT 94.3 81.45 95.68 81.75 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -923,7 +923,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 51.53 84.64 51.83 ; + RECT 94.3 65.13 95.68 65.43 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -931,7 +931,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 16.17 84.64 16.47 ; + RECT 94.3 80.09 95.68 80.39 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -939,7 +939,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 8.01 84.64 8.31 ; + RECT 94.3 58.33 95.68 58.63 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -947,7 +947,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 14.81 84.64 15.11 ; + RECT 94.3 24.33 95.68 24.63 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -955,7 +955,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 57.65 84.64 57.95 ; + RECT 94.3 63.77 95.68 64.07 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -963,7 +963,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.29 84.64 56.59 ; + RECT 94.3 78.73 95.68 79.03 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -971,7 +971,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.01 84.64 59.31 ; + RECT 94.3 42.01 95.68 42.31 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -979,7 +979,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 52.89 84.64 53.19 ; + RECT 94.3 54.25 95.68 54.55 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -987,7 +987,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.73 84.64 62.03 ; + RECT 94.3 73.97 95.68 74.27 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -995,7 +995,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 9.37 84.64 9.67 ; + RECT 94.3 47.45 95.68 47.75 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1003,7 +1003,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.17 84.64 50.47 ; + RECT 94.3 82.81 95.68 83.11 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1011,7 +1011,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.93 84.64 55.23 ; + RECT 94.3 32.49 95.68 32.79 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1019,7 +1019,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 35.21 84.64 35.51 ; + RECT 94.3 35.21 95.68 35.51 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1027,7 +1027,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 47.45 84.64 47.75 ; + RECT 94.3 33.85 95.68 34.15 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1035,15 +1035,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 5.29 84.64 5.59 ; + RECT 94.3 51.53 95.68 51.83 ; END END chanx_right_out[15] PIN chanx_right_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 79.51 0 79.65 1.36 ; + LAYER met3 ; + RECT 94.3 48.81 95.68 49.11 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1051,7 +1051,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 33.85 84.64 34.15 ; + RECT 94.3 50.17 95.68 50.47 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1059,7 +1059,7 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.09 84.64 29.39 ; + RECT 94.3 67.85 95.68 68.15 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1067,15 +1067,15 @@ MACRO sb_0__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 32.49 84.64 32.79 ; + RECT 94.3 29.77 95.68 30.07 ; END END chanx_right_out[19] PIN ccff_tail[0] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 11.41 1.38 11.71 ; + LAYER met2 ; + RECT 25.69 0 25.83 1.36 ; END END ccff_tail[0] PIN VDD @@ -1084,45 +1084,53 @@ MACRO sb_0__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; + RECT 95.2 62.32 95.68 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 65.76 67.76 66.24 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 65.76 73.2 66.24 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 65.76 78.64 66.24 79.12 ; + RECT 95.2 78.64 95.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 67.6 89.52 68.08 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 67.6 94.96 68.08 95.44 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 81 11.34 81.6 ; - RECT 40.18 81 40.78 81.6 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 85.26 0 85.86 0.6 ; + RECT 85.26 86.44 85.86 87.04 ; + RECT 11.66 97.32 12.26 97.92 ; + RECT 41.1 97.32 41.7 97.92 ; LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 81.44 10.64 84.64 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 81.44 51.44 84.64 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 92.48 11.32 95.68 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 92.48 52.12 95.68 55.32 ; END END VDD PIN VSS @@ -1130,571 +1138,671 @@ MACRO sb_0__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 84.64 0.24 ; + RECT 0 0 95.68 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; + RECT 95.2 10.64 95.68 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 84.16 16.08 84.64 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; - RECT 0 65.04 84.64 65.52 ; + RECT 95.2 59.6 95.68 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 65.76 70.48 66.24 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 65.76 75.92 66.24 76.4 ; - RECT 0 81.36 66.24 81.6 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; + RECT 0 86.8 95.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 67.6 92.24 68.08 92.72 ; + RECT 0 97.68 68.08 97.92 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 81 26.06 81.6 ; - RECT 54.9 81 55.5 81.6 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 97.32 26.98 97.92 ; + RECT 55.82 97.32 56.42 97.92 ; LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 81.44 31.04 84.64 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 92.48 31.72 95.68 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 92.48 72.52 95.68 75.72 ; END END VSS OBS LAYER li1 ; - RECT 0 81.515 66.24 81.685 ; - RECT 65.32 78.795 66.24 78.965 ; + RECT 0 97.835 68.08 98.005 ; + RECT 67.16 95.115 68.08 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 67.16 92.395 68.08 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 67.16 89.675 68.08 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 65.32 86.955 95.68 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 95.22 84.235 95.68 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 95.22 81.515 95.68 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 94.76 78.795 95.68 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 65.32 76.075 66.24 76.245 ; + RECT 94.76 76.075 95.68 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 65.32 73.355 66.24 73.525 ; + RECT 94.76 73.355 95.68 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 65.78 70.635 66.24 70.805 ; + RECT 94.76 70.635 95.68 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 65.32 67.915 66.24 68.085 ; + RECT 94.76 67.915 95.68 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 63.48 65.195 84.64 65.365 ; + RECT 94.76 65.195 95.68 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 83.72 62.475 84.64 62.645 ; + RECT 94.76 62.475 95.68 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 83.72 59.755 84.64 59.925 ; + RECT 94.76 59.755 95.68 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 83.72 57.035 84.64 57.205 ; + RECT 94.76 57.035 95.68 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 83.72 54.315 84.64 54.485 ; + RECT 94.76 54.315 95.68 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 83.72 51.595 84.64 51.765 ; + RECT 94.76 51.595 95.68 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 83.72 48.875 84.64 49.045 ; + RECT 94.76 48.875 95.68 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 83.72 46.155 84.64 46.325 ; + RECT 94.76 46.155 95.68 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 84.18 43.435 84.64 43.605 ; + RECT 94.76 43.435 95.68 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 80.96 40.715 84.64 40.885 ; + RECT 94.76 40.715 95.68 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 80.96 37.995 84.64 38.165 ; + RECT 94.76 37.995 95.68 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 83.72 35.275 84.64 35.445 ; + RECT 93.84 35.275 95.68 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; + RECT 93.84 32.555 95.68 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 94.76 29.835 95.68 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 83.72 27.115 84.64 27.285 ; + RECT 94.76 27.115 95.68 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 83.72 24.395 84.64 24.565 ; + RECT 95.22 24.395 95.68 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 80.96 21.675 84.64 21.845 ; + RECT 95.22 21.675 95.68 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 80.96 18.955 84.64 19.125 ; + RECT 95.22 18.955 95.68 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 83.72 16.235 84.64 16.405 ; + RECT 94.76 16.235 95.68 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 83.72 13.515 84.64 13.685 ; + RECT 92 13.515 95.68 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; + RECT 92 10.795 95.68 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 95.22 8.075 95.68 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 83.72 5.355 84.64 5.525 ; + RECT 95.22 5.355 95.68 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 83.72 2.635 84.64 2.805 ; + RECT 95.22 2.635 95.68 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 84.64 0.085 ; - LAYER met2 ; - RECT 55.06 81.415 55.34 81.785 ; - RECT 25.62 81.415 25.9 81.785 ; - RECT 44.03 79.74 44.29 80.06 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 81.32 65.96 65 84.36 65 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 0.28 0.28 0.28 81.32 7.01 81.32 7.01 79.96 7.71 79.96 7.71 81.32 13.91 81.32 13.91 79.96 14.61 79.96 14.61 81.32 21.73 81.32 21.73 79.96 22.43 79.96 22.43 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 26.33 81.32 26.33 79.96 27.03 79.96 27.03 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 28.17 81.32 28.17 79.96 28.87 79.96 28.87 81.32 29.09 81.32 29.09 79.96 29.79 79.96 29.79 81.32 30.01 81.32 30.01 79.96 30.71 79.96 30.71 81.32 42.43 81.32 42.43 79.96 43.13 79.96 43.13 81.32 43.35 81.32 43.35 79.96 44.05 79.96 44.05 81.32 44.27 81.32 44.27 79.96 44.97 79.96 44.97 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 48.41 81.32 48.41 79.96 49.11 79.96 49.11 81.32 49.33 81.32 49.33 79.96 50.03 79.96 50.03 81.32 50.25 81.32 50.25 79.96 50.95 79.96 50.95 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 57.61 81.32 57.61 79.96 58.31 79.96 58.31 81.32 61.75 81.32 61.75 79.96 62.45 79.96 62.45 81.32 ; - LAYER met4 ; - POLYGON 65.84 81.2 65.84 64.88 84.24 64.88 84.24 0.4 80.59 0.4 80.59 1.76 79.49 1.76 79.49 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 0.4 0.4 0.4 81.2 4.97 81.2 4.97 79.84 6.07 79.84 6.07 81.2 6.81 81.2 6.81 79.84 7.91 79.84 7.91 81.2 8.65 81.2 8.65 79.84 9.75 79.84 9.75 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 19.69 81.2 19.69 79.84 20.79 79.84 20.79 81.2 21.53 81.2 21.53 79.84 22.63 79.84 22.63 81.2 23.37 81.2 23.37 79.84 24.47 79.84 24.47 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 27.05 81.2 27.05 79.84 28.15 79.84 28.15 81.2 28.89 81.2 28.89 79.84 29.99 79.84 29.99 81.2 36.25 81.2 36.25 79.84 37.35 79.84 37.35 81.2 38.09 81.2 38.09 79.84 39.19 79.84 39.19 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 42.69 81.2 42.69 79.84 43.79 79.84 43.79 81.2 44.53 81.2 44.53 79.84 45.63 79.84 45.63 81.2 46.37 81.2 46.37 79.84 47.47 79.84 47.47 81.2 48.21 81.2 48.21 79.84 49.31 79.84 49.31 81.2 50.05 81.2 50.05 79.84 51.15 79.84 51.15 81.2 51.89 81.2 51.89 79.84 52.99 79.84 52.99 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 56.49 81.2 56.49 79.84 57.59 79.84 57.59 81.2 ; + RECT 0 -0.085 95.68 0.085 ; LAYER met3 ; - POLYGON 55.365 81.765 55.365 81.76 55.58 81.76 55.58 81.44 55.365 81.44 55.365 81.435 55.035 81.435 55.035 81.44 54.82 81.44 54.82 81.76 55.035 81.76 55.035 81.765 ; - POLYGON 25.925 81.765 25.925 81.76 26.14 81.76 26.14 81.44 25.925 81.44 25.925 81.435 25.595 81.435 25.595 81.44 25.38 81.44 25.38 81.76 25.595 81.76 25.595 81.765 ; - POLYGON 83.41 15.79 83.41 15.51 82.86 15.51 82.86 15.49 60.11 15.49 60.11 15.79 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 81.2 65.84 64.88 84.24 64.88 84.24 62.43 82.86 62.43 82.86 61.33 84.24 61.33 84.24 61.07 82.86 61.07 82.86 59.97 84.24 59.97 84.24 59.71 82.86 59.71 82.86 58.61 84.24 58.61 84.24 58.35 82.86 58.35 82.86 57.25 84.24 57.25 84.24 56.99 82.86 56.99 82.86 55.89 84.24 55.89 84.24 55.63 82.86 55.63 82.86 54.53 84.24 54.53 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 38.63 82.86 38.63 82.86 37.53 84.24 37.53 84.24 37.27 82.86 37.27 82.86 36.17 84.24 36.17 84.24 35.91 82.86 35.91 82.86 34.81 84.24 34.81 84.24 34.55 82.86 34.55 82.86 33.45 84.24 33.45 84.24 33.19 82.86 33.19 82.86 32.09 84.24 32.09 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 27.75 82.86 27.75 82.86 26.65 84.24 26.65 84.24 26.39 82.86 26.39 82.86 25.29 84.24 25.29 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 19.59 82.86 19.59 82.86 18.49 84.24 18.49 84.24 18.23 82.86 18.23 82.86 17.13 84.24 17.13 84.24 16.87 82.86 16.87 82.86 15.77 84.24 15.77 84.24 15.51 82.86 15.51 82.86 14.41 84.24 14.41 84.24 14.15 82.86 14.15 82.86 13.05 84.24 13.05 84.24 12.79 82.86 12.79 82.86 11.69 84.24 11.69 84.24 11.43 82.86 11.43 82.86 10.33 84.24 10.33 84.24 10.07 82.86 10.07 82.86 8.97 84.24 8.97 84.24 8.71 82.86 8.71 82.86 7.61 84.24 7.61 84.24 7.35 82.86 7.35 82.86 6.25 84.24 6.25 84.24 5.99 82.86 5.99 82.86 4.89 84.24 4.89 84.24 4.63 82.86 4.63 82.86 3.53 84.24 3.53 84.24 0.4 0.4 0.4 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 81.2 ; + POLYGON 56.285 98.085 56.285 98.08 56.5 98.08 56.5 97.76 56.285 97.76 56.285 97.755 55.955 97.755 55.955 97.76 55.74 97.76 55.74 98.08 55.955 98.08 55.955 98.085 ; + POLYGON 26.845 98.085 26.845 98.08 27.06 98.08 27.06 97.76 26.845 97.76 26.845 97.755 26.515 97.755 26.515 97.76 26.3 97.76 26.3 98.08 26.515 98.08 26.515 98.085 ; + POLYGON 94.45 67.47 94.45 67.19 93.9 67.19 93.9 67.17 79.89 67.17 79.89 67.47 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 97.52 67.68 86.64 95.28 86.64 95.28 83.51 93.9 83.51 93.9 82.41 95.28 82.41 95.28 82.15 93.9 82.15 93.9 81.05 95.28 81.05 95.28 80.79 93.9 80.79 93.9 79.69 95.28 79.69 95.28 79.43 93.9 79.43 93.9 78.33 95.28 78.33 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 72.63 93.9 72.63 93.9 71.53 95.28 71.53 95.28 71.27 93.9 71.27 93.9 70.17 95.28 70.17 95.28 69.91 93.9 69.91 93.9 68.81 95.28 68.81 95.28 68.55 93.9 68.55 93.9 67.45 95.28 67.45 95.28 67.19 93.9 67.19 93.9 66.09 95.28 66.09 95.28 65.83 93.9 65.83 93.9 64.73 95.28 64.73 95.28 64.47 93.9 64.47 93.9 63.37 95.28 63.37 95.28 62.43 93.9 62.43 93.9 61.33 95.28 61.33 95.28 61.07 93.9 61.07 93.9 59.97 95.28 59.97 95.28 59.03 93.9 59.03 93.9 57.93 95.28 57.93 95.28 57.67 93.9 57.67 93.9 56.57 95.28 56.57 95.28 56.31 93.9 56.31 93.9 55.21 95.28 55.21 95.28 54.95 93.9 54.95 93.9 53.85 95.28 53.85 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 52.23 93.9 52.23 93.9 51.13 95.28 51.13 95.28 50.87 93.9 50.87 93.9 49.77 95.28 49.77 95.28 49.51 93.9 49.51 93.9 48.41 95.28 48.41 95.28 48.15 93.9 48.15 93.9 47.05 95.28 47.05 95.28 46.79 93.9 46.79 93.9 45.69 95.28 45.69 95.28 45.43 93.9 45.43 93.9 44.33 95.28 44.33 95.28 44.07 93.9 44.07 93.9 42.97 95.28 42.97 95.28 42.71 93.9 42.71 93.9 41.61 95.28 41.61 95.28 41.35 93.9 41.35 93.9 40.25 95.28 40.25 95.28 39.99 93.9 39.99 93.9 38.89 95.28 38.89 95.28 38.63 93.9 38.63 93.9 37.53 95.28 37.53 95.28 35.91 93.9 35.91 93.9 34.81 95.28 34.81 95.28 34.55 93.9 34.55 93.9 33.45 95.28 33.45 95.28 33.19 93.9 33.19 93.9 32.09 95.28 32.09 95.28 31.83 93.9 31.83 93.9 30.73 95.28 30.73 95.28 30.47 93.9 30.47 93.9 29.37 95.28 29.37 95.28 29.11 93.9 29.11 93.9 28.01 95.28 28.01 95.28 27.75 93.9 27.75 93.9 26.65 95.28 26.65 95.28 26.39 93.9 26.39 93.9 25.29 95.28 25.29 95.28 25.03 93.9 25.03 93.9 23.93 95.28 23.93 95.28 23.67 93.9 23.67 93.9 22.57 95.28 22.57 95.28 22.31 93.9 22.31 93.9 21.21 95.28 21.21 95.28 14.15 93.9 14.15 93.9 13.05 95.28 13.05 95.28 12.79 93.9 12.79 93.9 11.69 95.28 11.69 95.28 11.43 93.9 11.43 93.9 10.33 95.28 10.33 95.28 10.07 93.9 10.07 93.9 8.97 95.28 8.97 95.28 7.35 93.9 7.35 93.9 6.25 95.28 6.25 95.28 0.4 0.4 0.4 0.4 97.52 ; + LAYER met2 ; + RECT 55.98 97.735 56.26 98.105 ; + RECT 26.54 97.735 26.82 98.105 ; + RECT 66.11 96.06 66.37 96.38 ; + RECT 56.91 96.06 57.17 96.38 ; + RECT 52.77 96.06 53.03 96.38 ; + RECT 39.89 96.06 40.15 96.38 ; + RECT 18.73 96.06 18.99 96.38 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 97.64 67.8 86.76 95.4 86.76 95.4 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 0.28 0.28 0.28 97.64 13.45 97.64 13.45 96.28 14.15 96.28 14.15 97.64 14.37 97.64 14.37 96.28 15.07 96.28 15.07 97.64 15.29 97.64 15.29 96.28 15.99 96.28 15.99 97.64 16.21 97.64 16.21 96.28 16.91 96.28 16.91 97.64 17.13 97.64 17.13 96.28 17.83 96.28 17.83 97.64 18.05 97.64 18.05 96.28 18.75 96.28 18.75 97.64 33.69 97.64 33.69 96.28 34.39 96.28 34.39 97.64 34.61 97.64 34.61 96.28 35.31 96.28 35.31 97.64 35.53 97.64 35.53 96.28 36.23 96.28 36.23 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.29 97.64 38.29 96.28 38.99 96.28 38.99 97.64 39.21 97.64 39.21 96.28 39.91 96.28 39.91 97.64 40.13 97.64 40.13 96.28 40.83 96.28 40.83 97.64 41.05 97.64 41.05 96.28 41.75 96.28 41.75 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 ; + LAYER met4 ; + POLYGON 67.68 97.52 67.68 86.64 84.86 86.64 84.86 86.04 86.26 86.04 86.26 86.64 95.28 86.64 95.28 0.4 86.26 0.4 86.26 1 84.86 1 84.86 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 97.52 11.26 97.52 11.26 96.92 12.66 96.92 12.66 97.52 15.09 97.52 15.09 96.16 16.19 96.16 16.19 97.52 16.93 97.52 16.93 96.16 18.03 96.16 18.03 97.52 25.98 97.52 25.98 96.92 27.38 96.92 27.38 97.52 33.49 97.52 33.49 96.16 34.59 96.16 34.59 97.52 35.33 97.52 35.33 96.16 36.43 96.16 36.43 97.52 37.17 97.52 37.17 96.16 38.27 96.16 38.27 97.52 39.01 97.52 39.01 96.16 40.11 96.16 40.11 97.52 40.7 97.52 40.7 96.92 42.1 96.92 42.1 97.52 53.73 97.52 53.73 96.16 54.83 96.16 54.83 97.52 55.42 97.52 55.42 96.92 56.82 96.92 56.82 97.52 57.41 97.52 57.41 96.16 58.51 96.16 58.51 97.52 59.25 97.52 59.25 96.16 60.35 96.16 60.35 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 ; LAYER met5 ; - POLYGON 64.64 80 64.64 63.68 83.04 63.68 83.04 56.24 79.84 56.24 79.84 49.84 83.04 49.84 83.04 35.84 79.84 35.84 79.84 29.44 83.04 29.44 83.04 15.44 79.84 15.44 79.84 9.04 83.04 9.04 83.04 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 80 ; + POLYGON 66.48 96.32 66.48 85.44 94.08 85.44 94.08 77.32 90.88 77.32 90.88 70.92 94.08 70.92 94.08 56.92 90.88 56.92 90.88 50.52 94.08 50.52 94.08 36.52 90.88 36.52 90.88 30.12 94.08 30.12 94.08 16.12 90.88 16.12 90.88 9.72 94.08 9.72 94.08 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 96.32 ; LAYER met1 ; - POLYGON 65.96 81.08 65.96 79.4 65.48 79.4 65.48 78.36 65.96 78.36 65.96 76.68 65.48 76.68 65.48 75.64 65.96 75.64 65.96 73.96 65.48 73.96 65.48 72.92 65.96 72.92 65.96 71.24 65.48 71.24 65.48 70.2 65.96 70.2 65.96 68.52 65.48 68.52 65.48 67.48 65.96 67.48 65.96 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 67.8 97.4 67.8 95.72 67.32 95.72 67.32 94.68 67.8 94.68 67.8 93 67.32 93 67.32 91.96 67.8 91.96 67.8 90.28 67.32 90.28 67.32 89.24 67.8 89.24 67.8 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 94.92 11.4 94.92 10.36 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 66.07 81.43 66.07 65.11 84.47 65.11 84.47 0.17 0.17 0.17 0.17 81.43 ; + POLYGON 67.91 97.75 67.91 86.87 95.51 86.87 95.51 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 25.445 97.835 25.615 98.005 ; + RECT 24.985 97.835 25.155 98.005 ; + RECT 24.525 97.835 24.695 98.005 ; + RECT 24.065 97.835 24.235 98.005 ; + RECT 23.605 97.835 23.775 98.005 ; + RECT 23.145 97.835 23.315 98.005 ; + RECT 22.685 97.835 22.855 98.005 ; + RECT 22.225 97.835 22.395 98.005 ; + RECT 21.765 97.835 21.935 98.005 ; + RECT 21.305 97.835 21.475 98.005 ; + RECT 20.845 97.835 21.015 98.005 ; + RECT 20.385 97.835 20.555 98.005 ; + RECT 19.925 97.835 20.095 98.005 ; + RECT 19.465 97.835 19.635 98.005 ; + RECT 19.005 97.835 19.175 98.005 ; + RECT 18.545 97.835 18.715 98.005 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 67.765 95.115 67.935 95.285 ; + RECT 67.305 95.115 67.475 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 67.765 92.395 67.935 92.565 ; + RECT 67.305 92.395 67.475 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 67.765 89.675 67.935 89.845 ; + RECT 67.305 89.675 67.475 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 94.445 86.955 94.615 87.125 ; + RECT 93.985 86.955 94.155 87.125 ; + RECT 93.525 86.955 93.695 87.125 ; + RECT 93.065 86.955 93.235 87.125 ; + RECT 92.605 86.955 92.775 87.125 ; + RECT 92.145 86.955 92.315 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; + RECT 90.765 86.955 90.935 87.125 ; + RECT 90.305 86.955 90.475 87.125 ; + RECT 89.845 86.955 90.015 87.125 ; + RECT 89.385 86.955 89.555 87.125 ; + RECT 88.925 86.955 89.095 87.125 ; + RECT 88.465 86.955 88.635 87.125 ; + RECT 88.005 86.955 88.175 87.125 ; + RECT 87.545 86.955 87.715 87.125 ; + RECT 87.085 86.955 87.255 87.125 ; + RECT 86.625 86.955 86.795 87.125 ; + RECT 86.165 86.955 86.335 87.125 ; + RECT 85.705 86.955 85.875 87.125 ; + RECT 85.245 86.955 85.415 87.125 ; + RECT 84.785 86.955 84.955 87.125 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 83.405 86.955 83.575 87.125 ; + RECT 82.945 86.955 83.115 87.125 ; + RECT 82.485 86.955 82.655 87.125 ; + RECT 82.025 86.955 82.195 87.125 ; + RECT 81.565 86.955 81.735 87.125 ; + RECT 81.105 86.955 81.275 87.125 ; + RECT 80.645 86.955 80.815 87.125 ; + RECT 80.185 86.955 80.355 87.125 ; + RECT 79.725 86.955 79.895 87.125 ; + RECT 79.265 86.955 79.435 87.125 ; + RECT 78.805 86.955 78.975 87.125 ; + RECT 78.345 86.955 78.515 87.125 ; + RECT 77.885 86.955 78.055 87.125 ; + RECT 77.425 86.955 77.595 87.125 ; + RECT 76.965 86.955 77.135 87.125 ; + RECT 76.505 86.955 76.675 87.125 ; + RECT 76.045 86.955 76.215 87.125 ; + RECT 75.585 86.955 75.755 87.125 ; + RECT 75.125 86.955 75.295 87.125 ; + RECT 74.665 86.955 74.835 87.125 ; + RECT 74.205 86.955 74.375 87.125 ; + RECT 73.745 86.955 73.915 87.125 ; + RECT 73.285 86.955 73.455 87.125 ; + RECT 72.825 86.955 72.995 87.125 ; + RECT 72.365 86.955 72.535 87.125 ; + RECT 71.905 86.955 72.075 87.125 ; + RECT 71.445 86.955 71.615 87.125 ; + RECT 70.985 86.955 71.155 87.125 ; + RECT 70.525 86.955 70.695 87.125 ; + RECT 70.065 86.955 70.235 87.125 ; + RECT 69.605 86.955 69.775 87.125 ; + RECT 69.145 86.955 69.315 87.125 ; + RECT 68.685 86.955 68.855 87.125 ; + RECT 68.225 86.955 68.395 87.125 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 65.925 78.795 66.095 78.965 ; - RECT 65.465 78.795 65.635 78.965 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 65.925 76.075 66.095 76.245 ; - RECT 65.465 76.075 65.635 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 65.925 73.355 66.095 73.525 ; - RECT 65.465 73.355 65.635 73.525 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 65.925 70.635 66.095 70.805 ; - RECT 65.465 70.635 65.635 70.805 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 65.925 67.915 66.095 68.085 ; - RECT 65.465 67.915 65.635 68.085 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; - RECT 83.405 65.195 83.575 65.365 ; - RECT 82.945 65.195 83.115 65.365 ; - RECT 82.485 65.195 82.655 65.365 ; - RECT 82.025 65.195 82.195 65.365 ; - RECT 81.565 65.195 81.735 65.365 ; - RECT 81.105 65.195 81.275 65.365 ; - RECT 80.645 65.195 80.815 65.365 ; - RECT 80.185 65.195 80.355 65.365 ; - RECT 79.725 65.195 79.895 65.365 ; - RECT 79.265 65.195 79.435 65.365 ; - RECT 78.805 65.195 78.975 65.365 ; - RECT 78.345 65.195 78.515 65.365 ; - RECT 77.885 65.195 78.055 65.365 ; - RECT 77.425 65.195 77.595 65.365 ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -1880,28 +1988,31 @@ MACRO sb_0__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 81.525 55.275 81.675 ; - RECT 25.685 81.525 25.835 81.675 ; - RECT 45.465 79.825 45.615 79.975 ; - RECT 23.845 79.825 23.995 79.975 ; - RECT 55.125 65.205 55.275 65.355 ; - RECT 25.685 65.205 25.835 65.355 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 97.845 56.195 97.995 ; + RECT 26.605 97.845 26.755 97.995 ; + RECT 55.125 96.145 55.275 96.295 ; + RECT 44.545 96.145 44.695 96.295 ; + RECT 36.725 96.145 36.875 96.295 ; + RECT 56.045 86.965 56.195 87.115 ; + RECT 26.605 86.965 26.755 87.115 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 81.5 55.3 81.7 ; - RECT 25.66 81.5 25.86 81.7 ; - RECT 82.7 50.22 82.9 50.42 ; - RECT 82.7 10.78 82.9 10.98 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 97.82 56.22 98.02 ; + RECT 26.58 97.82 26.78 98.02 ; + RECT 93.74 61.78 93.94 61.98 ; + RECT 93.74 47.5 93.94 47.7 ; + RECT 94.2 25.74 94.4 25.94 ; + RECT 94.2 12.14 94.4 12.34 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 81.5 55.3 81.7 ; - RECT 25.66 81.5 25.86 81.7 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 97.82 56.22 98.02 ; + RECT 26.58 97.82 26.78 98.02 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 81.6 66.24 81.6 66.24 65.28 84.64 65.28 84.64 0 ; + POLYGON 0 0 0 97.92 68.08 97.92 68.08 87.04 95.68 87.04 95.68 0 ; END END sb_0__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef index ae6b4fc..9bf316b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 97.92 ; + SIZE 95.68 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + LAYER met2 ; + RECT 83.65 10.88 83.79 12.24 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 96.56 51.59 97.92 ; + RECT 41.33 107.44 41.47 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 96.56 44.69 97.92 ; + RECT 61.11 107.44 61.25 108.8 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 96.56 42.85 97.92 ; + RECT 52.37 107.44 52.51 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 96.56 22.15 97.92 ; + RECT 60.19 107.44 60.33 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; + RECT 44.55 107.44 44.69 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 96.56 27.67 97.92 ; + RECT 62.03 107.44 62.17 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 96.56 29.51 97.92 ; + RECT 18.33 107.44 18.47 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 96.56 23.07 97.92 ; + RECT 40.41 107.44 40.55 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 96.56 23.99 97.92 ; + RECT 39.49 107.44 39.63 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 36.65 96.56 36.95 97.92 ; + RECT 17.33 107.44 17.63 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 38.49 96.56 38.79 97.92 ; + RECT 54.13 107.44 54.43 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; + RECT 57.43 107.44 57.57 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 96.56 43.77 97.92 ; + RECT 54.21 107.44 54.35 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; + RECT 62.95 107.44 63.09 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 96.56 7.43 97.92 ; + RECT 13.73 107.44 13.87 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 96.56 26.75 97.92 ; + RECT 17.41 107.44 17.55 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 96.56 30.43 97.92 ; + RECT 33.97 107.44 34.11 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 56.89 96.56 57.19 97.92 ; + RECT 63.33 107.44 63.63 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 52.29 96.56 52.59 97.92 ; + RECT 33.89 107.44 34.19 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 96.56 28.59 97.92 ; + RECT 34.89 107.44 35.03 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 96.56 58.03 97.92 ; + RECT 51.45 107.44 51.59 108.8 ; END END top_left_grid_pin_1_[0] PIN chanx_right_in[0] @@ -539,7 +539,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 34.53 84.64 34.83 ; + RECT 94.3 37.25 95.68 37.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -547,7 +547,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 94.3 71.25 95.68 71.55 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -555,7 +555,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 46.09 84.64 46.39 ; + RECT 94.3 92.33 95.68 92.63 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -563,7 +563,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 94.3 84.85 95.68 85.15 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -571,7 +571,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 68.53 84.64 68.83 ; + RECT 94.3 73.97 95.68 74.27 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -579,7 +579,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 67.17 84.64 67.47 ; + RECT 94.3 76.69 95.68 76.99 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -587,7 +587,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.97 84.64 40.27 ; + RECT 94.3 67.17 95.68 67.47 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -595,7 +595,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.25 84.64 37.55 ; + RECT 94.3 39.97 95.68 40.27 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -603,7 +603,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 41.33 84.64 41.63 ; + RECT 94.3 55.61 95.68 55.91 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -611,7 +611,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.05 84.64 61.35 ; + RECT 94.3 75.33 95.68 75.63 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -619,7 +619,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 94.3 59.69 95.68 59.99 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -627,7 +627,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 55.61 84.64 55.91 ; + RECT 94.3 72.61 95.68 72.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -635,7 +635,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 62.41 84.64 62.71 ; + RECT 94.3 78.05 95.68 78.35 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -643,7 +643,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.05 84.64 27.35 ; + RECT 94.3 35.89 95.68 36.19 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -651,7 +651,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 25.69 84.64 25.99 ; + RECT 94.3 31.81 95.68 32.11 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -659,7 +659,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 28.41 84.64 28.71 ; + RECT 94.3 41.33 95.68 41.63 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -667,7 +667,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 69.89 84.64 70.19 ; + RECT 94.3 89.61 95.68 89.91 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -675,7 +675,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 35.89 84.64 36.19 ; + RECT 94.3 44.05 95.68 44.35 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -683,7 +683,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.97 84.64 57.27 ; + RECT 94.3 80.77 95.68 81.07 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -691,7 +691,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.77 84.64 30.07 ; + RECT 94.3 38.61 95.68 38.91 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_34_[0] @@ -699,47 +699,47 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 79.51 16.32 79.65 17.68 ; + RECT 87.33 10.88 87.47 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 9.37 66.24 9.67 ; + LAYER met2 ; + RECT 88.25 10.88 88.39 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 78.97 16.32 79.27 17.68 ; + LAYER met2 ; + RECT 82.27 10.88 82.41 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 6.65 66.24 6.95 ; + LAYER met2 ; + RECT 85.03 10.88 85.17 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 5.29 66.24 5.59 ; + LAYER met2 ; + RECT 91.01 10.88 91.15 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 8.01 66.24 8.31 ; + LAYER met2 ; + RECT 89.17 10.88 89.31 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -747,7 +747,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 16.32 78.27 17.68 ; + RECT 90.09 10.88 90.23 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -755,7 +755,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 86.41 10.88 86.55 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -771,7 +771,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -779,7 +779,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -787,7 +787,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -795,7 +795,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -803,7 +803,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -811,7 +811,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 19.25 0 19.39 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -819,7 +819,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -827,7 +827,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -835,7 +835,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 18.33 0 18.47 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -843,7 +843,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -851,7 +851,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -859,7 +859,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -867,7 +867,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -875,7 +875,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -883,7 +883,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 13.73 0 13.87 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -891,7 +891,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -899,7 +899,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 0 6.51 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -907,7 +907,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -915,7 +915,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -923,7 +923,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] @@ -931,7 +931,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 73.97 84.64 74.27 ; + RECT 94.3 86.89 95.68 87.19 ; END END ccff_head[0] PIN chany_top_out[0] @@ -939,7 +939,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; + RECT 53.29 107.44 53.43 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -947,7 +947,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 96.56 24.91 97.92 ; + RECT 14.65 107.44 14.79 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -955,15 +955,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; + RECT 65.71 107.44 65.85 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 20.09 96.56 20.39 97.92 ; + LAYER met2 ; + RECT 16.49 107.44 16.63 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -971,47 +971,47 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 96.56 49.75 97.92 ; + RECT 64.33 107.44 64.47 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 43.09 96.56 43.39 97.92 ; + LAYER met2 ; + RECT 35.81 107.44 35.95 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 96.56 9.35 97.92 ; + LAYER met2 ; + RECT 38.57 107.44 38.71 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 50.45 96.56 50.75 97.92 ; + LAYER met2 ; + RECT 36.73 107.44 36.87 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 96.56 45.23 97.92 ; + LAYER met2 ; + RECT 15.57 107.44 15.71 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 96.56 5.67 97.92 ; + LAYER met2 ; + RECT 37.65 107.44 37.79 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1019,7 +1019,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; + RECT 55.13 107.44 55.27 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1027,7 +1027,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 48.61 96.56 48.91 97.92 ; + RECT 61.49 107.44 61.79 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1035,7 +1035,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; + RECT 58.35 107.44 58.49 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1043,7 +1043,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 46.77 96.56 47.07 97.92 ; + RECT 39.41 107.44 39.71 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1051,7 +1051,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 29.29 96.56 29.59 97.92 ; + RECT 15.49 107.44 15.79 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1059,7 +1059,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 21.93 96.56 22.23 97.92 ; + RECT 35.73 107.44 36.03 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1067,7 +1067,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 96.56 48.83 97.92 ; + RECT 59.27 107.44 59.41 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1075,7 +1075,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 27.45 96.56 27.75 97.92 ; + RECT 59.65 107.44 59.95 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1083,7 +1083,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 7.21 96.56 7.51 97.92 ; + RECT 57.81 107.44 58.11 108.8 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1091,7 +1091,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 23.77 96.56 24.07 97.92 ; + RECT 37.57 107.44 37.87 108.8 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1099,7 +1099,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 24.33 84.64 24.63 ; + RECT 94.3 83.49 95.68 83.79 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1107,7 +1107,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 33.17 84.64 33.47 ; + RECT 94.3 90.97 95.68 91.27 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1115,7 +1115,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.69 84.64 42.99 ; + RECT 94.3 48.13 95.68 48.43 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1123,7 +1123,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 52.89 84.64 53.19 ; + RECT 94.3 61.05 95.68 61.35 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1131,7 +1131,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.69 84.64 59.99 ; + RECT 94.3 82.13 95.68 82.43 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1139,7 +1139,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 64.45 84.64 64.75 ; + RECT 94.3 79.41 95.68 79.71 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1147,7 +1147,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.85 84.64 51.15 ; + RECT 94.3 54.25 95.68 54.55 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1155,7 +1155,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 58.33 84.64 58.63 ; + RECT 94.3 64.45 95.68 64.75 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1163,7 +1163,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 76.69 84.64 76.99 ; + RECT 94.3 56.97 95.68 57.27 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1171,7 +1171,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 71.25 84.64 71.55 ; + RECT 94.3 50.85 95.68 51.15 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1179,7 +1179,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 47.45 84.64 47.75 ; + RECT 94.3 49.49 95.68 49.79 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1187,7 +1187,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 49.49 84.64 49.79 ; + RECT 94.3 65.81 95.68 66.11 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1195,7 +1195,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 75.33 84.64 75.63 ; + RECT 94.3 45.41 95.68 45.71 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1203,7 +1203,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 78.05 84.64 78.35 ; + RECT 94.3 88.25 95.68 88.55 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1211,7 +1211,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 31.81 84.64 32.11 ; + RECT 94.3 46.77 95.68 47.07 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1219,7 +1219,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 72.61 84.64 72.91 ; + RECT 94.3 42.69 95.68 42.99 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1227,7 +1227,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 94.3 58.33 95.68 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1235,7 +1235,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 38.61 84.64 38.91 ; + RECT 94.3 52.89 95.68 53.19 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1243,7 +1243,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.25 84.64 54.55 ; + RECT 94.3 62.41 95.68 62.71 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1251,7 +1251,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 65.81 84.64 66.11 ; + RECT 94.3 69.21 95.68 69.51 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1259,7 +1259,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1267,7 +1267,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1275,7 +1275,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1283,7 +1283,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1291,7 +1291,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1299,7 +1299,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 17.41 0 17.55 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1307,7 +1307,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1315,7 +1315,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1323,7 +1323,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1331,7 +1331,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 35.35 0 35.49 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1339,15 +1339,15 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 0 45.23 1.36 ; + LAYER met2 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1355,31 +1355,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; + LAYER met2 ; + RECT 14.65 0 14.79 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; + LAYER met2 ; + RECT 16.49 0 16.63 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; + LAYER met2 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1387,31 +1387,31 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 23.77 0 24.07 1.36 ; + LAYER met2 ; + RECT 15.57 0 15.71 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; + LAYER met2 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1419,7 +1419,7 @@ MACRO sb_0__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END ccff_tail[0] PIN VDD @@ -1428,51 +1428,57 @@ MACRO sb_0__1_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; + RECT 95.2 62.32 95.68 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; + RECT 95.2 78.64 95.68 79.12 ; RECT 0 84.08 0.48 84.56 ; - RECT 65.76 84.08 66.24 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; RECT 0 89.52 0.48 90 ; - RECT 65.76 89.52 66.24 90 ; + RECT 95.2 89.52 95.68 90 ; RECT 0 94.96 0.48 95.44 ; - RECT 65.76 94.96 66.24 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; + RECT 0 100.4 0.48 100.88 ; + RECT 67.6 100.4 68.08 100.88 ; + RECT 0 105.84 0.48 106.32 ; + RECT 67.6 105.84 68.08 106.32 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 97.32 11.34 97.92 ; - RECT 40.18 97.32 40.78 97.92 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 85.26 10.88 85.86 11.48 ; + RECT 85.26 97.32 85.86 97.92 ; + RECT 11.66 108.2 12.26 108.8 ; + RECT 41.1 108.2 41.7 108.8 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 81.44 26.96 84.64 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 81.44 67.76 84.64 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 92.48 22.2 95.68 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 92.48 63 95.68 66.2 ; END END VDD PIN VSS @@ -1480,152 +1486,398 @@ MACRO sb_0__1_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 66.24 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 84.64 16.56 ; + RECT 67.6 5.2 68.08 5.68 ; + RECT 0 10.64 95.68 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; + RECT 95.2 59.6 95.68 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 84.16 65.04 84.64 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 0 81.36 84.64 81.84 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; RECT 0 86.8 0.48 87.28 ; - RECT 65.76 86.8 66.24 87.28 ; + RECT 95.2 86.8 95.68 87.28 ; RECT 0 92.24 0.48 92.72 ; - RECT 65.76 92.24 66.24 92.72 ; - RECT 0 97.68 66.24 97.92 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 0 97.68 95.68 98.16 ; + RECT 0 103.12 0.48 103.6 ; + RECT 67.6 103.12 68.08 103.6 ; + RECT 0 108.56 68.08 108.8 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 97.32 26.06 97.92 ; - RECT 54.9 97.32 55.5 97.92 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 108.2 26.98 108.8 ; + RECT 55.82 108.2 56.42 108.8 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 81.44 47.36 84.64 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 92.48 42.6 95.68 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 92.48 83.4 95.68 86.6 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 75.37 96.56 75.51 97.92 ; + END + END prog_clk__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 97.835 66.24 98.005 ; - RECT 65.78 95.115 66.24 95.285 ; + RECT 0 108.715 68.08 108.885 ; + RECT 67.16 105.995 68.08 106.165 ; + RECT 0 105.995 3.68 106.165 ; + RECT 67.16 103.275 68.08 103.445 ; + RECT 0 103.275 3.68 103.445 ; + RECT 67.16 100.555 68.08 100.725 ; + RECT 0 100.555 3.68 100.725 ; + RECT 65.32 97.835 95.68 98.005 ; + RECT 0 97.835 3.68 98.005 ; + RECT 95.22 95.115 95.68 95.285 ; RECT 0 95.115 3.68 95.285 ; - RECT 64.4 92.395 66.24 92.565 ; - RECT 0 92.395 1.84 92.565 ; - RECT 64.4 89.675 66.24 89.845 ; + RECT 95.22 92.395 95.68 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 95.22 89.675 95.68 89.845 ; RECT 0 89.675 3.68 89.845 ; - RECT 65.32 86.955 66.24 87.125 ; + RECT 94.76 86.955 95.68 87.125 ; RECT 0 86.955 3.68 87.125 ; - RECT 65.32 84.235 66.24 84.405 ; + RECT 94.76 84.235 95.68 84.405 ; RECT 0 84.235 3.68 84.405 ; - RECT 65.32 81.515 84.64 81.685 ; + RECT 94.76 81.515 95.68 81.685 ; RECT 0 81.515 3.68 81.685 ; - RECT 84.18 78.795 84.64 78.965 ; + RECT 94.76 78.795 95.68 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 83.72 76.075 84.64 76.245 ; + RECT 94.76 76.075 95.68 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 83.72 73.355 84.64 73.525 ; + RECT 94.76 73.355 95.68 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 83.72 70.635 84.64 70.805 ; + RECT 94.76 70.635 95.68 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 83.72 67.915 84.64 68.085 ; + RECT 95.22 67.915 95.68 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 83.72 65.195 84.64 65.365 ; + RECT 94.76 65.195 95.68 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 82.8 62.475 84.64 62.645 ; + RECT 94.76 62.475 95.68 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 82.8 59.755 84.64 59.925 ; + RECT 94.76 59.755 95.68 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 83.72 57.035 84.64 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 83.72 54.315 84.64 54.485 ; + RECT 94.76 57.035 95.68 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 94.76 54.315 95.68 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 83.72 51.595 84.64 51.765 ; + RECT 94.76 51.595 95.68 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 84.18 48.875 84.64 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 83.72 46.155 84.64 46.325 ; + RECT 94.76 48.875 95.68 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 94.76 46.155 95.68 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 83.72 43.435 84.64 43.605 ; + RECT 94.76 43.435 95.68 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 84.18 40.715 84.64 40.885 ; + RECT 94.76 40.715 95.68 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 83.72 37.995 84.64 38.165 ; + RECT 95.22 37.995 95.68 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 83.72 35.275 84.64 35.445 ; - RECT 0 35.275 1.84 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 95.22 35.275 95.68 35.445 ; + RECT 0 35.275 3.68 35.445 ; + RECT 95.22 32.555 95.68 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 95.22 29.835 95.68 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 83.72 27.115 84.64 27.285 ; + RECT 95.22 27.115 95.68 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 83.72 24.395 84.64 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 83.72 21.675 84.64 21.845 ; + RECT 92 24.395 95.68 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 92 21.675 95.68 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 84.18 18.955 84.64 19.125 ; + RECT 92 18.955 95.68 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 63.02 16.235 84.64 16.405 ; + RECT 92 16.235 95.68 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; + RECT 94.76 13.515 95.68 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 65.32 10.795 66.24 10.965 ; - RECT 0 10.795 1.84 10.965 ; - RECT 65.32 8.075 66.24 8.245 ; + RECT 65.32 10.795 95.68 10.965 ; + RECT 0 10.795 3.68 10.965 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; + RECT 67.16 5.355 68.08 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; - LAYER met3 ; - POLYGON 55.365 98.085 55.365 98.08 55.58 98.08 55.58 97.76 55.365 97.76 55.365 97.755 55.035 97.755 55.035 97.76 54.82 97.76 54.82 98.08 55.035 98.08 55.035 98.085 ; - POLYGON 25.925 98.085 25.925 98.08 26.14 98.08 26.14 97.76 25.925 97.76 25.925 97.755 25.595 97.755 25.595 97.76 25.38 97.76 25.38 98.08 25.595 98.08 25.595 98.085 ; - POLYGON 84.33 66.79 84.33 66.51 82.86 66.51 82.86 66.49 81.73 66.49 81.73 66.79 ; - POLYGON 83.41 26.67 83.41 26.39 82.86 26.39 82.86 26.37 51.83 26.37 51.83 26.67 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 65.84 97.52 65.84 81.2 84.24 81.2 84.24 78.75 82.86 78.75 82.86 77.65 84.24 77.65 84.24 77.39 82.86 77.39 82.86 76.29 84.24 76.29 84.24 76.03 82.86 76.03 82.86 74.93 84.24 74.93 84.24 74.67 82.86 74.67 82.86 73.57 84.24 73.57 84.24 73.31 82.86 73.31 82.86 72.21 84.24 72.21 84.24 71.95 82.86 71.95 82.86 70.85 84.24 70.85 84.24 70.59 82.86 70.59 82.86 69.49 84.24 69.49 84.24 69.23 82.86 69.23 82.86 68.13 84.24 68.13 84.24 67.87 82.86 67.87 82.86 66.77 84.24 66.77 84.24 66.51 82.86 66.51 82.86 65.41 84.24 65.41 84.24 65.15 82.86 65.15 82.86 64.05 84.24 64.05 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 60.39 82.86 60.39 82.86 59.29 84.24 59.29 84.24 59.03 82.86 59.03 82.86 57.93 84.24 57.93 84.24 57.67 82.86 57.67 82.86 56.57 84.24 56.57 84.24 56.31 82.86 56.31 82.86 55.21 84.24 55.21 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 51.55 82.86 51.55 82.86 50.45 84.24 50.45 84.24 50.19 82.86 50.19 82.86 49.09 84.24 49.09 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 43.39 82.86 43.39 82.86 42.29 84.24 42.29 84.24 42.03 82.86 42.03 82.86 40.93 84.24 40.93 84.24 40.67 82.86 40.67 82.86 39.57 84.24 39.57 84.24 39.31 82.86 39.31 82.86 38.21 84.24 38.21 84.24 37.95 82.86 37.95 82.86 36.85 84.24 36.85 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 30.47 82.86 30.47 82.86 29.37 84.24 29.37 84.24 29.11 82.86 29.11 82.86 28.01 84.24 28.01 84.24 27.75 82.86 27.75 82.86 26.65 84.24 26.65 84.24 26.39 82.86 26.39 82.86 25.29 84.24 25.29 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 10.07 64.46 10.07 64.46 8.97 65.84 8.97 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 0.4 0.4 0.4 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 97.52 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 55.06 97.735 55.34 98.105 ; - RECT 25.62 97.735 25.9 98.105 ; - RECT 44.95 96.06 45.21 96.38 ; + RECT 55.98 108.615 56.26 108.985 ; + RECT 26.54 108.615 26.82 108.985 ; + RECT 58.75 106.94 59.01 107.26 ; + RECT 51.85 106.94 52.11 107.26 ; + RECT 64.73 1.54 64.99 1.86 ; + RECT 56.91 1.54 57.17 1.86 ; RECT 48.63 1.54 48.89 1.86 ; - RECT 30.69 1.54 30.95 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 65.96 97.64 65.96 81.32 84.36 81.32 84.36 16.6 79.93 16.6 79.93 17.96 79.23 17.96 79.23 16.6 78.55 16.6 78.55 17.96 77.85 17.96 77.85 16.6 65.96 16.6 65.96 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 21.73 97.64 21.73 96.28 22.43 96.28 22.43 97.64 22.65 97.64 22.65 96.28 23.35 96.28 23.35 97.64 23.57 97.64 23.57 96.28 24.27 96.28 24.27 97.64 24.49 97.64 24.49 96.28 25.19 96.28 25.19 97.64 26.33 97.64 26.33 96.28 27.03 96.28 27.03 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 30.01 97.64 30.01 96.28 30.71 96.28 30.71 97.64 42.43 97.64 42.43 96.28 43.13 96.28 43.13 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 48.41 97.64 48.41 96.28 49.11 96.28 49.11 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 57.61 97.64 57.61 96.28 58.31 96.28 58.31 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 67.8 108.52 67.8 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 95.4 97.64 95.4 11.16 91.43 11.16 91.43 12.52 90.73 12.52 90.73 11.16 90.51 11.16 90.51 12.52 89.81 12.52 89.81 11.16 89.59 11.16 89.59 12.52 88.89 12.52 88.89 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.83 11.16 86.83 12.52 86.13 12.52 86.13 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 84.07 11.16 84.07 12.52 83.37 12.52 83.37 11.16 82.69 11.16 82.69 12.52 81.99 12.52 81.99 11.16 67.8 11.16 67.8 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 0.28 0.28 0.28 108.52 13.45 108.52 13.45 107.16 14.15 107.16 14.15 108.52 14.37 108.52 14.37 107.16 15.07 107.16 15.07 108.52 15.29 108.52 15.29 107.16 15.99 107.16 15.99 108.52 16.21 108.52 16.21 107.16 16.91 107.16 16.91 108.52 17.13 108.52 17.13 107.16 17.83 107.16 17.83 108.52 18.05 108.52 18.05 107.16 18.75 107.16 18.75 108.52 33.69 108.52 33.69 107.16 34.39 107.16 34.39 108.52 34.61 108.52 34.61 107.16 35.31 107.16 35.31 108.52 35.53 108.52 35.53 107.16 36.23 107.16 36.23 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 37.37 108.52 37.37 107.16 38.07 107.16 38.07 108.52 38.29 108.52 38.29 107.16 38.99 107.16 38.99 108.52 39.21 108.52 39.21 107.16 39.91 107.16 39.91 108.52 40.13 108.52 40.13 107.16 40.83 107.16 40.83 108.52 41.05 108.52 41.05 107.16 41.75 107.16 41.75 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 51.17 108.52 51.17 107.16 51.87 107.16 51.87 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 53.93 108.52 53.93 107.16 54.63 107.16 54.63 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 64.05 108.52 64.05 107.16 64.75 107.16 64.75 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 ; LAYER met4 ; - POLYGON 65.84 97.52 65.84 81.2 84.24 81.2 84.24 16.72 79.67 16.72 79.67 18.08 78.57 18.08 78.57 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 97.52 4.97 97.52 4.97 96.16 6.07 96.16 6.07 97.52 6.81 97.52 6.81 96.16 7.91 96.16 7.91 97.52 8.65 97.52 8.65 96.16 9.75 96.16 9.75 97.52 10.34 97.52 10.34 96.92 11.74 96.92 11.74 97.52 19.69 97.52 19.69 96.16 20.79 96.16 20.79 97.52 21.53 97.52 21.53 96.16 22.63 96.16 22.63 97.52 23.37 97.52 23.37 96.16 24.47 96.16 24.47 97.52 25.06 97.52 25.06 96.92 26.46 96.92 26.46 97.52 27.05 97.52 27.05 96.16 28.15 96.16 28.15 97.52 28.89 97.52 28.89 96.16 29.99 96.16 29.99 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 38.09 97.52 38.09 96.16 39.19 96.16 39.19 97.52 39.78 97.52 39.78 96.92 41.18 96.92 41.18 97.52 42.69 97.52 42.69 96.16 43.79 96.16 43.79 97.52 44.53 97.52 44.53 96.16 45.63 96.16 45.63 97.52 46.37 97.52 46.37 96.16 47.47 96.16 47.47 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 50.05 97.52 50.05 96.16 51.15 96.16 51.15 97.52 51.89 97.52 51.89 96.16 52.99 96.16 52.99 97.52 54.5 97.52 54.5 96.92 55.9 96.92 55.9 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 ; + POLYGON 67.68 108.4 67.68 97.52 84.86 97.52 84.86 96.92 86.26 96.92 86.26 97.52 95.28 97.52 95.28 11.28 86.26 11.28 86.26 11.88 84.86 11.88 84.86 11.28 67.68 11.28 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 108.4 11.26 108.4 11.26 107.8 12.66 107.8 12.66 108.4 15.09 108.4 15.09 107.04 16.19 107.04 16.19 108.4 16.93 108.4 16.93 107.04 18.03 107.04 18.03 108.4 25.98 108.4 25.98 107.8 27.38 107.8 27.38 108.4 33.49 108.4 33.49 107.04 34.59 107.04 34.59 108.4 35.33 108.4 35.33 107.04 36.43 107.04 36.43 108.4 37.17 108.4 37.17 107.04 38.27 107.04 38.27 108.4 39.01 108.4 39.01 107.04 40.11 107.04 40.11 108.4 40.7 108.4 40.7 107.8 42.1 107.8 42.1 108.4 53.73 108.4 53.73 107.04 54.83 107.04 54.83 108.4 55.42 108.4 55.42 107.8 56.82 107.8 56.82 108.4 57.41 108.4 57.41 107.04 58.51 107.04 58.51 108.4 59.25 108.4 59.25 107.04 60.35 107.04 60.35 108.4 61.09 108.4 61.09 107.04 62.19 107.04 62.19 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 ; + LAYER met3 ; + POLYGON 56.285 108.965 56.285 108.96 56.5 108.96 56.5 108.64 56.285 108.64 56.285 108.635 55.955 108.635 55.955 108.64 55.74 108.64 55.74 108.96 55.955 108.96 55.955 108.965 ; + POLYGON 26.845 108.965 26.845 108.96 27.06 108.96 27.06 108.64 26.845 108.64 26.845 108.635 26.515 108.635 26.515 108.64 26.3 108.64 26.3 108.96 26.515 108.96 26.515 108.965 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 67.68 108.4 67.68 97.52 95.28 97.52 95.28 93.03 93.9 93.03 93.9 91.93 95.28 91.93 95.28 91.67 93.9 91.67 93.9 90.57 95.28 90.57 95.28 90.31 93.9 90.31 93.9 89.21 95.28 89.21 95.28 88.95 93.9 88.95 93.9 87.85 95.28 87.85 95.28 87.59 93.9 87.59 93.9 86.49 95.28 86.49 95.28 85.55 93.9 85.55 93.9 84.45 95.28 84.45 95.28 84.19 93.9 84.19 93.9 83.09 95.28 83.09 95.28 82.83 93.9 82.83 93.9 81.73 95.28 81.73 95.28 81.47 93.9 81.47 93.9 80.37 95.28 80.37 95.28 80.11 93.9 80.11 93.9 79.01 95.28 79.01 95.28 78.75 93.9 78.75 93.9 77.65 95.28 77.65 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 73.31 93.9 73.31 93.9 72.21 95.28 72.21 95.28 71.95 93.9 71.95 93.9 70.85 95.28 70.85 95.28 69.91 93.9 69.91 93.9 68.81 95.28 68.81 95.28 67.87 93.9 67.87 93.9 66.77 95.28 66.77 95.28 66.51 93.9 66.51 93.9 65.41 95.28 65.41 95.28 65.15 93.9 65.15 93.9 64.05 95.28 64.05 95.28 63.11 93.9 63.11 93.9 62.01 95.28 62.01 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 60.39 93.9 60.39 93.9 59.29 95.28 59.29 95.28 59.03 93.9 59.03 93.9 57.93 95.28 57.93 95.28 57.67 93.9 57.67 93.9 56.57 95.28 56.57 95.28 56.31 93.9 56.31 93.9 55.21 95.28 55.21 95.28 54.95 93.9 54.95 93.9 53.85 95.28 53.85 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 51.55 93.9 51.55 93.9 50.45 95.28 50.45 95.28 50.19 93.9 50.19 93.9 49.09 95.28 49.09 95.28 48.83 93.9 48.83 93.9 47.73 95.28 47.73 95.28 47.47 93.9 47.47 93.9 46.37 95.28 46.37 95.28 46.11 93.9 46.11 93.9 45.01 95.28 45.01 95.28 44.75 93.9 44.75 93.9 43.65 95.28 43.65 95.28 43.39 93.9 43.39 93.9 42.29 95.28 42.29 95.28 42.03 93.9 42.03 93.9 40.93 95.28 40.93 95.28 40.67 93.9 40.67 93.9 39.57 95.28 39.57 95.28 39.31 93.9 39.31 93.9 38.21 95.28 38.21 95.28 37.95 93.9 37.95 93.9 36.85 95.28 36.85 95.28 36.59 93.9 36.59 93.9 35.49 95.28 35.49 95.28 32.51 93.9 32.51 93.9 31.41 95.28 31.41 95.28 11.28 67.68 11.28 67.68 0.4 0.4 0.4 0.4 108.4 ; LAYER met5 ; - POLYGON 64.64 96.32 64.64 80 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 17.92 64.64 17.92 64.64 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 96.32 ; + POLYGON 66.48 107.2 66.48 96.32 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 12.48 66.48 12.48 66.48 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 107.2 ; LAYER met1 ; - POLYGON 65.96 97.4 65.96 95.72 65.48 95.72 65.48 94.68 65.96 94.68 65.96 93 65.48 93 65.48 91.96 65.96 91.96 65.96 90.28 65.48 90.28 65.48 89.24 65.96 89.24 65.96 87.56 65.48 87.56 65.48 86.52 65.96 86.52 65.96 84.84 65.48 84.84 65.48 83.8 65.96 83.8 65.96 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 ; + POLYGON 67.8 108.28 67.8 106.6 67.32 106.6 67.32 105.56 67.8 105.56 67.8 103.88 67.32 103.88 67.32 102.84 67.8 102.84 67.8 101.16 67.32 101.16 67.32 100.12 67.8 100.12 67.8 98.44 0.28 98.44 0.28 100.12 0.76 100.12 0.76 101.16 0.28 101.16 0.28 102.84 0.76 102.84 0.76 103.88 0.28 103.88 0.28 105.56 0.76 105.56 0.76 106.6 0.28 106.6 0.28 108.28 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; LAYER li1 ; - POLYGON 66.07 97.75 66.07 81.43 84.47 81.43 84.47 16.49 66.07 16.49 66.07 0.17 0.17 0.17 0.17 97.75 ; + POLYGON 67.91 108.63 67.91 97.75 95.51 97.75 95.51 11.05 67.91 11.05 67.91 0.17 0.17 0.17 0.17 108.63 ; LAYER mcon ; + RECT 67.765 108.715 67.935 108.885 ; + RECT 67.305 108.715 67.475 108.885 ; + RECT 66.845 108.715 67.015 108.885 ; + RECT 66.385 108.715 66.555 108.885 ; + RECT 65.925 108.715 66.095 108.885 ; + RECT 65.465 108.715 65.635 108.885 ; + RECT 65.005 108.715 65.175 108.885 ; + RECT 64.545 108.715 64.715 108.885 ; + RECT 64.085 108.715 64.255 108.885 ; + RECT 63.625 108.715 63.795 108.885 ; + RECT 63.165 108.715 63.335 108.885 ; + RECT 62.705 108.715 62.875 108.885 ; + RECT 62.245 108.715 62.415 108.885 ; + RECT 61.785 108.715 61.955 108.885 ; + RECT 61.325 108.715 61.495 108.885 ; + RECT 60.865 108.715 61.035 108.885 ; + RECT 60.405 108.715 60.575 108.885 ; + RECT 59.945 108.715 60.115 108.885 ; + RECT 59.485 108.715 59.655 108.885 ; + RECT 59.025 108.715 59.195 108.885 ; + RECT 58.565 108.715 58.735 108.885 ; + RECT 58.105 108.715 58.275 108.885 ; + RECT 57.645 108.715 57.815 108.885 ; + RECT 57.185 108.715 57.355 108.885 ; + RECT 56.725 108.715 56.895 108.885 ; + RECT 56.265 108.715 56.435 108.885 ; + RECT 55.805 108.715 55.975 108.885 ; + RECT 55.345 108.715 55.515 108.885 ; + RECT 54.885 108.715 55.055 108.885 ; + RECT 54.425 108.715 54.595 108.885 ; + RECT 53.965 108.715 54.135 108.885 ; + RECT 53.505 108.715 53.675 108.885 ; + RECT 53.045 108.715 53.215 108.885 ; + RECT 52.585 108.715 52.755 108.885 ; + RECT 52.125 108.715 52.295 108.885 ; + RECT 51.665 108.715 51.835 108.885 ; + RECT 51.205 108.715 51.375 108.885 ; + RECT 50.745 108.715 50.915 108.885 ; + RECT 50.285 108.715 50.455 108.885 ; + RECT 49.825 108.715 49.995 108.885 ; + RECT 49.365 108.715 49.535 108.885 ; + RECT 48.905 108.715 49.075 108.885 ; + RECT 48.445 108.715 48.615 108.885 ; + RECT 47.985 108.715 48.155 108.885 ; + RECT 47.525 108.715 47.695 108.885 ; + RECT 47.065 108.715 47.235 108.885 ; + RECT 46.605 108.715 46.775 108.885 ; + RECT 46.145 108.715 46.315 108.885 ; + RECT 45.685 108.715 45.855 108.885 ; + RECT 45.225 108.715 45.395 108.885 ; + RECT 44.765 108.715 44.935 108.885 ; + RECT 44.305 108.715 44.475 108.885 ; + RECT 43.845 108.715 44.015 108.885 ; + RECT 43.385 108.715 43.555 108.885 ; + RECT 42.925 108.715 43.095 108.885 ; + RECT 42.465 108.715 42.635 108.885 ; + RECT 42.005 108.715 42.175 108.885 ; + RECT 41.545 108.715 41.715 108.885 ; + RECT 41.085 108.715 41.255 108.885 ; + RECT 40.625 108.715 40.795 108.885 ; + RECT 40.165 108.715 40.335 108.885 ; + RECT 39.705 108.715 39.875 108.885 ; + RECT 39.245 108.715 39.415 108.885 ; + RECT 38.785 108.715 38.955 108.885 ; + RECT 38.325 108.715 38.495 108.885 ; + RECT 37.865 108.715 38.035 108.885 ; + RECT 37.405 108.715 37.575 108.885 ; + RECT 36.945 108.715 37.115 108.885 ; + RECT 36.485 108.715 36.655 108.885 ; + RECT 36.025 108.715 36.195 108.885 ; + RECT 35.565 108.715 35.735 108.885 ; + RECT 35.105 108.715 35.275 108.885 ; + RECT 34.645 108.715 34.815 108.885 ; + RECT 34.185 108.715 34.355 108.885 ; + RECT 33.725 108.715 33.895 108.885 ; + RECT 33.265 108.715 33.435 108.885 ; + RECT 32.805 108.715 32.975 108.885 ; + RECT 32.345 108.715 32.515 108.885 ; + RECT 31.885 108.715 32.055 108.885 ; + RECT 31.425 108.715 31.595 108.885 ; + RECT 30.965 108.715 31.135 108.885 ; + RECT 30.505 108.715 30.675 108.885 ; + RECT 30.045 108.715 30.215 108.885 ; + RECT 29.585 108.715 29.755 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 28.205 108.715 28.375 108.885 ; + RECT 27.745 108.715 27.915 108.885 ; + RECT 27.285 108.715 27.455 108.885 ; + RECT 26.825 108.715 26.995 108.885 ; + RECT 26.365 108.715 26.535 108.885 ; + RECT 25.905 108.715 26.075 108.885 ; + RECT 25.445 108.715 25.615 108.885 ; + RECT 24.985 108.715 25.155 108.885 ; + RECT 24.525 108.715 24.695 108.885 ; + RECT 24.065 108.715 24.235 108.885 ; + RECT 23.605 108.715 23.775 108.885 ; + RECT 23.145 108.715 23.315 108.885 ; + RECT 22.685 108.715 22.855 108.885 ; + RECT 22.225 108.715 22.395 108.885 ; + RECT 21.765 108.715 21.935 108.885 ; + RECT 21.305 108.715 21.475 108.885 ; + RECT 20.845 108.715 21.015 108.885 ; + RECT 20.385 108.715 20.555 108.885 ; + RECT 19.925 108.715 20.095 108.885 ; + RECT 19.465 108.715 19.635 108.885 ; + RECT 19.005 108.715 19.175 108.885 ; + RECT 18.545 108.715 18.715 108.885 ; + RECT 18.085 108.715 18.255 108.885 ; + RECT 17.625 108.715 17.795 108.885 ; + RECT 17.165 108.715 17.335 108.885 ; + RECT 16.705 108.715 16.875 108.885 ; + RECT 16.245 108.715 16.415 108.885 ; + RECT 15.785 108.715 15.955 108.885 ; + RECT 15.325 108.715 15.495 108.885 ; + RECT 14.865 108.715 15.035 108.885 ; + RECT 14.405 108.715 14.575 108.885 ; + RECT 13.945 108.715 14.115 108.885 ; + RECT 13.485 108.715 13.655 108.885 ; + RECT 13.025 108.715 13.195 108.885 ; + RECT 12.565 108.715 12.735 108.885 ; + RECT 12.105 108.715 12.275 108.885 ; + RECT 11.645 108.715 11.815 108.885 ; + RECT 11.185 108.715 11.355 108.885 ; + RECT 10.725 108.715 10.895 108.885 ; + RECT 10.265 108.715 10.435 108.885 ; + RECT 9.805 108.715 9.975 108.885 ; + RECT 9.345 108.715 9.515 108.885 ; + RECT 8.885 108.715 9.055 108.885 ; + RECT 8.425 108.715 8.595 108.885 ; + RECT 7.965 108.715 8.135 108.885 ; + RECT 7.505 108.715 7.675 108.885 ; + RECT 7.045 108.715 7.215 108.885 ; + RECT 6.585 108.715 6.755 108.885 ; + RECT 6.125 108.715 6.295 108.885 ; + RECT 5.665 108.715 5.835 108.885 ; + RECT 5.205 108.715 5.375 108.885 ; + RECT 4.745 108.715 4.915 108.885 ; + RECT 4.285 108.715 4.455 108.885 ; + RECT 3.825 108.715 3.995 108.885 ; + RECT 3.365 108.715 3.535 108.885 ; + RECT 2.905 108.715 3.075 108.885 ; + RECT 2.445 108.715 2.615 108.885 ; + RECT 1.985 108.715 2.155 108.885 ; + RECT 1.525 108.715 1.695 108.885 ; + RECT 1.065 108.715 1.235 108.885 ; + RECT 0.605 108.715 0.775 108.885 ; + RECT 0.145 108.715 0.315 108.885 ; + RECT 67.765 105.995 67.935 106.165 ; + RECT 67.305 105.995 67.475 106.165 ; + RECT 0.605 105.995 0.775 106.165 ; + RECT 0.145 105.995 0.315 106.165 ; + RECT 67.765 103.275 67.935 103.445 ; + RECT 67.305 103.275 67.475 103.445 ; + RECT 0.605 103.275 0.775 103.445 ; + RECT 0.145 103.275 0.315 103.445 ; + RECT 67.765 100.555 67.935 100.725 ; + RECT 67.305 100.555 67.475 100.725 ; + RECT 0.605 100.555 0.775 100.725 ; + RECT 0.145 100.555 0.315 100.725 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; RECT 65.925 97.835 66.095 98.005 ; RECT 65.465 97.835 65.635 98.005 ; RECT 65.005 97.835 65.175 98.005 ; @@ -1770,506 +2022,354 @@ MACRO sb_0__1_ RECT 1.065 97.835 1.235 98.005 ; RECT 0.605 97.835 0.775 98.005 ; RECT 0.145 97.835 0.315 98.005 ; - RECT 65.925 95.115 66.095 95.285 ; - RECT 65.465 95.115 65.635 95.285 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; RECT 0.605 95.115 0.775 95.285 ; RECT 0.145 95.115 0.315 95.285 ; - RECT 65.925 92.395 66.095 92.565 ; - RECT 65.465 92.395 65.635 92.565 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; RECT 0.605 92.395 0.775 92.565 ; RECT 0.145 92.395 0.315 92.565 ; - RECT 65.925 89.675 66.095 89.845 ; - RECT 65.465 89.675 65.635 89.845 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; RECT 0.605 89.675 0.775 89.845 ; RECT 0.145 89.675 0.315 89.845 ; - RECT 65.925 86.955 66.095 87.125 ; - RECT 65.465 86.955 65.635 87.125 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; RECT 0.605 86.955 0.775 87.125 ; RECT 0.145 86.955 0.315 87.125 ; - RECT 65.925 84.235 66.095 84.405 ; - RECT 65.465 84.235 65.635 84.405 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; RECT 0.605 84.235 0.775 84.405 ; RECT 0.145 84.235 0.315 84.405 ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; RECT 65.925 10.795 66.095 10.965 ; RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; + RECT 19.005 10.795 19.175 10.965 ; + RECT 18.545 10.795 18.715 10.965 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -2415,31 +2515,36 @@ MACRO sb_0__1_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 97.845 55.275 97.995 ; - RECT 25.685 97.845 25.835 97.995 ; - RECT 55.125 81.525 55.275 81.675 ; - RECT 25.685 81.525 25.835 81.675 ; - RECT 55.125 16.245 55.275 16.395 ; - RECT 25.685 16.245 25.835 16.395 ; - RECT 46.385 1.625 46.535 1.775 ; - RECT 26.605 1.625 26.755 1.775 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 108.725 56.195 108.875 ; + RECT 26.605 108.725 26.755 108.875 ; + RECT 61.105 107.025 61.255 107.175 ; + RECT 38.565 107.025 38.715 107.175 ; + RECT 56.045 97.845 56.195 97.995 ; + RECT 26.605 97.845 26.755 97.995 ; + RECT 56.045 10.805 56.195 10.955 ; + RECT 26.605 10.805 26.755 10.955 ; + RECT 61.105 1.625 61.255 1.775 ; + RECT 42.705 1.625 42.855 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 83.16 64.5 83.36 64.7 ; - RECT 83.16 50.9 83.36 51.1 ; - RECT 83.16 20.3 83.36 20.5 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 108.7 56.22 108.9 ; + RECT 26.58 108.7 26.78 108.9 ; + RECT 94.2 88.3 94.4 88.5 ; + RECT 94.2 86.94 94.4 87.14 ; + RECT 94.2 65.86 94.4 66.06 ; + RECT 94.2 49.54 94.4 49.74 ; + RECT 94.2 45.46 94.4 45.66 ; + RECT 94.2 37.3 94.4 37.5 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 97.82 55.3 98.02 ; - RECT 25.66 97.82 25.86 98.02 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 108.7 56.22 108.9 ; + RECT 26.58 108.7 26.78 108.9 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 97.92 66.24 97.92 66.24 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 ; + POLYGON 0 0 0 108.8 68.08 108.8 68.08 97.92 95.68 97.92 95.68 10.88 68.08 10.88 68.08 0 ; END END sb_0__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef index f63320b..9d98cfe 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_0__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_0__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 81.6 ; + SIZE 95.68 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 14.19 0 14.33 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -371,7 +371,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 54.25 84.64 54.55 ; + RECT 94.3 71.25 95.68 71.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -379,7 +379,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 42.01 84.64 42.31 ; + RECT 94.3 34.53 95.68 34.83 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -387,7 +387,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 56.29 84.64 56.59 ; + RECT 94.3 73.97 95.68 74.27 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -395,7 +395,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 26.37 84.64 26.67 ; + RECT 94.3 81.45 95.68 81.75 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -403,7 +403,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 35.89 84.64 36.19 ; + RECT 94.3 35.89 95.68 36.19 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -411,7 +411,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 69.21 84.64 69.51 ; + RECT 94.3 17.53 95.68 17.83 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -419,7 +419,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 33.17 84.64 33.47 ; + RECT 94.3 40.65 95.68 40.95 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -427,7 +427,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 63.77 84.64 64.07 ; + RECT 94.3 50.17 95.68 50.47 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -435,7 +435,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 43.37 84.64 43.67 ; + RECT 94.3 76.69 95.68 76.99 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -443,15 +443,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 76.01 84.64 76.31 ; + RECT 94.3 61.05 95.68 61.35 ; END END chanx_right_in[9] PIN chanx_right_in[10] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 82.27 16.32 82.41 17.68 ; + LAYER met3 ; + RECT 94.3 72.61 95.68 72.91 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -459,7 +459,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 77.37 84.64 77.67 ; + RECT 94.3 80.09 95.68 80.39 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -467,7 +467,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 59.01 84.64 59.31 ; + RECT 94.3 57.65 95.68 57.95 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -475,15 +475,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 22.97 84.64 23.27 ; + RECT 94.3 67.85 95.68 68.15 ; END END chanx_right_in[13] PIN chanx_right_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 81.35 16.32 81.49 17.68 ; + LAYER met3 ; + RECT 94.3 54.93 95.68 55.23 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -491,7 +491,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 67.85 84.64 68.15 ; + RECT 94.3 52.89 95.68 53.19 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -499,7 +499,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 44.73 84.64 45.03 ; + RECT 94.3 59.69 95.68 59.99 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -507,7 +507,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 21.61 84.64 21.91 ; + RECT 94.3 84.17 95.68 84.47 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -515,7 +515,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 61.05 84.64 61.35 ; + RECT 94.3 75.33 95.68 75.63 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -523,7 +523,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 65.13 84.64 65.43 ; + RECT 94.3 62.41 95.68 62.71 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] @@ -531,31 +531,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 37.25 84.64 37.55 ; + RECT 94.3 37.25 95.68 37.55 ; END END right_top_grid_pin_1_[0] PIN right_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 5.29 66.24 5.59 ; + LAYER met2 ; + RECT 87.33 10.88 87.47 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 8.01 66.24 8.31 ; + LAYER met2 ; + RECT 88.25 10.88 88.39 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 64.86 6.65 66.24 6.95 ; + LAYER met2 ; + RECT 82.27 10.88 82.41 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -563,7 +563,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.83 16.32 75.97 17.68 ; + RECT 85.03 10.88 85.17 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -571,7 +571,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.75 16.32 76.89 17.68 ; + RECT 91.01 10.88 91.15 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -579,7 +579,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.43 16.32 80.57 17.68 ; + RECT 89.17 10.88 89.31 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -587,7 +587,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 16.32 78.27 17.68 ; + RECT 90.09 10.88 90.23 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -595,7 +595,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 86.41 10.88 86.55 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -611,7 +611,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -619,7 +619,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 0 52.97 1.36 ; + RECT 63.87 0 64.01 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 44.55 0 44.69 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.71 0 42.85 1.36 ; + RECT 46.39 0 46.53 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.17 0 20.31 1.36 ; + RECT 19.25 0 19.39 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 34.43 0 34.57 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.21 0 8.35 1.36 ; + RECT 12.81 0 12.95 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.09 0 21.23 1.36 ; + RECT 18.33 0 18.47 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 24.77 0 24.91 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; + RECT 32.59 0 32.73 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -699,7 +699,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + RECT 45.47 0 45.61 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -707,7 +707,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 40.87 0 41.01 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 13.73 0 13.87 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.27 0 36.41 1.36 ; + RECT 25.69 0 25.83 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 0 6.51 1.36 ; + RECT 10.97 0 11.11 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 11.89 0 12.03 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,7 +755,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.29 0 7.43 1.36 ; + RECT 10.05 0 10.19 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_1_[0] @@ -763,7 +763,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END bottom_left_grid_pin_1_[0] PIN ccff_head[0] @@ -771,7 +771,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 47.45 84.64 47.75 ; + RECT 94.3 42.69 95.68 42.99 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -779,7 +779,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 52.89 84.64 53.19 ; + RECT 94.3 31.81 95.68 32.11 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -787,7 +787,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 29.09 84.64 29.39 ; + RECT 94.3 33.17 95.68 33.47 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -795,7 +795,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 50.17 84.64 50.47 ; + RECT 94.3 29.09 95.68 29.39 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -803,7 +803,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 31.81 84.64 32.11 ; + RECT 94.3 30.45 95.68 30.75 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -811,7 +811,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 70.57 84.64 70.87 ; + RECT 94.3 63.77 95.68 64.07 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -819,7 +819,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 24.33 84.64 24.63 ; + RECT 94.3 19.57 95.68 19.87 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -827,7 +827,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 66.49 84.64 66.79 ; + RECT 94.3 46.09 95.68 46.39 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -835,7 +835,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 51.53 84.64 51.83 ; + RECT 94.3 27.73 95.68 28.03 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -843,7 +843,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 34.53 84.64 34.83 ; + RECT 94.3 48.13 95.68 48.43 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -851,7 +851,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 20.25 84.64 20.55 ; + RECT 94.3 24.33 95.68 24.63 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -859,7 +859,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 71.93 84.64 72.23 ; + RECT 94.3 51.53 95.68 51.83 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -867,7 +867,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 30.45 84.64 30.75 ; + RECT 94.3 22.97 95.68 23.27 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -875,7 +875,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 39.29 84.64 39.59 ; + RECT 94.3 56.29 95.68 56.59 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -883,7 +883,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 27.73 84.64 28.03 ; + RECT 94.3 26.37 95.68 26.67 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -891,7 +891,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 48.81 84.64 49.11 ; + RECT 94.3 44.05 95.68 44.35 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -899,7 +899,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 74.65 84.64 74.95 ; + RECT 94.3 38.61 95.68 38.91 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -907,7 +907,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 57.65 84.64 57.95 ; + RECT 94.3 69.89 95.68 70.19 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -915,7 +915,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 46.09 84.64 46.39 ; + RECT 94.3 82.81 95.68 83.11 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -923,7 +923,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 73.29 84.64 73.59 ; + RECT 94.3 65.81 95.68 66.11 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -931,7 +931,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 62.41 84.64 62.71 ; + RECT 94.3 21.61 95.68 21.91 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -939,7 +939,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 53.75 0 53.89 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -947,7 +947,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -955,7 +955,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -963,7 +963,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 61.11 0 61.25 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -971,7 +971,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -979,7 +979,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 17.41 0 17.55 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -987,7 +987,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 39.95 0 40.09 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -995,7 +995,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 60.19 0 60.33 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1003,7 +1003,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 59.27 0 59.41 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1011,7 +1011,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 35.35 0 35.49 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1019,15 +1019,15 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 0 62.17 1.36 ; + RECT 62.95 0 63.09 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 44.93 0 45.23 1.36 ; + LAYER met2 ; + RECT 39.03 0 39.17 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1035,31 +1035,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 41.79 0 41.93 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 9.05 0 9.35 1.36 ; + LAYER met2 ; + RECT 14.65 0 14.79 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 48.61 0 48.91 1.36 ; + LAYER met2 ; + RECT 16.49 0 16.63 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 46.77 0 47.07 1.36 ; + LAYER met2 ; + RECT 36.27 0 36.41 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1067,31 +1067,31 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 0 41.01 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 5.37 0 5.67 1.36 ; + LAYER met2 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 23.77 0 24.07 1.36 ; + LAYER met2 ; + RECT 15.57 0 15.71 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 7.21 0 7.51 1.36 ; + LAYER met2 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[19] PIN ccff_tail[0] @@ -1099,7 +1099,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.63 0 43.77 1.36 ; + RECT 42.71 0 42.85 1.36 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1107,23 +1107,23 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 77.37 1.38 77.67 ; END END SC_IN_TOP PIN SC_IN_BOT DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + LAYER met3 ; + RECT 0 47.45 1.38 47.75 ; END END SC_IN_BOT PIN SC_OUT_TOP DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + LAYER met3 ; + RECT 0 48.81 1.38 49.11 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1131,7 +1131,7 @@ MACRO sb_0__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 83.26 40.65 84.64 40.95 ; + RECT 94.3 78.73 95.68 79.03 ; END END SC_OUT_BOT PIN VDD @@ -1140,45 +1140,53 @@ MACRO sb_0__2_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 65.76 2.48 66.24 2.96 ; + RECT 67.6 2.48 68.08 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 65.76 7.92 66.24 8.4 ; + RECT 67.6 7.92 68.08 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 65.76 13.36 66.24 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; + RECT 95.2 62.32 95.68 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; + RECT 95.2 78.64 95.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 95.2 89.52 95.68 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; LAYER met4 ; - RECT 10.74 0 11.34 0.6 ; - RECT 40.18 0 40.78 0.6 ; - RECT 10.74 81 11.34 81.6 ; - RECT 40.18 81 40.78 81.6 ; + RECT 11.66 0 12.26 0.6 ; + RECT 41.1 0 41.7 0.6 ; + RECT 85.26 10.88 85.86 11.48 ; + RECT 11.66 97.32 12.26 97.92 ; + RECT 41.1 97.32 41.7 97.92 ; + RECT 85.26 97.32 85.86 97.92 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 81.44 26.96 84.64 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 81.44 67.76 84.64 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 92.48 22.2 95.68 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 92.48 63 95.68 66.2 ; END END VDD PIN VSS @@ -1186,616 +1194,708 @@ MACRO sb_0__2_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 66.24 0.24 ; + RECT 0 0 68.08 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 65.76 5.2 66.24 5.68 ; - RECT 0 10.64 0.48 11.12 ; - RECT 65.76 10.64 66.24 11.12 ; - RECT 0 16.08 84.64 16.56 ; + RECT 67.6 5.2 68.08 5.68 ; + RECT 0 10.64 95.68 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; + RECT 95.2 59.6 95.68 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 84.16 65.04 84.64 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 0 81.36 84.64 81.6 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 95.2 86.8 95.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 0 97.68 95.68 97.92 ; LAYER met4 ; - RECT 25.46 0 26.06 0.6 ; - RECT 54.9 0 55.5 0.6 ; - RECT 25.46 81 26.06 81.6 ; - RECT 54.9 81 55.5 81.6 ; + RECT 26.38 0 26.98 0.6 ; + RECT 55.82 0 56.42 0.6 ; + RECT 26.38 97.32 26.98 97.92 ; + RECT 55.82 97.32 56.42 97.92 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 81.44 47.36 84.64 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 92.48 42.6 95.68 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 92.48 83.4 95.68 86.6 ; END END VSS OBS LAYER li1 ; - RECT 0 81.515 84.64 81.685 ; - RECT 80.96 78.795 84.64 78.965 ; + RECT 0 97.835 95.68 98.005 ; + RECT 95.22 95.115 95.68 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 95.22 92.395 95.68 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 95.22 89.675 95.68 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 94.76 86.955 95.68 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 94.76 84.235 95.68 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 94.76 81.515 95.68 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 94.76 78.795 95.68 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 80.96 76.075 84.64 76.245 ; + RECT 94.76 76.075 95.68 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 83.72 73.355 84.64 73.525 ; + RECT 94.76 73.355 95.68 73.525 ; RECT 0 73.355 3.68 73.525 ; - RECT 83.72 70.635 84.64 70.805 ; + RECT 95.22 70.635 95.68 70.805 ; RECT 0 70.635 3.68 70.805 ; - RECT 84.18 67.915 84.64 68.085 ; + RECT 95.22 67.915 95.68 68.085 ; RECT 0 67.915 3.68 68.085 ; - RECT 83.72 65.195 84.64 65.365 ; + RECT 93.84 65.195 95.68 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 83.72 62.475 84.64 62.645 ; + RECT 92 62.475 95.68 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 83.72 59.755 84.64 59.925 ; + RECT 92 59.755 95.68 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 83.72 57.035 84.64 57.205 ; + RECT 94.76 57.035 95.68 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 84.18 54.315 84.64 54.485 ; + RECT 94.76 54.315 95.68 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 84.18 51.595 84.64 51.765 ; + RECT 95.22 51.595 95.68 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 83.72 48.875 84.64 49.045 ; + RECT 94.76 48.875 95.68 49.045 ; RECT 0 48.875 3.68 49.045 ; - RECT 83.72 46.155 84.64 46.325 ; + RECT 94.76 46.155 95.68 46.325 ; RECT 0 46.155 3.68 46.325 ; - RECT 83.72 43.435 84.64 43.605 ; + RECT 94.76 43.435 95.68 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 83.72 40.715 84.64 40.885 ; + RECT 94.76 40.715 95.68 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 83.72 37.995 84.64 38.165 ; + RECT 94.76 37.995 95.68 38.165 ; RECT 0 37.995 3.68 38.165 ; - RECT 83.72 35.275 84.64 35.445 ; + RECT 94.76 35.275 95.68 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; + RECT 94.76 32.555 95.68 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 94.76 29.835 95.68 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 80.96 27.115 84.64 27.285 ; + RECT 94.76 27.115 95.68 27.285 ; RECT 0 27.115 3.68 27.285 ; - RECT 80.96 24.395 84.64 24.565 ; + RECT 94.76 24.395 95.68 24.565 ; RECT 0 24.395 3.68 24.565 ; - RECT 83.72 21.675 84.64 21.845 ; + RECT 94.76 21.675 95.68 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 83.72 18.955 84.64 19.125 ; + RECT 94.76 18.955 95.68 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 65.32 16.235 84.64 16.405 ; + RECT 94.76 16.235 95.68 16.405 ; RECT 0 16.235 3.68 16.405 ; - RECT 65.32 13.515 66.24 13.685 ; + RECT 95.22 13.515 95.68 13.685 ; RECT 0 13.515 3.68 13.685 ; - RECT 62.56 10.795 66.24 10.965 ; + RECT 64.86 10.795 95.68 10.965 ; RECT 0 10.795 3.68 10.965 ; - RECT 62.56 8.075 66.24 8.245 ; + RECT 67.16 8.075 68.08 8.245 ; RECT 0 8.075 3.68 8.245 ; - RECT 65.32 5.355 66.24 5.525 ; + RECT 67.16 5.355 68.08 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 65.32 2.635 66.24 2.805 ; + RECT 67.16 2.635 68.08 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 66.24 0.085 ; + RECT 0 -0.085 68.08 0.085 ; LAYER met2 ; - RECT 55.06 81.415 55.34 81.785 ; - RECT 25.62 81.415 25.9 81.785 ; - POLYGON 66.31 27.27 66.31 16.59 64.79 16.59 64.79 16.73 66.17 16.73 66.17 27.27 ; - RECT 80.83 17.86 81.09 18.18 ; - RECT 32.99 1.54 33.25 1.86 ; - RECT 27.01 1.54 27.27 1.86 ; - RECT 55.06 -0.185 55.34 0.185 ; - RECT 25.62 -0.185 25.9 0.185 ; - POLYGON 84.36 81.32 84.36 16.6 82.69 16.6 82.69 17.96 81.99 17.96 81.99 16.6 81.77 16.6 81.77 17.96 81.07 17.96 81.07 16.6 80.85 16.6 80.85 17.96 80.15 17.96 80.15 16.6 78.55 16.6 78.55 17.96 77.85 17.96 77.85 16.6 77.17 16.6 77.17 17.96 76.47 17.96 76.47 16.6 76.25 16.6 76.25 17.96 75.55 17.96 75.55 16.6 65.96 16.6 65.96 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.51 0.28 21.51 1.64 20.81 1.64 20.81 0.28 20.59 0.28 20.59 1.64 19.89 1.64 19.89 0.28 14.61 0.28 14.61 1.64 13.91 1.64 13.91 0.28 8.63 0.28 8.63 1.64 7.93 1.64 7.93 0.28 7.71 0.28 7.71 1.64 7.01 1.64 7.01 0.28 6.79 0.28 6.79 1.64 6.09 1.64 6.09 0.28 0.28 0.28 0.28 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 ; + RECT 55.98 97.735 56.26 98.105 ; + RECT 26.54 97.735 26.82 98.105 ; + RECT 53.23 1.54 53.49 1.86 ; + RECT 46.79 1.54 47.05 1.86 ; + RECT 38.51 1.54 38.77 1.86 ; + RECT 55.98 -0.185 56.26 0.185 ; + RECT 26.54 -0.185 26.82 0.185 ; + POLYGON 95.4 97.64 95.4 11.16 91.43 11.16 91.43 12.52 90.73 12.52 90.73 11.16 90.51 11.16 90.51 12.52 89.81 12.52 89.81 11.16 89.59 11.16 89.59 12.52 88.89 12.52 88.89 11.16 88.67 11.16 88.67 12.52 87.97 12.52 87.97 11.16 87.75 11.16 87.75 12.52 87.05 12.52 87.05 11.16 86.83 11.16 86.83 12.52 86.13 12.52 86.13 11.16 85.45 11.16 85.45 12.52 84.75 12.52 84.75 11.16 82.69 11.16 82.69 12.52 81.99 12.52 81.99 11.16 67.8 11.16 67.8 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.17 0.28 54.17 1.64 53.47 1.64 53.47 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 43.13 0.28 43.13 1.64 42.43 1.64 42.43 0.28 42.21 0.28 42.21 1.64 41.51 1.64 41.51 0.28 41.29 0.28 41.29 1.64 40.59 1.64 40.59 0.28 40.37 0.28 40.37 1.64 39.67 1.64 39.67 0.28 39.45 0.28 39.45 1.64 38.75 1.64 38.75 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 36.69 0.28 36.69 1.64 35.99 1.64 35.99 0.28 35.77 0.28 35.77 1.64 35.07 1.64 35.07 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 19.67 0.28 19.67 1.64 18.97 1.64 18.97 0.28 18.75 0.28 18.75 1.64 18.05 1.64 18.05 0.28 17.83 0.28 17.83 1.64 17.13 1.64 17.13 0.28 16.91 0.28 16.91 1.64 16.21 1.64 16.21 0.28 15.99 0.28 15.99 1.64 15.29 1.64 15.29 0.28 15.07 0.28 15.07 1.64 14.37 1.64 14.37 0.28 14.15 0.28 14.15 1.64 13.45 1.64 13.45 0.28 13.23 0.28 13.23 1.64 12.53 1.64 12.53 0.28 12.31 0.28 12.31 1.64 11.61 1.64 11.61 0.28 11.39 0.28 11.39 1.64 10.69 1.64 10.69 0.28 10.47 0.28 10.47 1.64 9.77 1.64 9.77 0.28 0.28 0.28 0.28 97.64 ; LAYER met3 ; - POLYGON 55.365 81.765 55.365 81.76 55.58 81.76 55.58 81.44 55.365 81.44 55.365 81.435 55.035 81.435 55.035 81.44 54.82 81.44 54.82 81.76 55.035 81.76 55.035 81.765 ; - POLYGON 25.925 81.765 25.925 81.76 26.14 81.76 26.14 81.44 25.925 81.44 25.925 81.435 25.595 81.435 25.595 81.44 25.38 81.44 25.38 81.76 25.595 81.76 25.595 81.765 ; - POLYGON 83.425 38.245 83.425 37.915 83.095 37.915 83.095 37.93 72.07 37.93 72.07 38.23 83.095 38.23 83.095 38.245 ; - POLYGON 83.41 23.95 83.41 23.67 82.86 23.67 82.86 23.65 30.21 23.65 30.21 23.95 ; - POLYGON 64.565 9.005 64.565 8.675 64.235 8.675 64.235 8.69 57.35 8.69 57.35 8.99 64.235 8.99 64.235 9.005 ; - POLYGON 55.365 0.165 55.365 0.16 55.58 0.16 55.58 -0.16 55.365 -0.16 55.365 -0.165 55.035 -0.165 55.035 -0.16 54.82 -0.16 54.82 0.16 55.035 0.16 55.035 0.165 ; - POLYGON 25.925 0.165 25.925 0.16 26.14 0.16 26.14 -0.16 25.925 -0.16 25.925 -0.165 25.595 -0.165 25.595 -0.16 25.38 -0.16 25.38 0.16 25.595 0.16 25.595 0.165 ; - POLYGON 84.24 81.2 84.24 78.07 82.86 78.07 82.86 76.97 84.24 76.97 84.24 76.71 82.86 76.71 82.86 75.61 84.24 75.61 84.24 75.35 82.86 75.35 82.86 74.25 84.24 74.25 84.24 73.99 82.86 73.99 82.86 72.89 84.24 72.89 84.24 72.63 82.86 72.63 82.86 71.53 84.24 71.53 84.24 71.27 82.86 71.27 82.86 70.17 84.24 70.17 84.24 69.91 82.86 69.91 82.86 68.81 84.24 68.81 84.24 68.55 82.86 68.55 82.86 67.45 84.24 67.45 84.24 67.19 82.86 67.19 82.86 66.09 84.24 66.09 84.24 65.83 82.86 65.83 82.86 64.73 84.24 64.73 84.24 64.47 82.86 64.47 82.86 63.37 84.24 63.37 84.24 63.11 82.86 63.11 82.86 62.01 84.24 62.01 84.24 61.75 82.86 61.75 82.86 60.65 84.24 60.65 84.24 59.71 82.86 59.71 82.86 58.61 84.24 58.61 84.24 58.35 82.86 58.35 82.86 57.25 84.24 57.25 84.24 56.99 82.86 56.99 82.86 55.89 84.24 55.89 84.24 54.95 82.86 54.95 82.86 53.85 84.24 53.85 84.24 53.59 82.86 53.59 82.86 52.49 84.24 52.49 84.24 52.23 82.86 52.23 82.86 51.13 84.24 51.13 84.24 50.87 82.86 50.87 82.86 49.77 84.24 49.77 84.24 49.51 82.86 49.51 82.86 48.41 84.24 48.41 84.24 48.15 82.86 48.15 82.86 47.05 84.24 47.05 84.24 46.79 82.86 46.79 82.86 45.69 84.24 45.69 84.24 45.43 82.86 45.43 82.86 44.33 84.24 44.33 84.24 44.07 82.86 44.07 82.86 42.97 84.24 42.97 84.24 42.71 82.86 42.71 82.86 41.61 84.24 41.61 84.24 41.35 82.86 41.35 82.86 40.25 84.24 40.25 84.24 39.99 82.86 39.99 82.86 38.89 84.24 38.89 84.24 37.95 82.86 37.95 82.86 36.85 84.24 36.85 84.24 36.59 82.86 36.59 82.86 35.49 84.24 35.49 84.24 35.23 82.86 35.23 82.86 34.13 84.24 34.13 84.24 33.87 82.86 33.87 82.86 32.77 84.24 32.77 84.24 32.51 82.86 32.51 82.86 31.41 84.24 31.41 84.24 31.15 82.86 31.15 82.86 30.05 84.24 30.05 84.24 29.79 82.86 29.79 82.86 28.69 84.24 28.69 84.24 28.43 82.86 28.43 82.86 27.33 84.24 27.33 84.24 27.07 82.86 27.07 82.86 25.97 84.24 25.97 84.24 25.03 82.86 25.03 82.86 23.93 84.24 23.93 84.24 23.67 82.86 23.67 82.86 22.57 84.24 22.57 84.24 22.31 82.86 22.31 82.86 21.21 84.24 21.21 84.24 20.95 82.86 20.95 82.86 19.85 84.24 19.85 84.24 16.72 65.84 16.72 65.84 8.71 64.46 8.71 64.46 7.61 65.84 7.61 65.84 7.35 64.46 7.35 64.46 6.25 65.84 6.25 65.84 5.99 64.46 5.99 64.46 4.89 65.84 4.89 65.84 0.4 0.4 0.4 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 81.2 ; - LAYER met4 ; - POLYGON 84.24 81.2 84.24 16.72 65.84 16.72 65.84 0.4 55.9 0.4 55.9 1 54.5 1 54.5 0.4 49.31 0.4 49.31 1.76 48.21 1.76 48.21 0.4 47.47 0.4 47.47 1.76 46.37 1.76 46.37 0.4 45.63 0.4 45.63 1.76 44.53 1.76 44.53 0.4 41.18 0.4 41.18 1 39.78 1 39.78 0.4 26.46 0.4 26.46 1 25.06 1 25.06 0.4 24.47 0.4 24.47 1.76 23.37 1.76 23.37 0.4 11.74 0.4 11.74 1 10.34 1 10.34 0.4 9.75 0.4 9.75 1.76 8.65 1.76 8.65 0.4 7.91 0.4 7.91 1.76 6.81 1.76 6.81 0.4 6.07 0.4 6.07 1.76 4.97 1.76 4.97 0.4 0.4 0.4 0.4 81.2 10.34 81.2 10.34 80.6 11.74 80.6 11.74 81.2 25.06 81.2 25.06 80.6 26.46 80.6 26.46 81.2 39.78 81.2 39.78 80.6 41.18 80.6 41.18 81.2 54.5 81.2 54.5 80.6 55.9 80.6 55.9 81.2 ; + POLYGON 56.285 98.085 56.285 98.08 56.5 98.08 56.5 97.76 56.285 97.76 56.285 97.755 55.955 97.755 55.955 97.76 55.74 97.76 55.74 98.08 55.955 98.08 55.955 98.085 ; + POLYGON 26.845 98.085 26.845 98.08 27.06 98.08 27.06 97.76 26.845 97.76 26.845 97.755 26.515 97.755 26.515 97.76 26.3 97.76 26.3 98.08 26.515 98.08 26.515 98.085 ; + POLYGON 56.285 0.165 56.285 0.16 56.5 0.16 56.5 -0.16 56.285 -0.16 56.285 -0.165 55.955 -0.165 55.955 -0.16 55.74 -0.16 55.74 0.16 55.955 0.16 55.955 0.165 ; + POLYGON 26.845 0.165 26.845 0.16 27.06 0.16 27.06 -0.16 26.845 -0.16 26.845 -0.165 26.515 -0.165 26.515 -0.16 26.3 -0.16 26.3 0.16 26.515 0.16 26.515 0.165 ; + POLYGON 95.28 97.52 95.28 84.87 93.9 84.87 93.9 83.77 95.28 83.77 95.28 83.51 93.9 83.51 93.9 82.41 95.28 82.41 95.28 82.15 93.9 82.15 93.9 81.05 95.28 81.05 95.28 80.79 93.9 80.79 93.9 79.69 95.28 79.69 95.28 79.43 93.9 79.43 93.9 78.33 95.28 78.33 95.28 77.39 93.9 77.39 93.9 76.29 95.28 76.29 95.28 76.03 93.9 76.03 93.9 74.93 95.28 74.93 95.28 74.67 93.9 74.67 93.9 73.57 95.28 73.57 95.28 73.31 93.9 73.31 93.9 72.21 95.28 72.21 95.28 71.95 93.9 71.95 93.9 70.85 95.28 70.85 95.28 70.59 93.9 70.59 93.9 69.49 95.28 69.49 95.28 68.55 93.9 68.55 93.9 67.45 95.28 67.45 95.28 66.51 93.9 66.51 93.9 65.41 95.28 65.41 95.28 64.47 93.9 64.47 93.9 63.37 95.28 63.37 95.28 63.11 93.9 63.11 93.9 62.01 95.28 62.01 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 60.39 93.9 60.39 93.9 59.29 95.28 59.29 95.28 58.35 93.9 58.35 93.9 57.25 95.28 57.25 95.28 56.99 93.9 56.99 93.9 55.89 95.28 55.89 95.28 55.63 93.9 55.63 93.9 54.53 95.28 54.53 95.28 53.59 93.9 53.59 93.9 52.49 95.28 52.49 95.28 52.23 93.9 52.23 93.9 51.13 95.28 51.13 95.28 50.87 93.9 50.87 93.9 49.77 95.28 49.77 95.28 48.83 93.9 48.83 93.9 47.73 95.28 47.73 95.28 46.79 93.9 46.79 93.9 45.69 95.28 45.69 95.28 44.75 93.9 44.75 93.9 43.65 95.28 43.65 95.28 43.39 93.9 43.39 93.9 42.29 95.28 42.29 95.28 41.35 93.9 41.35 93.9 40.25 95.28 40.25 95.28 39.31 93.9 39.31 93.9 38.21 95.28 38.21 95.28 37.95 93.9 37.95 93.9 36.85 95.28 36.85 95.28 36.59 93.9 36.59 93.9 35.49 95.28 35.49 95.28 35.23 93.9 35.23 93.9 34.13 95.28 34.13 95.28 33.87 93.9 33.87 93.9 32.77 95.28 32.77 95.28 32.51 93.9 32.51 93.9 31.41 95.28 31.41 95.28 31.15 93.9 31.15 93.9 30.05 95.28 30.05 95.28 29.79 93.9 29.79 93.9 28.69 95.28 28.69 95.28 28.43 93.9 28.43 93.9 27.33 95.28 27.33 95.28 27.07 93.9 27.07 93.9 25.97 95.28 25.97 95.28 25.03 93.9 25.03 93.9 23.93 95.28 23.93 95.28 23.67 93.9 23.67 93.9 22.57 95.28 22.57 95.28 22.31 93.9 22.31 93.9 21.21 95.28 21.21 95.28 20.27 93.9 20.27 93.9 19.17 95.28 19.17 95.28 18.23 93.9 18.23 93.9 17.13 95.28 17.13 95.28 11.28 67.68 11.28 67.68 0.4 0.4 0.4 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 97.52 ; LAYER met5 ; - POLYGON 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 17.92 64.64 17.92 64.64 1.6 1.6 1.6 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; + POLYGON 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 12.48 66.48 12.48 66.48 1.6 1.6 1.6 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; + LAYER met4 ; + POLYGON 95.28 97.52 95.28 11.28 86.26 11.28 86.26 11.88 84.86 11.88 84.86 11.28 67.68 11.28 67.68 0.4 56.82 0.4 56.82 1 55.42 1 55.42 0.4 42.1 0.4 42.1 1 40.7 1 40.7 0.4 27.38 0.4 27.38 1 25.98 1 25.98 0.4 12.66 0.4 12.66 1 11.26 1 11.26 0.4 0.4 0.4 0.4 97.52 11.26 97.52 11.26 96.92 12.66 96.92 12.66 97.52 25.98 97.52 25.98 96.92 27.38 96.92 27.38 97.52 40.7 97.52 40.7 96.92 42.1 96.92 42.1 97.52 55.42 97.52 55.42 96.92 56.82 96.92 56.82 97.52 84.86 97.52 84.86 96.92 86.26 96.92 86.26 97.52 ; LAYER met1 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 65.96 15.8 65.96 14.12 65.48 14.12 65.48 13.08 65.96 13.08 65.96 11.4 65.48 11.4 65.48 10.36 65.96 10.36 65.96 8.68 65.48 8.68 65.48 7.64 65.96 7.64 65.96 5.96 65.48 5.96 65.48 4.92 65.96 4.92 65.96 3.24 65.48 3.24 65.48 2.2 65.96 2.2 65.96 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 67.8 10.36 67.8 8.68 67.32 8.68 67.32 7.64 67.8 7.64 67.8 5.96 67.32 5.96 67.32 4.92 67.8 4.92 67.8 3.24 67.32 3.24 67.32 2.2 67.8 2.2 67.8 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 ; LAYER li1 ; - POLYGON 84.47 81.43 84.47 16.49 66.07 16.49 66.07 0.17 0.17 0.17 0.17 81.43 ; + POLYGON 95.51 97.75 95.51 11.05 67.91 11.05 67.91 0.17 0.17 0.17 0.17 97.75 ; LAYER mcon ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 25.445 97.835 25.615 98.005 ; + RECT 24.985 97.835 25.155 98.005 ; + RECT 24.525 97.835 24.695 98.005 ; + RECT 24.065 97.835 24.235 98.005 ; + RECT 23.605 97.835 23.775 98.005 ; + RECT 23.145 97.835 23.315 98.005 ; + RECT 22.685 97.835 22.855 98.005 ; + RECT 22.225 97.835 22.395 98.005 ; + RECT 21.765 97.835 21.935 98.005 ; + RECT 21.305 97.835 21.475 98.005 ; + RECT 20.845 97.835 21.015 98.005 ; + RECT 20.385 97.835 20.555 98.005 ; + RECT 19.925 97.835 20.095 98.005 ; + RECT 19.465 97.835 19.635 98.005 ; + RECT 19.005 97.835 19.175 98.005 ; + RECT 18.545 97.835 18.715 98.005 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 65.925 13.515 66.095 13.685 ; - RECT 65.465 13.515 65.635 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; + RECT 84.325 10.795 84.495 10.965 ; + RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; RECT 65.925 10.795 66.095 10.965 ; RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; + RECT 19.005 10.795 19.175 10.965 ; + RECT 18.545 10.795 18.715 10.965 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 65.925 8.075 66.095 8.245 ; - RECT 65.465 8.075 65.635 8.245 ; + RECT 67.765 8.075 67.935 8.245 ; + RECT 67.305 8.075 67.475 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 65.925 5.355 66.095 5.525 ; - RECT 65.465 5.355 65.635 5.525 ; + RECT 67.765 5.355 67.935 5.525 ; + RECT 67.305 5.355 67.475 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 65.925 2.635 66.095 2.805 ; - RECT 65.465 2.635 65.635 2.805 ; + RECT 67.765 2.635 67.935 2.805 ; + RECT 67.305 2.635 67.475 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 67.765 -0.085 67.935 0.085 ; + RECT 67.305 -0.085 67.475 0.085 ; + RECT 66.845 -0.085 67.015 0.085 ; + RECT 66.385 -0.085 66.555 0.085 ; RECT 65.925 -0.085 66.095 0.085 ; RECT 65.465 -0.085 65.635 0.085 ; RECT 65.005 -0.085 65.175 0.085 ; @@ -1941,30 +2041,39 @@ MACRO sb_0__2_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 55.125 81.525 55.275 81.675 ; - RECT 25.685 81.525 25.835 81.675 ; - RECT 82.265 17.945 82.415 18.095 ; - RECT 76.745 17.945 76.895 18.095 ; - RECT 55.125 16.245 55.275 16.395 ; - RECT 25.685 16.245 25.835 16.395 ; - RECT 55.125 -0.075 55.275 0.075 ; - RECT 25.685 -0.075 25.835 0.075 ; + RECT 56.045 97.845 56.195 97.995 ; + RECT 26.605 97.845 26.755 97.995 ; + RECT 82.265 12.505 82.415 12.655 ; + RECT 56.045 10.805 56.195 10.955 ; + RECT 26.605 10.805 26.755 10.955 ; + RECT 55.125 1.625 55.275 1.775 ; + RECT 42.705 1.625 42.855 1.775 ; + RECT 36.265 1.625 36.415 1.775 ; + RECT 34.425 1.625 34.575 1.775 ; + RECT 17.405 1.625 17.555 1.775 ; + RECT 56.045 -0.075 56.195 0.075 ; + RECT 26.605 -0.075 26.755 0.075 ; LAYER via2 ; - RECT 55.1 81.5 55.3 81.7 ; - RECT 25.66 81.5 25.86 81.7 ; - RECT 83.16 50.22 83.36 50.42 ; - RECT 83.16 44.78 83.36 44.98 ; - RECT 82.7 40.7 82.9 40.9 ; - RECT 83.16 31.86 83.36 32.06 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 97.82 56.22 98.02 ; + RECT 26.58 97.82 26.78 98.02 ; + RECT 93.74 78.78 93.94 78.98 ; + RECT 1.28 77.42 1.48 77.62 ; + RECT 94.2 69.94 94.4 70.14 ; + RECT 94.2 61.1 94.4 61.3 ; + RECT 94.2 52.94 94.4 53.14 ; + RECT 1.28 47.5 1.48 47.7 ; + RECT 94.2 42.74 94.4 42.94 ; + RECT 93.74 34.58 93.94 34.78 ; + RECT 94.2 23.02 94.4 23.22 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER via3 ; - RECT 55.1 81.5 55.3 81.7 ; - RECT 25.66 81.5 25.86 81.7 ; - RECT 55.1 -0.1 55.3 0.1 ; - RECT 25.66 -0.1 25.86 0.1 ; + RECT 56.02 97.82 56.22 98.02 ; + RECT 26.58 97.82 26.78 98.02 ; + RECT 56.02 -0.1 56.22 0.1 ; + RECT 26.58 -0.1 26.78 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 81.6 84.64 81.6 84.64 16.32 66.24 16.32 66.24 0 ; + POLYGON 0 0 0 97.92 95.68 97.92 95.68 10.88 68.08 10.88 68.08 0 ; END END sb_0__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef index dfeefc6..d4402d5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 103.04 BY 81.6 ; + SIZE 123.28 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 20.63 80.24 20.77 81.6 ; + RECT 57.43 0 57.57 1.36 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.61 80.24 72.75 81.6 ; + RECT 67.55 96.56 67.69 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 80.24 53.43 81.6 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 80.24 52.51 81.6 ; + RECT 65.71 96.56 65.85 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,15 +395,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.85 80.24 69.99 81.6 ; + RECT 80.43 96.56 80.57 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 60.57 80.24 60.87 81.6 ; + LAYER met2 ; + RECT 60.65 96.56 60.79 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 80.24 47.45 81.6 ; + RECT 73.99 96.56 74.13 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.29 80.24 76.43 81.6 ; + RECT 58.81 96.56 58.95 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 80.24 65.85 81.6 ; + RECT 75.83 96.56 75.97 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 80.24 56.19 81.6 ; + RECT 52.37 96.56 52.51 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 80.24 40.09 81.6 ; + RECT 71.23 96.56 71.37 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 55.97 80.24 56.27 81.6 ; + RECT 66.09 96.56 66.39 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.77 80.24 70.91 81.6 ; + RECT 50.53 96.56 50.67 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 80.24 75.51 81.6 ; + RECT 86.41 96.56 86.55 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.93 80.24 69.07 81.6 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 80.24 54.35 81.6 ; + RECT 62.95 96.56 63.09 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,15 +491,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 80.24 39.17 81.6 ; + RECT 66.63 96.56 66.77 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 62.41 80.24 62.71 81.6 ; + LAYER met2 ; + RECT 81.35 96.56 81.49 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 80.24 58.49 81.6 ; + RECT 74.91 96.56 75.05 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 80.24 55.27 81.6 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 80.24 57.11 81.6 ; + RECT 51.45 96.56 51.59 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,15 +531,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 80.24 25.83 81.6 ; + RECT 17.87 85.68 18.01 87.04 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 80.24 24.99 81.6 ; + LAYER met2 ; + RECT 12.81 85.68 12.95 87.04 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] @@ -547,7 +547,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 80.24 23.99 81.6 ; + RECT 8.21 85.68 8.35 87.04 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 80.24 22.15 81.6 ; + RECT 11.89 85.68 12.03 87.04 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 80.24 23.07 81.6 ; + RECT 6.37 85.68 6.51 87.04 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,15 +571,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 63.92 8.81 65.28 ; + RECT 10.97 85.68 11.11 87.04 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 80.24 23.15 81.6 ; + LAYER met2 ; + RECT 7.29 85.68 7.43 87.04 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] @@ -587,7 +587,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 80.24 24.91 81.6 ; + RECT 5.45 85.68 5.59 87.04 ; END END top_left_grid_pin_49_[0] PIN chanx_right_in[0] @@ -595,7 +595,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 36.57 103.04 36.87 ; + RECT 121.9 76.69 123.28 76.99 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -603,7 +603,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 18.89 103.04 19.19 ; + RECT 121.9 25.69 123.28 25.99 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -611,23 +611,23 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 17.53 103.04 17.83 ; + RECT 121.9 13.45 123.28 13.75 ; END END chanx_right_in[2] PIN chanx_right_in[3] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 98.83 0 98.97 1.36 ; + LAYER met3 ; + RECT 121.9 39.29 123.28 39.59 ; END END chanx_right_in[3] PIN chanx_right_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 100.67 0 100.81 1.36 ; + LAYER met3 ; + RECT 121.9 37.93 123.28 38.23 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -635,7 +635,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 10.73 103.04 11.03 ; + RECT 121.9 40.65 123.28 40.95 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -643,7 +643,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.29 103.04 39.59 ; + RECT 121.9 27.05 123.28 27.35 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -651,7 +651,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 121.9 52.89 123.28 53.19 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -659,15 +659,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 43.37 103.04 43.67 ; + RECT 121.9 75.33 123.28 75.63 ; END END chanx_right_in[8] PIN chanx_right_in[9] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 97.91 0 98.05 1.36 ; + LAYER met3 ; + RECT 121.9 46.09 123.28 46.39 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -675,7 +675,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 3.93 103.04 4.23 ; + RECT 121.9 44.73 123.28 45.03 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -683,7 +683,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.01 103.04 42.31 ; + RECT 121.9 21.61 123.28 21.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -691,7 +691,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.93 103.04 38.23 ; + RECT 121.9 10.73 123.28 11.03 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -699,7 +699,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 46.09 103.04 46.39 ; + RECT 121.9 70.57 123.28 70.87 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -707,15 +707,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 40.65 103.04 40.95 ; + RECT 121.9 61.73 123.28 62.03 ; END END chanx_right_in[14] PIN chanx_right_in[15] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 98.29 0 98.59 1.36 ; + LAYER met3 ; + RECT 121.9 71.93 123.28 72.23 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -723,7 +723,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 25.69 103.04 25.99 ; + RECT 121.9 22.97 123.28 23.27 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -731,7 +731,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 6.65 103.04 6.95 ; + RECT 121.9 9.37 123.28 9.67 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -739,7 +739,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 12.09 103.04 12.39 ; + RECT 121.9 31.13 123.28 31.43 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -747,7 +747,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 13.45 103.04 13.75 ; + RECT 121.9 28.41 123.28 28.71 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_1_[0] @@ -755,7 +755,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 121.9 60.37 123.28 60.67 ; END END right_bottom_grid_pin_1_[0] PIN right_bottom_grid_pin_3_[0] @@ -763,7 +763,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 48.81 103.04 49.11 ; + RECT 121.9 56.97 123.28 57.27 ; END END right_bottom_grid_pin_3_[0] PIN right_bottom_grid_pin_5_[0] @@ -771,7 +771,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 121.9 66.49 123.28 66.79 ; END END right_bottom_grid_pin_5_[0] PIN right_bottom_grid_pin_7_[0] @@ -779,7 +779,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 30.45 103.04 30.75 ; + RECT 121.9 43.37 123.28 43.67 ; END END right_bottom_grid_pin_7_[0] PIN right_bottom_grid_pin_9_[0] @@ -787,7 +787,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 121.9 69.21 123.28 69.51 ; END END right_bottom_grid_pin_9_[0] PIN right_bottom_grid_pin_11_[0] @@ -795,7 +795,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 24.33 103.04 24.63 ; + RECT 121.9 55.61 123.28 55.91 ; END END right_bottom_grid_pin_11_[0] PIN chanx_left_in[0] @@ -803,7 +803,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 76.69 1.38 76.99 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -811,7 +811,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -819,7 +819,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -827,7 +827,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -835,7 +835,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -843,7 +843,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -851,15 +851,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[6] PIN chanx_left_in[7] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.15 63.92 3.29 65.28 ; + LAYER met3 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -867,7 +867,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -875,7 +875,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 10.05 1.38 10.35 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -883,15 +883,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[10] PIN chanx_left_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 63.92 2.37 65.28 ; + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -899,23 +899,23 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_in[12] PIN chanx_left_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.99 63.92 5.13 65.28 ; + LAYER met3 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_in[13] PIN chanx_left_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 63.92 4.75 65.28 ; + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -923,7 +923,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -931,7 +931,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -939,7 +939,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -947,7 +947,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -955,7 +955,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_1_[0] @@ -963,7 +963,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; + RECT 0 54.25 1.38 54.55 ; END END left_bottom_grid_pin_1_[0] PIN left_bottom_grid_pin_3_[0] @@ -971,7 +971,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 51.53 1.38 51.83 ; END END left_bottom_grid_pin_3_[0] PIN left_bottom_grid_pin_5_[0] @@ -979,7 +979,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 40.65 1.38 40.95 ; END END left_bottom_grid_pin_5_[0] PIN left_bottom_grid_pin_7_[0] @@ -987,7 +987,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 67.85 1.38 68.15 ; END END left_bottom_grid_pin_7_[0] PIN left_bottom_grid_pin_9_[0] @@ -995,7 +995,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 42.01 1.38 42.31 ; END END left_bottom_grid_pin_9_[0] PIN left_bottom_grid_pin_11_[0] @@ -1003,7 +1003,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 48.13 1.38 48.43 ; END END left_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -1011,7 +1011,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.05 103.04 27.35 ; + RECT 121.9 12.09 123.28 12.39 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1019,7 +1019,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 80.24 49.75 81.6 ; + RECT 55.59 96.56 55.73 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1027,7 +1027,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 80.24 51.59 81.6 ; + RECT 79.51 96.56 79.65 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1035,7 +1035,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 80.24 45.61 81.6 ; + RECT 59.73 96.56 59.87 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1043,7 +1043,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 80.24 64.01 81.6 ; + RECT 77.67 96.56 77.81 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1051,7 +1051,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 80.24 59.41 81.6 ; + RECT 72.15 96.56 72.29 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1059,7 +1059,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 80.24 68.15 81.6 ; + RECT 82.73 96.56 82.87 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1067,7 +1067,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 80.24 50.67 81.6 ; + RECT 63.87 96.56 64.01 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1075,7 +1075,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 80.24 61.25 81.6 ; + RECT 68.47 96.56 68.61 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1083,7 +1083,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + RECT 49.15 96.56 49.29 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1091,7 +1091,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 80.24 60.33 81.6 ; + RECT 84.57 96.56 84.71 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1099,7 +1099,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 80.24 48.37 81.6 ; + RECT 64.79 96.56 64.93 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1107,7 +1107,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.69 80.24 71.83 81.6 ; + RECT 69.85 96.56 69.99 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1115,7 +1115,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 80.24 74.59 81.6 ; + RECT 85.49 96.56 85.63 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1123,7 +1123,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 80.24 62.63 81.6 ; + RECT 87.79 96.56 87.93 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1131,7 +1131,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 80.24 41.01 81.6 ; + RECT 34.89 96.56 35.03 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1139,7 +1139,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 80.24 64.93 81.6 ; + RECT 76.75 96.56 76.89 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1147,7 +1147,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + RECT 36.73 96.56 36.87 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1155,7 +1155,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 80.24 66.77 81.6 ; + RECT 73.07 96.56 73.21 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1163,7 +1163,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 80.24 46.53 81.6 ; + RECT 53.29 96.56 53.43 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1171,7 +1171,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 80.24 77.81 81.6 ; + RECT 78.59 96.56 78.73 97.92 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1179,7 +1179,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 60.37 103.04 60.67 ; + RECT 121.9 81.45 123.28 81.75 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1187,7 +1187,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 51.53 103.04 51.83 ; + RECT 121.9 65.13 123.28 65.43 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1195,7 +1195,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 16.17 103.04 16.47 ; + RECT 121.9 80.09 123.28 80.39 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1203,7 +1203,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 8.01 103.04 8.31 ; + RECT 121.9 58.33 123.28 58.63 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1211,7 +1211,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 14.81 103.04 15.11 ; + RECT 121.9 24.33 123.28 24.63 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1219,7 +1219,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 57.65 103.04 57.95 ; + RECT 121.9 63.77 123.28 64.07 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1227,7 +1227,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.29 103.04 56.59 ; + RECT 121.9 78.73 123.28 79.03 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1235,7 +1235,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.01 103.04 59.31 ; + RECT 121.9 42.01 123.28 42.31 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1243,7 +1243,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.89 103.04 53.19 ; + RECT 121.9 54.25 123.28 54.55 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1251,7 +1251,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.73 103.04 62.03 ; + RECT 121.9 73.97 123.28 74.27 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1259,7 +1259,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 9.37 103.04 9.67 ; + RECT 121.9 47.45 123.28 47.75 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1267,7 +1267,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.17 103.04 50.47 ; + RECT 121.9 82.81 123.28 83.11 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1275,7 +1275,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.93 103.04 55.23 ; + RECT 121.9 32.49 123.28 32.79 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1283,7 +1283,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 35.21 103.04 35.51 ; + RECT 121.9 35.21 123.28 35.51 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1291,7 +1291,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 47.45 103.04 47.75 ; + RECT 121.9 33.85 123.28 34.15 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1299,15 +1299,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 5.29 103.04 5.59 ; + RECT 121.9 51.53 123.28 51.83 ; END END chanx_right_out[15] PIN chanx_right_out[16] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 99.75 0 99.89 1.36 ; + LAYER met3 ; + RECT 121.9 48.81 123.28 49.11 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1315,7 +1315,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 33.85 103.04 34.15 ; + RECT 121.9 50.17 123.28 50.47 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1323,7 +1323,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.09 103.04 29.39 ; + RECT 121.9 67.85 123.28 68.15 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1331,7 +1331,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 32.49 103.04 32.79 ; + RECT 121.9 29.77 123.28 30.07 ; END END chanx_right_out[19] PIN chanx_left_out[0] @@ -1339,7 +1339,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1355,15 +1355,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.07 63.92 4.21 65.28 ; + LAYER met3 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1371,7 +1371,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1386,8 +1386,8 @@ MACRO sb_1__0_ DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + LAYER met3 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1395,7 +1395,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 8.69 1.38 8.99 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1403,15 +1403,15 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.15 0 3.29 1.36 ; + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1419,7 +1419,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1427,7 +1427,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1435,7 +1435,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1443,7 +1443,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 16.17 1.38 16.47 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1451,7 +1451,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1459,7 +1459,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1467,7 +1467,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1475,7 +1475,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1483,7 +1483,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1491,7 +1491,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1499,7 +1499,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 11.41 1.38 11.71 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1507,7 +1507,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 22.29 1.38 22.59 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1515,7 +1515,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 49.53 80.24 49.83 81.6 ; + RECT 63.33 96.56 63.63 97.92 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1523,7 +1523,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 51.37 80.24 51.67 81.6 ; + RECT 61.49 96.56 61.79 97.92 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1531,7 +1531,7 @@ MACRO sb_1__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 98.83 63.92 98.97 65.28 ; + RECT 120.91 85.68 121.05 87.04 ; END END SC_OUT_BOT PIN VDD @@ -1540,45 +1540,53 @@ MACRO sb_1__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 102.56 2.48 103.04 2.96 ; + RECT 122.8 2.48 123.28 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 102.56 7.92 103.04 8.4 ; + RECT 122.8 7.92 123.28 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 102.56 13.36 103.04 13.84 ; + RECT 122.8 13.36 123.28 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 102.56 18.8 103.04 19.28 ; + RECT 122.8 18.8 123.28 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 102.56 24.24 103.04 24.72 ; + RECT 122.8 24.24 123.28 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 102.56 29.68 103.04 30.16 ; + RECT 122.8 29.68 123.28 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 102.56 35.12 103.04 35.6 ; + RECT 122.8 35.12 123.28 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 102.56 40.56 103.04 41.04 ; + RECT 122.8 40.56 123.28 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 102.56 46 103.04 46.48 ; + RECT 122.8 46 123.28 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 102.56 51.44 103.04 51.92 ; + RECT 122.8 51.44 123.28 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 102.56 56.88 103.04 57.36 ; + RECT 122.8 56.88 123.28 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 102.56 62.32 103.04 62.8 ; - RECT 18.4 67.76 18.88 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; - RECT 18.4 73.2 18.88 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; - RECT 18.4 78.64 18.88 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; + RECT 122.8 62.32 123.28 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 122.8 67.76 123.28 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 122.8 73.2 123.28 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 122.8 78.64 123.28 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 122.8 84.08 123.28 84.56 ; + RECT 27.6 89.52 28.08 90 ; + RECT 95.2 89.52 95.68 90 ; + RECT 27.6 94.96 28.08 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 81 29.74 81.6 ; - RECT 58.58 81 59.18 81.6 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 112.86 0 113.46 0.6 ; + RECT 112.86 86.44 113.46 87.04 ; + RECT 39.26 97.32 39.86 97.92 ; + RECT 68.7 97.32 69.3 97.92 ; LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 99.84 10.64 103.04 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 99.84 51.44 103.04 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 120.08 11.32 123.28 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 120.08 52.12 123.28 55.32 ; END END VDD PIN VSS @@ -1586,621 +1594,836 @@ MACRO sb_1__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 103.04 0.24 ; + RECT 0 0 123.28 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 102.56 5.2 103.04 5.68 ; + RECT 122.8 5.2 123.28 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 102.56 10.64 103.04 11.12 ; + RECT 122.8 10.64 123.28 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 102.56 16.08 103.04 16.56 ; + RECT 122.8 16.08 123.28 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 102.56 21.52 103.04 22 ; + RECT 122.8 21.52 123.28 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 102.56 26.96 103.04 27.44 ; + RECT 122.8 26.96 123.28 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 102.56 32.4 103.04 32.88 ; + RECT 122.8 32.4 123.28 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 102.56 37.84 103.04 38.32 ; + RECT 122.8 37.84 123.28 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 102.56 43.28 103.04 43.76 ; + RECT 122.8 43.28 123.28 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 102.56 48.72 103.04 49.2 ; + RECT 122.8 48.72 123.28 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 102.56 54.16 103.04 54.64 ; + RECT 122.8 54.16 123.28 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 102.56 59.6 103.04 60.08 ; - RECT 0 65.04 103.04 65.52 ; - RECT 18.4 70.48 18.88 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; - RECT 18.4 75.92 18.88 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 18.4 81.36 84.64 81.6 ; + RECT 122.8 59.6 123.28 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 122.8 65.04 123.28 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 122.8 70.48 123.28 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 122.8 75.92 123.28 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 122.8 81.36 123.28 81.84 ; + RECT 0 86.8 123.28 87.28 ; + RECT 27.6 92.24 28.08 92.72 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 27.6 97.68 95.68 97.92 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 81 44.46 81.6 ; - RECT 73.3 81 73.9 81.6 ; + RECT 9.82 0 10.42 0.6 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 86.44 10.42 87.04 ; + RECT 53.98 97.32 54.58 97.92 ; + RECT 83.42 97.32 84.02 97.92 ; LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 99.84 31.04 103.04 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 120.08 31.72 123.28 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 120.08 72.52 123.28 75.72 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; + END + END prog_clk__FEEDTHRU_1[0] + PIN prog_clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 57.43 96.56 57.57 97.92 ; + END + END prog_clk__FEEDTHRU_2[0] + PIN Test_en__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 70.77 0 70.91 1.36 ; + END + END Test_en__FEEDTHRU_0[0] + PIN Test_en__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 85.68 2.37 87.04 ; + END + END Test_en__FEEDTHRU_1[0] + PIN Test_en__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 119.99 85.68 120.13 87.04 ; + END + END Test_en__FEEDTHRU_2[0] + PIN clk__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 68.47 0 68.61 1.36 ; + END + END clk__FEEDTHRU_0[0] + PIN clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 116.31 85.68 116.45 87.04 ; + END + END clk__FEEDTHRU_1[0] + PIN clk__FEEDTHRU_2[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met3 ; + RECT 0 81.45 1.38 81.75 ; + END + END clk__FEEDTHRU_2[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 9.13 85.68 9.27 87.04 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 96.56 35.95 97.92 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 18.4 81.515 84.64 81.685 ; - RECT 83.72 78.795 84.64 78.965 ; - RECT 18.4 78.795 22.08 78.965 ; - RECT 83.72 76.075 84.64 76.245 ; - RECT 18.4 76.075 22.08 76.245 ; - RECT 83.72 73.355 84.64 73.525 ; - RECT 18.4 73.355 22.08 73.525 ; - RECT 83.72 70.635 84.64 70.805 ; - RECT 18.4 70.635 22.08 70.805 ; - RECT 80.96 67.915 84.64 68.085 ; - RECT 18.4 67.915 22.08 68.085 ; - RECT 80.96 65.195 103.04 65.365 ; - RECT 0 65.195 22.08 65.365 ; - RECT 102.12 62.475 103.04 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 102.12 59.755 103.04 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 102.12 57.035 103.04 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 102.12 54.315 103.04 54.485 ; + RECT 27.6 97.835 95.68 98.005 ; + RECT 94.76 95.115 95.68 95.285 ; + RECT 27.6 95.115 31.28 95.285 ; + RECT 94.76 92.395 95.68 92.565 ; + RECT 27.6 92.395 29.44 92.565 ; + RECT 94.76 89.675 95.68 89.845 ; + RECT 27.6 89.675 29.44 89.845 ; + RECT 92.92 86.955 123.28 87.125 ; + RECT 0 86.955 29.44 87.125 ; + RECT 122.36 84.235 123.28 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 122.36 81.515 123.28 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 122.36 78.795 123.28 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 122.36 76.075 123.28 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 122.36 73.355 123.28 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 122.36 70.635 123.28 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 122.36 67.915 123.28 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 122.36 65.195 123.28 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 122.36 62.475 123.28 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 122.36 59.755 123.28 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 122.36 57.035 123.28 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 122.36 54.315 123.28 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 102.12 51.595 103.04 51.765 ; + RECT 122.36 51.595 123.28 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 102.12 48.875 103.04 49.045 ; + RECT 122.36 48.875 123.28 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 102.12 46.155 103.04 46.325 ; + RECT 122.36 46.155 123.28 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 102.12 43.435 103.04 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 102.12 40.715 103.04 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 102.12 37.995 103.04 38.165 ; + RECT 122.36 43.435 123.28 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 122.36 40.715 123.28 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 122.36 37.995 123.28 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 102.12 35.275 103.04 35.445 ; + RECT 122.36 35.275 123.28 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 102.12 32.555 103.04 32.725 ; + RECT 122.36 32.555 123.28 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 102.12 29.835 103.04 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 102.12 27.115 103.04 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 101.2 24.395 103.04 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 101.2 21.675 103.04 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 102.12 18.955 103.04 19.125 ; + RECT 122.36 29.835 123.28 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 121.44 27.115 123.28 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 121.44 24.395 123.28 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 122.36 21.675 123.28 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 122.82 18.955 123.28 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 102.12 16.235 103.04 16.405 ; + RECT 122.82 16.235 123.28 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 102.12 13.515 103.04 13.685 ; + RECT 122.82 13.515 123.28 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 102.12 10.795 103.04 10.965 ; + RECT 122.82 10.795 123.28 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 102.12 8.075 103.04 8.245 ; + RECT 121.44 8.075 123.28 8.245 ; RECT 0 8.075 1.84 8.245 ; - RECT 102.12 5.355 103.04 5.525 ; - RECT 0 5.355 1.84 5.525 ; - RECT 102.12 2.635 103.04 2.805 ; + RECT 121.44 5.355 123.28 5.525 ; + RECT 0 5.355 3.68 5.525 ; + RECT 122.82 2.635 123.28 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 103.04 0.085 ; + RECT 0 -0.085 123.28 0.085 ; LAYER met2 ; - RECT 73.46 81.415 73.74 81.785 ; - RECT 44.02 81.415 44.3 81.785 ; - RECT 74.85 79.74 75.11 80.06 ; - RECT 59.67 79.74 59.93 80.06 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 65 98.55 65 98.55 63.64 99.25 63.64 99.25 65 102.76 65 102.76 0.28 101.09 0.28 101.09 1.64 100.39 1.64 100.39 0.28 100.17 0.28 100.17 1.64 99.47 1.64 99.47 0.28 99.25 0.28 99.25 1.64 98.55 1.64 98.55 0.28 98.33 0.28 98.33 1.64 97.63 1.64 97.63 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 2.87 65 2.87 63.64 3.57 63.64 3.57 65 3.79 65 3.79 63.64 4.49 63.64 4.49 65 4.71 65 4.71 63.64 5.41 63.64 5.41 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.73 81.32 21.73 79.96 22.43 79.96 22.43 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 25.41 81.32 25.41 79.96 26.11 79.96 26.11 81.32 38.75 81.32 38.75 79.96 39.45 79.96 39.45 81.32 39.67 81.32 39.67 79.96 40.37 79.96 40.37 81.32 40.59 81.32 40.59 79.96 41.29 79.96 41.29 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 49.33 81.32 49.33 79.96 50.03 79.96 50.03 81.32 50.25 81.32 50.25 79.96 50.95 79.96 50.95 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 54.85 81.32 54.85 79.96 55.55 79.96 55.55 81.32 55.77 81.32 55.77 79.96 56.47 79.96 56.47 81.32 56.69 81.32 56.69 79.96 57.39 79.96 57.39 81.32 58.07 81.32 58.07 79.96 58.77 79.96 58.77 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 62.21 81.32 62.21 79.96 62.91 79.96 62.91 81.32 63.59 81.32 63.59 79.96 64.29 79.96 64.29 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 65.43 81.32 65.43 79.96 66.13 79.96 66.13 81.32 66.35 81.32 66.35 79.96 67.05 79.96 67.05 81.32 67.73 81.32 67.73 79.96 68.43 79.96 68.43 81.32 68.65 81.32 68.65 79.96 69.35 79.96 69.35 81.32 69.57 81.32 69.57 79.96 70.27 79.96 70.27 81.32 70.49 81.32 70.49 79.96 71.19 79.96 71.19 81.32 71.41 81.32 71.41 79.96 72.11 79.96 72.11 81.32 72.33 81.32 72.33 79.96 73.03 79.96 73.03 81.32 74.17 81.32 74.17 79.96 74.87 79.96 74.87 81.32 75.09 81.32 75.09 79.96 75.79 79.96 75.79 81.32 76.01 81.32 76.01 79.96 76.71 79.96 76.71 81.32 77.39 81.32 77.39 79.96 78.09 79.96 78.09 81.32 ; + RECT 83.58 97.735 83.86 98.105 ; + RECT 54.14 97.735 54.42 98.105 ; + RECT 36.21 96.06 36.47 96.38 ; + RECT 9.98 86.855 10.26 87.225 ; + RECT 17.35 85.18 17.61 85.5 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + RECT 9.98 -0.185 10.26 0.185 ; + POLYGON 95.4 97.64 95.4 86.76 116.03 86.76 116.03 85.4 116.73 85.4 116.73 86.76 119.71 86.76 119.71 85.4 120.41 85.4 120.41 86.76 120.63 86.76 120.63 85.4 121.33 85.4 121.33 86.76 123 86.76 123 0.28 71.19 0.28 71.19 1.64 70.49 1.64 70.49 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 0.28 0.28 0.28 86.76 1.95 86.76 1.95 85.4 2.65 85.4 2.65 86.76 5.17 86.76 5.17 85.4 5.87 85.4 5.87 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 7.93 86.76 7.93 85.4 8.63 85.4 8.63 86.76 8.85 86.76 8.85 85.4 9.55 85.4 9.55 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 11.61 86.76 11.61 85.4 12.31 85.4 12.31 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 17.59 86.76 17.59 85.4 18.29 85.4 18.29 86.76 27.88 86.76 27.88 97.64 34.61 97.64 34.61 96.28 35.31 96.28 35.31 97.64 35.53 97.64 35.53 96.28 36.23 96.28 36.23 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 55.31 97.64 55.31 96.28 56.01 96.28 56.01 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.53 97.64 58.53 96.28 59.23 96.28 59.23 97.64 59.45 97.64 59.45 96.28 60.15 96.28 60.15 97.64 60.37 97.64 60.37 96.28 61.07 96.28 61.07 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.27 97.64 67.27 96.28 67.97 96.28 67.97 97.64 68.19 97.64 68.19 96.28 68.89 96.28 68.89 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.95 97.64 70.95 96.28 71.65 96.28 71.65 97.64 71.87 97.64 71.87 96.28 72.57 96.28 72.57 97.64 72.79 97.64 72.79 96.28 73.49 96.28 73.49 97.64 73.71 97.64 73.71 96.28 74.41 96.28 74.41 97.64 74.63 97.64 74.63 96.28 75.33 96.28 75.33 97.64 75.55 97.64 75.55 96.28 76.25 96.28 76.25 97.64 76.47 97.64 76.47 96.28 77.17 96.28 77.17 97.64 77.39 97.64 77.39 96.28 78.09 96.28 78.09 97.64 78.31 97.64 78.31 96.28 79.01 96.28 79.01 97.64 79.23 97.64 79.23 96.28 79.93 96.28 79.93 97.64 80.15 97.64 80.15 96.28 80.85 96.28 80.85 97.64 81.07 97.64 81.07 96.28 81.77 96.28 81.77 97.64 82.45 97.64 82.45 96.28 83.15 96.28 83.15 97.64 84.29 97.64 84.29 96.28 84.99 96.28 84.99 97.64 85.21 97.64 85.21 96.28 85.91 96.28 85.91 97.64 86.13 97.64 86.13 96.28 86.83 96.28 86.83 97.64 87.51 97.64 87.51 96.28 88.21 96.28 88.21 97.64 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 64.88 102.64 64.88 102.64 0.4 98.99 0.4 98.99 1.76 97.89 1.76 97.89 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 24.29 81.2 24.29 79.84 25.39 79.84 25.39 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 49.13 81.2 49.13 79.84 50.23 79.84 50.23 81.2 50.97 81.2 50.97 79.84 52.07 79.84 52.07 81.2 55.57 81.2 55.57 79.84 56.67 79.84 56.67 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 60.17 81.2 60.17 79.84 61.27 79.84 61.27 81.2 62.01 81.2 62.01 79.84 63.11 79.84 63.11 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 95.28 97.52 95.28 86.64 112.46 86.64 112.46 86.04 113.86 86.04 113.86 86.64 122.88 86.64 122.88 0.4 113.86 0.4 113.86 1 112.46 1 112.46 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 10.82 0.4 10.82 1 9.42 1 9.42 0.4 0.4 0.4 0.4 86.64 9.42 86.64 9.42 86.04 10.82 86.04 10.82 86.64 28 86.64 28 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 65.69 97.52 65.69 96.16 66.79 96.16 66.79 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; LAYER met3 ; - POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; - POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 101.81 42.99 101.81 42.71 101.26 42.71 101.26 42.69 61.95 42.69 61.95 42.99 ; - POLYGON 101.81 36.19 101.81 35.91 101.26 35.91 101.26 35.89 92.77 35.89 92.77 36.19 ; - POLYGON 2.03 25.32 2.03 25.31 63.63 25.31 63.63 25.01 2.03 25.01 2.03 25 1.65 25 1.65 25.32 ; - POLYGON 101.26 19.87 101.26 19.85 101.81 19.85 101.81 19.57 74.83 19.57 74.83 19.87 ; - POLYGON 101.26 18.51 101.26 18.49 101.81 18.49 101.81 18.21 88.17 18.21 88.17 18.51 ; - POLYGON 1.99 15.11 1.99 14.43 5.21 14.43 5.21 14.13 1.69 14.13 1.69 14.41 1.78 14.41 1.78 15.11 ; - POLYGON 7.05 8.99 7.05 8.69 1.99 8.69 1.99 8.01 1.78 8.01 1.78 8.71 1.69 8.71 1.69 8.99 ; - POLYGON 101.81 7.63 101.81 7.35 101.26 7.35 101.26 7.33 65.17 7.33 65.17 7.63 ; - POLYGON 11.65 6.27 11.65 5.97 1.23 5.97 1.23 6.25 1.78 6.25 1.78 6.27 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 64.88 102.64 64.88 102.64 62.43 101.26 62.43 101.26 61.33 102.64 61.33 102.64 61.07 101.26 61.07 101.26 59.97 102.64 59.97 102.64 59.71 101.26 59.71 101.26 58.61 102.64 58.61 102.64 58.35 101.26 58.35 101.26 57.25 102.64 57.25 102.64 56.99 101.26 56.99 101.26 55.89 102.64 55.89 102.64 55.63 101.26 55.63 101.26 54.53 102.64 54.53 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 38.63 101.26 38.63 101.26 37.53 102.64 37.53 102.64 37.27 101.26 37.27 101.26 36.17 102.64 36.17 102.64 35.91 101.26 35.91 101.26 34.81 102.64 34.81 102.64 34.55 101.26 34.55 101.26 33.45 102.64 33.45 102.64 33.19 101.26 33.19 101.26 32.09 102.64 32.09 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 27.75 101.26 27.75 101.26 26.65 102.64 26.65 102.64 26.39 101.26 26.39 101.26 25.29 102.64 25.29 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 19.59 101.26 19.59 101.26 18.49 102.64 18.49 102.64 18.23 101.26 18.23 101.26 17.13 102.64 17.13 102.64 16.87 101.26 16.87 101.26 15.77 102.64 15.77 102.64 15.51 101.26 15.51 101.26 14.41 102.64 14.41 102.64 14.15 101.26 14.15 101.26 13.05 102.64 13.05 102.64 12.79 101.26 12.79 101.26 11.69 102.64 11.69 102.64 11.43 101.26 11.43 101.26 10.33 102.64 10.33 102.64 10.07 101.26 10.07 101.26 8.97 102.64 8.97 102.64 8.71 101.26 8.71 101.26 7.61 102.64 7.61 102.64 7.35 101.26 7.35 101.26 6.25 102.64 6.25 102.64 5.99 101.26 5.99 101.26 4.89 102.64 4.89 102.64 4.63 101.26 4.63 101.26 3.53 102.64 3.53 102.64 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 18.8 64.88 18.8 81.2 ; + POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; + POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; + POLYGON 10.285 87.205 10.285 87.2 10.5 87.2 10.5 86.88 10.285 86.88 10.285 86.875 9.955 86.875 9.955 86.88 9.74 86.88 9.74 87.2 9.955 87.2 9.955 87.205 ; + POLYGON 11.65 67.47 11.65 67.17 1.99 67.17 1.99 66.49 1.78 66.49 1.78 67.19 1.69 67.19 1.69 67.47 ; + POLYGON 87.55 64.75 87.55 64.45 1.78 64.45 1.78 64.47 1.23 64.47 1.23 64.75 ; + POLYGON 78.35 56.59 78.35 56.29 1.99 56.29 1.99 55.61 1.78 55.61 1.78 56.31 1.69 56.31 1.69 56.59 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 10.285 0.165 10.285 0.16 10.5 0.16 10.5 -0.16 10.285 -0.16 10.285 -0.165 9.955 -0.165 9.955 -0.16 9.74 -0.16 9.74 0.16 9.955 0.16 9.955 0.165 ; + POLYGON 95.28 97.52 95.28 86.64 122.88 86.64 122.88 83.51 121.5 83.51 121.5 82.41 122.88 82.41 122.88 82.15 121.5 82.15 121.5 81.05 122.88 81.05 122.88 80.79 121.5 80.79 121.5 79.69 122.88 79.69 122.88 79.43 121.5 79.43 121.5 78.33 122.88 78.33 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 72.63 121.5 72.63 121.5 71.53 122.88 71.53 122.88 71.27 121.5 71.27 121.5 70.17 122.88 70.17 122.88 69.91 121.5 69.91 121.5 68.81 122.88 68.81 122.88 68.55 121.5 68.55 121.5 67.45 122.88 67.45 122.88 67.19 121.5 67.19 121.5 66.09 122.88 66.09 122.88 65.83 121.5 65.83 121.5 64.73 122.88 64.73 122.88 64.47 121.5 64.47 121.5 63.37 122.88 63.37 122.88 62.43 121.5 62.43 121.5 61.33 122.88 61.33 122.88 61.07 121.5 61.07 121.5 59.97 122.88 59.97 122.88 59.03 121.5 59.03 121.5 57.93 122.88 57.93 122.88 57.67 121.5 57.67 121.5 56.57 122.88 56.57 122.88 56.31 121.5 56.31 121.5 55.21 122.88 55.21 122.88 54.95 121.5 54.95 121.5 53.85 122.88 53.85 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 52.23 121.5 52.23 121.5 51.13 122.88 51.13 122.88 50.87 121.5 50.87 121.5 49.77 122.88 49.77 122.88 49.51 121.5 49.51 121.5 48.41 122.88 48.41 122.88 48.15 121.5 48.15 121.5 47.05 122.88 47.05 122.88 46.79 121.5 46.79 121.5 45.69 122.88 45.69 122.88 45.43 121.5 45.43 121.5 44.33 122.88 44.33 122.88 44.07 121.5 44.07 121.5 42.97 122.88 42.97 122.88 42.71 121.5 42.71 121.5 41.61 122.88 41.61 122.88 41.35 121.5 41.35 121.5 40.25 122.88 40.25 122.88 39.99 121.5 39.99 121.5 38.89 122.88 38.89 122.88 38.63 121.5 38.63 121.5 37.53 122.88 37.53 122.88 35.91 121.5 35.91 121.5 34.81 122.88 34.81 122.88 34.55 121.5 34.55 121.5 33.45 122.88 33.45 122.88 33.19 121.5 33.19 121.5 32.09 122.88 32.09 122.88 31.83 121.5 31.83 121.5 30.73 122.88 30.73 122.88 30.47 121.5 30.47 121.5 29.37 122.88 29.37 122.88 29.11 121.5 29.11 121.5 28.01 122.88 28.01 122.88 27.75 121.5 27.75 121.5 26.65 122.88 26.65 122.88 26.39 121.5 26.39 121.5 25.29 122.88 25.29 122.88 25.03 121.5 25.03 121.5 23.93 122.88 23.93 122.88 23.67 121.5 23.67 121.5 22.57 122.88 22.57 122.88 22.31 121.5 22.31 121.5 21.21 122.88 21.21 122.88 14.15 121.5 14.15 121.5 13.05 122.88 13.05 122.88 12.79 121.5 12.79 121.5 11.69 122.88 11.69 122.88 11.43 121.5 11.43 121.5 10.33 122.88 10.33 122.88 10.07 121.5 10.07 121.5 8.97 122.88 8.97 122.88 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 28 86.64 28 97.52 ; LAYER met5 ; - POLYGON 83.04 80 83.04 63.68 101.44 63.68 101.44 56.24 98.24 56.24 98.24 49.84 101.44 49.84 101.44 35.84 98.24 35.84 98.24 29.44 101.44 29.44 101.44 15.44 98.24 15.44 98.24 9.04 101.44 9.04 101.44 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 20 63.68 20 80 ; + POLYGON 94.08 96.32 94.08 85.44 121.68 85.44 121.68 77.32 118.48 77.32 118.48 70.92 121.68 70.92 121.68 56.92 118.48 56.92 118.48 50.52 121.68 50.52 121.68 36.52 118.48 36.52 118.48 30.12 121.68 30.12 121.68 16.12 118.48 16.12 118.48 9.72 121.68 9.72 121.68 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 29.2 85.44 29.2 96.32 ; LAYER met1 ; - RECT 33.315 65.77 33.605 66 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 18.68 65.8 18.68 67.48 19.16 67.48 19.16 68.52 18.68 68.52 18.68 70.2 19.16 70.2 19.16 71.24 18.68 71.24 18.68 72.92 19.16 72.92 19.16 73.96 18.68 73.96 18.68 75.64 19.16 75.64 19.16 76.68 18.68 76.68 18.68 78.36 19.16 78.36 19.16 79.4 18.68 79.4 18.68 81.08 ; - POLYGON 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 102.28 16.84 102.28 15.8 102.76 15.8 102.76 14.12 102.28 14.12 102.28 13.08 102.76 13.08 102.76 11.4 102.28 11.4 102.28 10.36 102.76 10.36 102.76 8.68 102.28 8.68 102.28 7.64 102.76 7.64 102.76 5.96 102.28 5.96 102.28 4.92 102.76 4.92 102.76 3.24 102.28 3.24 102.28 2.2 102.76 2.2 102.76 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 27.88 87.56 27.88 89.24 28.36 89.24 28.36 90.28 27.88 90.28 27.88 91.96 28.36 91.96 28.36 93 27.88 93 27.88 94.68 28.36 94.68 28.36 95.72 27.88 95.72 27.88 97.4 ; + POLYGON 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 122.52 11.4 122.52 10.36 123 10.36 123 8.68 122.52 8.68 122.52 7.64 123 7.64 123 5.96 122.52 5.96 122.52 4.92 123 4.92 123 3.24 122.52 3.24 122.52 2.2 123 2.2 123 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 84.47 81.43 84.47 65.11 102.87 65.11 102.87 0.17 0.17 0.17 0.17 65.11 18.57 65.11 18.57 81.43 ; + POLYGON 95.51 97.75 95.51 86.87 123.11 86.87 123.11 0.17 0.17 0.17 0.17 86.87 27.77 86.87 27.77 97.75 ; LAYER mcon ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; - RECT 19.005 78.795 19.175 78.965 ; - RECT 18.545 78.795 18.715 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; - RECT 19.005 76.075 19.175 76.245 ; - RECT 18.545 76.075 18.715 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; - RECT 19.005 73.355 19.175 73.525 ; - RECT 18.545 73.355 18.715 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; - RECT 19.005 70.635 19.175 70.805 ; - RECT 18.545 70.635 18.715 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; - RECT 19.005 67.915 19.175 68.085 ; - RECT 18.545 67.915 18.715 68.085 ; - RECT 102.725 65.195 102.895 65.365 ; - RECT 102.265 65.195 102.435 65.365 ; - RECT 101.805 65.195 101.975 65.365 ; - RECT 101.345 65.195 101.515 65.365 ; - RECT 100.885 65.195 101.055 65.365 ; - RECT 100.425 65.195 100.595 65.365 ; - RECT 99.965 65.195 100.135 65.365 ; - RECT 99.505 65.195 99.675 65.365 ; - RECT 99.045 65.195 99.215 65.365 ; - RECT 98.585 65.195 98.755 65.365 ; - RECT 98.125 65.195 98.295 65.365 ; - RECT 97.665 65.195 97.835 65.365 ; - RECT 97.205 65.195 97.375 65.365 ; - RECT 96.745 65.195 96.915 65.365 ; - RECT 96.285 65.195 96.455 65.365 ; - RECT 95.825 65.195 95.995 65.365 ; - RECT 95.365 65.195 95.535 65.365 ; - RECT 94.905 65.195 95.075 65.365 ; - RECT 94.445 65.195 94.615 65.365 ; - RECT 93.985 65.195 94.155 65.365 ; - RECT 93.525 65.195 93.695 65.365 ; - RECT 93.065 65.195 93.235 65.365 ; - RECT 92.605 65.195 92.775 65.365 ; - RECT 92.145 65.195 92.315 65.365 ; - RECT 91.685 65.195 91.855 65.365 ; - RECT 91.225 65.195 91.395 65.365 ; - RECT 90.765 65.195 90.935 65.365 ; - RECT 90.305 65.195 90.475 65.365 ; - RECT 89.845 65.195 90.015 65.365 ; - RECT 89.385 65.195 89.555 65.365 ; - RECT 88.925 65.195 89.095 65.365 ; - RECT 88.465 65.195 88.635 65.365 ; - RECT 88.005 65.195 88.175 65.365 ; - RECT 87.545 65.195 87.715 65.365 ; - RECT 87.085 65.195 87.255 65.365 ; - RECT 86.625 65.195 86.795 65.365 ; - RECT 86.165 65.195 86.335 65.365 ; - RECT 85.705 65.195 85.875 65.365 ; - RECT 85.245 65.195 85.415 65.365 ; - RECT 84.785 65.195 84.955 65.365 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; - RECT 83.405 65.195 83.575 65.365 ; - RECT 82.945 65.195 83.115 65.365 ; - RECT 82.485 65.195 82.655 65.365 ; - RECT 82.025 65.195 82.195 65.365 ; - RECT 81.565 65.195 81.735 65.365 ; - RECT 81.105 65.195 81.275 65.365 ; - RECT 80.645 65.195 80.815 65.365 ; - RECT 80.185 65.195 80.355 65.365 ; - RECT 79.725 65.195 79.895 65.365 ; - RECT 79.265 65.195 79.435 65.365 ; - RECT 78.805 65.195 78.975 65.365 ; - RECT 78.345 65.195 78.515 65.365 ; - RECT 77.885 65.195 78.055 65.365 ; - RECT 77.425 65.195 77.595 65.365 ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; + RECT 28.205 95.115 28.375 95.285 ; + RECT 27.745 95.115 27.915 95.285 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; + RECT 28.205 92.395 28.375 92.565 ; + RECT 27.745 92.395 27.915 92.565 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; + RECT 28.205 89.675 28.375 89.845 ; + RECT 27.745 89.675 27.915 89.845 ; + RECT 122.965 86.955 123.135 87.125 ; + RECT 122.505 86.955 122.675 87.125 ; + RECT 122.045 86.955 122.215 87.125 ; + RECT 121.585 86.955 121.755 87.125 ; + RECT 121.125 86.955 121.295 87.125 ; + RECT 120.665 86.955 120.835 87.125 ; + RECT 120.205 86.955 120.375 87.125 ; + RECT 119.745 86.955 119.915 87.125 ; + RECT 119.285 86.955 119.455 87.125 ; + RECT 118.825 86.955 118.995 87.125 ; + RECT 118.365 86.955 118.535 87.125 ; + RECT 117.905 86.955 118.075 87.125 ; + RECT 117.445 86.955 117.615 87.125 ; + RECT 116.985 86.955 117.155 87.125 ; + RECT 116.525 86.955 116.695 87.125 ; + RECT 116.065 86.955 116.235 87.125 ; + RECT 115.605 86.955 115.775 87.125 ; + RECT 115.145 86.955 115.315 87.125 ; + RECT 114.685 86.955 114.855 87.125 ; + RECT 114.225 86.955 114.395 87.125 ; + RECT 113.765 86.955 113.935 87.125 ; + RECT 113.305 86.955 113.475 87.125 ; + RECT 112.845 86.955 113.015 87.125 ; + RECT 112.385 86.955 112.555 87.125 ; + RECT 111.925 86.955 112.095 87.125 ; + RECT 111.465 86.955 111.635 87.125 ; + RECT 111.005 86.955 111.175 87.125 ; + RECT 110.545 86.955 110.715 87.125 ; + RECT 110.085 86.955 110.255 87.125 ; + RECT 109.625 86.955 109.795 87.125 ; + RECT 109.165 86.955 109.335 87.125 ; + RECT 108.705 86.955 108.875 87.125 ; + RECT 108.245 86.955 108.415 87.125 ; + RECT 107.785 86.955 107.955 87.125 ; + RECT 107.325 86.955 107.495 87.125 ; + RECT 106.865 86.955 107.035 87.125 ; + RECT 106.405 86.955 106.575 87.125 ; + RECT 105.945 86.955 106.115 87.125 ; + RECT 105.485 86.955 105.655 87.125 ; + RECT 105.025 86.955 105.195 87.125 ; + RECT 104.565 86.955 104.735 87.125 ; + RECT 104.105 86.955 104.275 87.125 ; + RECT 103.645 86.955 103.815 87.125 ; + RECT 103.185 86.955 103.355 87.125 ; + RECT 102.725 86.955 102.895 87.125 ; + RECT 102.265 86.955 102.435 87.125 ; + RECT 101.805 86.955 101.975 87.125 ; + RECT 101.345 86.955 101.515 87.125 ; + RECT 100.885 86.955 101.055 87.125 ; + RECT 100.425 86.955 100.595 87.125 ; + RECT 99.965 86.955 100.135 87.125 ; + RECT 99.505 86.955 99.675 87.125 ; + RECT 99.045 86.955 99.215 87.125 ; + RECT 98.585 86.955 98.755 87.125 ; + RECT 98.125 86.955 98.295 87.125 ; + RECT 97.665 86.955 97.835 87.125 ; + RECT 97.205 86.955 97.375 87.125 ; + RECT 96.745 86.955 96.915 87.125 ; + RECT 96.285 86.955 96.455 87.125 ; + RECT 95.825 86.955 95.995 87.125 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 94.445 86.955 94.615 87.125 ; + RECT 93.985 86.955 94.155 87.125 ; + RECT 93.525 86.955 93.695 87.125 ; + RECT 93.065 86.955 93.235 87.125 ; + RECT 92.605 86.955 92.775 87.125 ; + RECT 92.145 86.955 92.315 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; + RECT 90.765 86.955 90.935 87.125 ; + RECT 90.305 86.955 90.475 87.125 ; + RECT 89.845 86.955 90.015 87.125 ; + RECT 89.385 86.955 89.555 87.125 ; + RECT 88.925 86.955 89.095 87.125 ; + RECT 88.465 86.955 88.635 87.125 ; + RECT 88.005 86.955 88.175 87.125 ; + RECT 87.545 86.955 87.715 87.125 ; + RECT 87.085 86.955 87.255 87.125 ; + RECT 86.625 86.955 86.795 87.125 ; + RECT 86.165 86.955 86.335 87.125 ; + RECT 85.705 86.955 85.875 87.125 ; + RECT 85.245 86.955 85.415 87.125 ; + RECT 84.785 86.955 84.955 87.125 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 83.405 86.955 83.575 87.125 ; + RECT 82.945 86.955 83.115 87.125 ; + RECT 82.485 86.955 82.655 87.125 ; + RECT 82.025 86.955 82.195 87.125 ; + RECT 81.565 86.955 81.735 87.125 ; + RECT 81.105 86.955 81.275 87.125 ; + RECT 80.645 86.955 80.815 87.125 ; + RECT 80.185 86.955 80.355 87.125 ; + RECT 79.725 86.955 79.895 87.125 ; + RECT 79.265 86.955 79.435 87.125 ; + RECT 78.805 86.955 78.975 87.125 ; + RECT 78.345 86.955 78.515 87.125 ; + RECT 77.885 86.955 78.055 87.125 ; + RECT 77.425 86.955 77.595 87.125 ; + RECT 76.965 86.955 77.135 87.125 ; + RECT 76.505 86.955 76.675 87.125 ; + RECT 76.045 86.955 76.215 87.125 ; + RECT 75.585 86.955 75.755 87.125 ; + RECT 75.125 86.955 75.295 87.125 ; + RECT 74.665 86.955 74.835 87.125 ; + RECT 74.205 86.955 74.375 87.125 ; + RECT 73.745 86.955 73.915 87.125 ; + RECT 73.285 86.955 73.455 87.125 ; + RECT 72.825 86.955 72.995 87.125 ; + RECT 72.365 86.955 72.535 87.125 ; + RECT 71.905 86.955 72.075 87.125 ; + RECT 71.445 86.955 71.615 87.125 ; + RECT 70.985 86.955 71.155 87.125 ; + RECT 70.525 86.955 70.695 87.125 ; + RECT 70.065 86.955 70.235 87.125 ; + RECT 69.605 86.955 69.775 87.125 ; + RECT 69.145 86.955 69.315 87.125 ; + RECT 68.685 86.955 68.855 87.125 ; + RECT 68.225 86.955 68.395 87.125 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 122.965 84.235 123.135 84.405 ; + RECT 122.505 84.235 122.675 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 122.965 81.515 123.135 81.685 ; + RECT 122.505 81.515 122.675 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 122.965 78.795 123.135 78.965 ; + RECT 122.505 78.795 122.675 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 122.965 76.075 123.135 76.245 ; + RECT 122.505 76.075 122.675 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 122.965 73.355 123.135 73.525 ; + RECT 122.505 73.355 122.675 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 122.965 70.635 123.135 70.805 ; + RECT 122.505 70.635 122.675 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 122.965 67.915 123.135 68.085 ; + RECT 122.505 67.915 122.675 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 122.965 65.195 123.135 65.365 ; + RECT 122.505 65.195 122.675 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 102.725 62.475 102.895 62.645 ; - RECT 102.265 62.475 102.435 62.645 ; + RECT 122.965 62.475 123.135 62.645 ; + RECT 122.505 62.475 122.675 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 102.725 59.755 102.895 59.925 ; - RECT 102.265 59.755 102.435 59.925 ; + RECT 122.965 59.755 123.135 59.925 ; + RECT 122.505 59.755 122.675 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 102.725 57.035 102.895 57.205 ; - RECT 102.265 57.035 102.435 57.205 ; + RECT 122.965 57.035 123.135 57.205 ; + RECT 122.505 57.035 122.675 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 102.725 54.315 102.895 54.485 ; - RECT 102.265 54.315 102.435 54.485 ; + RECT 122.965 54.315 123.135 54.485 ; + RECT 122.505 54.315 122.675 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 102.725 51.595 102.895 51.765 ; - RECT 102.265 51.595 102.435 51.765 ; + RECT 122.965 51.595 123.135 51.765 ; + RECT 122.505 51.595 122.675 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 102.725 48.875 102.895 49.045 ; - RECT 102.265 48.875 102.435 49.045 ; + RECT 122.965 48.875 123.135 49.045 ; + RECT 122.505 48.875 122.675 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 102.725 46.155 102.895 46.325 ; - RECT 102.265 46.155 102.435 46.325 ; + RECT 122.965 46.155 123.135 46.325 ; + RECT 122.505 46.155 122.675 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 102.725 43.435 102.895 43.605 ; - RECT 102.265 43.435 102.435 43.605 ; + RECT 122.965 43.435 123.135 43.605 ; + RECT 122.505 43.435 122.675 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 102.725 40.715 102.895 40.885 ; - RECT 102.265 40.715 102.435 40.885 ; + RECT 122.965 40.715 123.135 40.885 ; + RECT 122.505 40.715 122.675 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 102.725 37.995 102.895 38.165 ; - RECT 102.265 37.995 102.435 38.165 ; + RECT 122.965 37.995 123.135 38.165 ; + RECT 122.505 37.995 122.675 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 102.725 35.275 102.895 35.445 ; - RECT 102.265 35.275 102.435 35.445 ; + RECT 122.965 35.275 123.135 35.445 ; + RECT 122.505 35.275 122.675 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 102.725 32.555 102.895 32.725 ; - RECT 102.265 32.555 102.435 32.725 ; + RECT 122.965 32.555 123.135 32.725 ; + RECT 122.505 32.555 122.675 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 102.725 29.835 102.895 30.005 ; - RECT 102.265 29.835 102.435 30.005 ; + RECT 122.965 29.835 123.135 30.005 ; + RECT 122.505 29.835 122.675 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 102.725 27.115 102.895 27.285 ; - RECT 102.265 27.115 102.435 27.285 ; + RECT 122.965 27.115 123.135 27.285 ; + RECT 122.505 27.115 122.675 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 102.725 24.395 102.895 24.565 ; - RECT 102.265 24.395 102.435 24.565 ; + RECT 122.965 24.395 123.135 24.565 ; + RECT 122.505 24.395 122.675 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 102.725 21.675 102.895 21.845 ; - RECT 102.265 21.675 102.435 21.845 ; + RECT 122.965 21.675 123.135 21.845 ; + RECT 122.505 21.675 122.675 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 102.725 18.955 102.895 19.125 ; - RECT 102.265 18.955 102.435 19.125 ; + RECT 122.965 18.955 123.135 19.125 ; + RECT 122.505 18.955 122.675 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 102.725 16.235 102.895 16.405 ; - RECT 102.265 16.235 102.435 16.405 ; + RECT 122.965 16.235 123.135 16.405 ; + RECT 122.505 16.235 122.675 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 102.725 13.515 102.895 13.685 ; - RECT 102.265 13.515 102.435 13.685 ; + RECT 122.965 13.515 123.135 13.685 ; + RECT 122.505 13.515 122.675 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 102.725 10.795 102.895 10.965 ; - RECT 102.265 10.795 102.435 10.965 ; + RECT 122.965 10.795 123.135 10.965 ; + RECT 122.505 10.795 122.675 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 102.725 8.075 102.895 8.245 ; - RECT 102.265 8.075 102.435 8.245 ; + RECT 122.965 8.075 123.135 8.245 ; + RECT 122.505 8.075 122.675 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 102.725 5.355 102.895 5.525 ; - RECT 102.265 5.355 102.435 5.525 ; + RECT 122.965 5.355 123.135 5.525 ; + RECT 122.505 5.355 122.675 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 102.725 2.635 102.895 2.805 ; - RECT 102.265 2.635 102.435 2.805 ; + RECT 122.965 2.635 123.135 2.805 ; + RECT 122.505 2.635 122.675 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 122.965 -0.085 123.135 0.085 ; + RECT 122.505 -0.085 122.675 0.085 ; + RECT 122.045 -0.085 122.215 0.085 ; + RECT 121.585 -0.085 121.755 0.085 ; + RECT 121.125 -0.085 121.295 0.085 ; + RECT 120.665 -0.085 120.835 0.085 ; + RECT 120.205 -0.085 120.375 0.085 ; + RECT 119.745 -0.085 119.915 0.085 ; + RECT 119.285 -0.085 119.455 0.085 ; + RECT 118.825 -0.085 118.995 0.085 ; + RECT 118.365 -0.085 118.535 0.085 ; + RECT 117.905 -0.085 118.075 0.085 ; + RECT 117.445 -0.085 117.615 0.085 ; + RECT 116.985 -0.085 117.155 0.085 ; + RECT 116.525 -0.085 116.695 0.085 ; + RECT 116.065 -0.085 116.235 0.085 ; + RECT 115.605 -0.085 115.775 0.085 ; + RECT 115.145 -0.085 115.315 0.085 ; + RECT 114.685 -0.085 114.855 0.085 ; + RECT 114.225 -0.085 114.395 0.085 ; + RECT 113.765 -0.085 113.935 0.085 ; + RECT 113.305 -0.085 113.475 0.085 ; + RECT 112.845 -0.085 113.015 0.085 ; + RECT 112.385 -0.085 112.555 0.085 ; + RECT 111.925 -0.085 112.095 0.085 ; + RECT 111.465 -0.085 111.635 0.085 ; + RECT 111.005 -0.085 111.175 0.085 ; + RECT 110.545 -0.085 110.715 0.085 ; + RECT 110.085 -0.085 110.255 0.085 ; + RECT 109.625 -0.085 109.795 0.085 ; + RECT 109.165 -0.085 109.335 0.085 ; + RECT 108.705 -0.085 108.875 0.085 ; + RECT 108.245 -0.085 108.415 0.085 ; + RECT 107.785 -0.085 107.955 0.085 ; + RECT 107.325 -0.085 107.495 0.085 ; + RECT 106.865 -0.085 107.035 0.085 ; + RECT 106.405 -0.085 106.575 0.085 ; + RECT 105.945 -0.085 106.115 0.085 ; + RECT 105.485 -0.085 105.655 0.085 ; + RECT 105.025 -0.085 105.195 0.085 ; + RECT 104.565 -0.085 104.735 0.085 ; + RECT 104.105 -0.085 104.275 0.085 ; + RECT 103.645 -0.085 103.815 0.085 ; + RECT 103.185 -0.085 103.355 0.085 ; RECT 102.725 -0.085 102.895 0.085 ; RECT 102.265 -0.085 102.435 0.085 ; RECT 101.805 -0.085 101.975 0.085 ; @@ -2426,41 +2649,48 @@ MACRO sb_1__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 71.685 79.825 71.835 79.975 ; - RECT 68.005 79.825 68.155 79.975 ; - RECT 73.525 65.205 73.675 65.355 ; - RECT 44.085 65.205 44.235 65.355 ; - RECT 3.145 63.505 3.295 63.655 ; - RECT 100.665 1.625 100.815 1.775 ; - RECT 98.825 1.625 98.975 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 63.865 96.145 64.015 96.295 ; + RECT 83.645 86.965 83.795 87.115 ; + RECT 54.205 86.965 54.355 87.115 ; + RECT 10.045 86.965 10.195 87.115 ; + RECT 119.985 85.265 120.135 85.415 ; + RECT 17.865 85.265 18.015 85.415 ; + RECT 5.445 85.265 5.595 85.415 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; + RECT 10.045 -0.075 10.195 0.075 ; LAYER via2 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 1.28 59.74 1.48 59.94 ; - RECT 101.1 59.06 101.3 59.26 ; - RECT 1.28 44.1 1.48 44.3 ; - RECT 1.74 42.74 1.94 42.94 ; - RECT 1.28 34.58 1.48 34.78 ; - RECT 101.1 33.9 101.3 34.1 ; - RECT 1.74 25.74 1.94 25.94 ; - RECT 1.74 17.58 1.94 17.78 ; - RECT 101.56 16.22 101.76 16.42 ; - RECT 1.28 10.78 1.48 10.98 ; - RECT 1.28 5.34 1.48 5.54 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 86.94 10.22 87.14 ; + RECT 1.28 82.86 1.48 83.06 ; + RECT 1.74 75.38 1.94 75.58 ; + RECT 1.28 65.18 1.48 65.38 ; + RECT 121.8 48.86 122 49.06 ; + RECT 1.74 46.14 1.94 46.34 ; + RECT 121.8 43.42 122 43.62 ; + RECT 121.34 35.26 121.54 35.46 ; + RECT 121.8 31.18 122 31.38 ; + RECT 1.74 28.46 1.94 28.66 ; + RECT 121.8 23.02 122 23.22 ; + RECT 1.28 20.3 1.48 20.5 ; + RECT 1.74 11.46 1.94 11.66 ; + RECT 121.8 10.78 122 10.98 ; + RECT 121.8 9.42 122 9.62 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; + RECT 10.02 -0.1 10.22 0.1 ; LAYER via3 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 20.3 1.94 20.5 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 86.94 10.22 87.14 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; + RECT 10.02 -0.1 10.22 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 65.28 18.4 65.28 18.4 81.6 84.64 81.6 84.64 65.28 103.04 65.28 103.04 0 ; + POLYGON 0 0 0 87.04 27.6 87.04 27.6 97.92 95.68 97.92 95.68 87.04 123.28 87.04 123.28 0 ; END END sb_1__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef index fdd0622..4cec805 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 103.04 BY 97.92 ; + SIZE 123.28 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 80.24 2.37 81.6 ; + RECT 55.59 0 55.73 1.36 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.61 96.56 72.75 97.92 ; + RECT 67.55 107.44 67.69 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] @@ -379,7 +379,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 96.56 53.43 97.92 ; + RECT 47.31 107.44 47.45 108.8 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 96.56 52.51 97.92 ; + RECT 65.71 107.44 65.85 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,15 +395,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.85 96.56 69.99 97.92 ; + RECT 80.43 107.44 80.57 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 60.57 96.56 60.87 97.92 ; + LAYER met2 ; + RECT 60.65 107.44 60.79 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; + RECT 73.99 107.44 74.13 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.29 96.56 76.43 97.92 ; + RECT 58.81 107.44 58.95 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 96.56 65.85 97.92 ; + RECT 75.83 107.44 75.97 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 96.56 56.19 97.92 ; + RECT 52.37 107.44 52.51 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 96.56 40.09 97.92 ; + RECT 71.23 107.44 71.37 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 55.97 96.56 56.27 97.92 ; + RECT 66.09 107.44 66.39 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.77 96.56 70.91 97.92 ; + RECT 50.53 107.44 50.67 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 96.56 75.51 97.92 ; + RECT 86.41 107.44 86.55 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.93 96.56 69.07 97.92 ; + RECT 62.03 107.44 62.17 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 96.56 54.35 97.92 ; + RECT 62.95 107.44 63.09 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,15 +491,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 96.56 39.17 97.92 ; + RECT 66.63 107.44 66.77 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 62.41 96.56 62.71 97.92 ; + LAYER met2 ; + RECT 81.35 107.44 81.49 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 96.56 58.49 97.92 ; + RECT 74.91 107.44 75.05 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 96.56 55.27 97.92 ; + RECT 48.23 107.44 48.37 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 96.56 57.11 97.92 ; + RECT 51.45 107.44 51.59 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] @@ -531,7 +531,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.31 96.56 24.45 97.92 ; + RECT 17.87 96.56 18.01 97.92 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,15 +539,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.39 96.56 23.53 97.92 ; + RECT 12.81 96.56 12.95 97.92 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 96.56 23.15 97.92 ; + LAYER met2 ; + RECT 8.21 96.56 8.35 97.92 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 96.56 22.61 97.92 ; + RECT 11.89 96.56 12.03 97.92 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 96.56 20.77 97.92 ; + RECT 6.37 96.56 6.51 97.92 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 80.24 8.81 81.6 ; + RECT 10.97 96.56 11.11 97.92 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,15 +579,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 96.56 21.69 97.92 ; + RECT 7.29 96.56 7.43 97.92 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 96.56 24.99 97.92 ; + LAYER met2 ; + RECT 5.45 96.56 5.59 97.92 ; END END top_left_grid_pin_49_[0] PIN chanx_right_in[0] @@ -595,7 +595,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 34.53 103.04 34.83 ; + RECT 121.9 37.25 123.28 37.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -603,7 +603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 121.9 71.25 123.28 71.55 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -611,7 +611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 46.09 103.04 46.39 ; + RECT 121.9 92.33 123.28 92.63 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -619,7 +619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 121.9 84.85 123.28 85.15 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -627,7 +627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 68.53 103.04 68.83 ; + RECT 121.9 73.97 123.28 74.27 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -635,7 +635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 67.17 103.04 67.47 ; + RECT 121.9 76.69 123.28 76.99 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -643,7 +643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.97 103.04 40.27 ; + RECT 121.9 67.17 123.28 67.47 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -651,7 +651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.25 103.04 37.55 ; + RECT 121.9 39.97 123.28 40.27 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -659,7 +659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 41.33 103.04 41.63 ; + RECT 121.9 55.61 123.28 55.91 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -667,7 +667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.05 103.04 61.35 ; + RECT 121.9 75.33 123.28 75.63 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -675,7 +675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 121.9 59.69 123.28 59.99 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -683,7 +683,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 55.61 103.04 55.91 ; + RECT 121.9 72.61 123.28 72.91 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -691,7 +691,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 62.41 103.04 62.71 ; + RECT 121.9 78.05 123.28 78.35 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -699,7 +699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.05 103.04 27.35 ; + RECT 121.9 35.89 123.28 36.19 ; END END chanx_right_in[13] PIN chanx_right_in[14] @@ -707,7 +707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 25.69 103.04 25.99 ; + RECT 121.9 31.81 123.28 32.11 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -715,7 +715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 28.41 103.04 28.71 ; + RECT 121.9 41.33 123.28 41.63 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -723,7 +723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 69.89 103.04 70.19 ; + RECT 121.9 89.61 123.28 89.91 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -731,7 +731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 35.89 103.04 36.19 ; + RECT 121.9 44.05 123.28 44.35 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -739,7 +739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.97 103.04 57.27 ; + RECT 121.9 80.77 123.28 81.07 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -747,7 +747,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.77 103.04 30.07 ; + RECT 121.9 38.61 123.28 38.91 ; END END chanx_right_in[19] PIN right_bottom_grid_pin_34_[0] @@ -755,7 +755,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 97.91 16.32 98.05 17.68 ; + RECT 114.93 10.88 115.07 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -763,15 +763,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 100.67 16.32 100.81 17.68 ; + RECT 115.85 10.88 115.99 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 97.37 16.32 97.67 17.68 ; + LAYER met2 ; + RECT 109.87 10.88 110.01 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -779,7 +779,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 94.23 16.32 94.37 17.68 ; + RECT 112.63 10.88 112.77 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -787,7 +787,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 95.15 16.32 95.29 17.68 ; + RECT 118.61 10.88 118.75 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] @@ -795,7 +795,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 98.83 16.32 98.97 17.68 ; + RECT 116.77 10.88 116.91 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -803,7 +803,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 96.53 16.32 96.67 17.68 ; + RECT 117.69 10.88 117.83 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -811,7 +811,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.27 0 82.41 1.36 ; + RECT 114.01 10.88 114.15 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -819,7 +819,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -827,7 +827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -835,7 +835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 80.43 0 80.57 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -843,7 +843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 70.31 0 70.45 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -851,7 +851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 60.65 0 60.79 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -859,7 +859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + RECT 64.33 0 64.47 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -867,7 +867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; + RECT 61.57 0 61.71 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -875,7 +875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -883,7 +883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; + RECT 67.55 0 67.69 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -891,7 +891,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -899,7 +899,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 71.23 0 71.37 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -907,7 +907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -915,7 +915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 66.63 0 66.77 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -923,7 +923,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -931,7 +931,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; + RECT 81.35 0 81.49 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -939,7 +939,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -947,7 +947,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 59.73 0 59.87 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -955,7 +955,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; + RECT 63.41 0 63.55 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -963,7 +963,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.29 0 76.43 1.36 ; + RECT 65.71 0 65.85 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -971,7 +971,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 78.59 0 78.73 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_42_[0] @@ -979,7 +979,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + RECT 11.43 10.88 11.57 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] @@ -987,7 +987,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.47 0 22.61 1.36 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -995,7 +995,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 6.37 16.32 6.51 17.68 ; + RECT 12.35 10.88 12.49 12.24 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -1003,15 +1003,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 16.32 4.67 17.68 ; + RECT 14.19 10.88 14.33 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 6.65 19.78 6.95 ; + LAYER met2 ; + RECT 16.03 10.88 16.17 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] @@ -1019,23 +1019,23 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.23 16.32 2.37 17.68 ; + RECT 17.87 10.88 18.01 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 5.29 19.78 5.59 ; + LAYER met4 ; + RECT 5.37 10.88 5.67 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 8.01 19.78 8.31 ; + LAYER met4 ; + RECT 11.81 10.88 12.11 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -1043,7 +1043,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -1051,7 +1051,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -1059,7 +1059,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 85.53 1.38 85.83 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -1067,7 +1067,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -1075,7 +1075,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -1083,7 +1083,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -1091,7 +1091,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + RECT 0 90.97 1.38 91.27 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -1099,7 +1099,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -1107,7 +1107,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -1115,7 +1115,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 84.17 1.38 84.47 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -1123,7 +1123,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 88.25 1.38 88.55 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -1131,7 +1131,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 86.89 1.38 87.19 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -1139,7 +1139,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -1147,7 +1147,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -1155,7 +1155,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -1163,7 +1163,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -1171,7 +1171,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -1179,7 +1179,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -1187,7 +1187,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -1195,23 +1195,23 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 6.29 16.32 6.59 17.68 ; + LAYER met2 ; + RECT 15.11 10.88 15.25 12.24 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 16.32 4.75 17.68 ; + LAYER met2 ; + RECT 13.27 10.88 13.41 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -1219,7 +1219,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + RECT 4.99 10.88 5.13 12.24 ; END END left_bottom_grid_pin_36_[0] PIN left_bottom_grid_pin_37_[0] @@ -1227,7 +1227,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 16.32 5.59 17.68 ; + RECT 5.91 10.88 6.05 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1235,15 +1235,15 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 7.75 10.88 7.89 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + LAYER met2 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -1251,7 +1251,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 0 21.69 1.36 ; + RECT 3.15 10.88 3.29 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1259,7 +1259,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 16.32 7.89 17.68 ; + RECT 6.83 10.88 6.97 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1267,7 +1267,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 73.97 103.04 74.27 ; + RECT 121.9 86.89 123.28 87.19 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1275,7 +1275,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 96.56 49.75 97.92 ; + RECT 55.59 107.44 55.73 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1283,7 +1283,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 96.56 51.59 97.92 ; + RECT 79.51 107.44 79.65 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1291,7 +1291,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; + RECT 59.73 107.44 59.87 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1299,7 +1299,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; + RECT 77.67 107.44 77.81 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1307,7 +1307,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 72.15 107.44 72.29 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1315,7 +1315,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.01 96.56 68.15 97.92 ; + RECT 82.73 107.44 82.87 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1323,7 +1323,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 96.56 50.67 97.92 ; + RECT 63.87 107.44 64.01 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1331,7 +1331,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 68.47 107.44 68.61 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1339,7 +1339,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 96.56 43.31 97.92 ; + RECT 49.15 107.44 49.29 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1347,7 +1347,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 84.57 107.44 84.71 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1355,7 +1355,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 64.79 107.44 64.93 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1363,7 +1363,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.69 96.56 71.83 97.92 ; + RECT 69.85 107.44 69.99 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1371,7 +1371,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 96.56 74.59 97.92 ; + RECT 85.49 107.44 85.63 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1379,7 +1379,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 96.56 62.63 97.92 ; + RECT 87.79 107.44 87.93 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1387,7 +1387,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 96.56 41.01 97.92 ; + RECT 34.89 107.44 35.03 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1395,7 +1395,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; + RECT 76.75 107.44 76.89 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1403,7 +1403,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; + RECT 36.73 107.44 36.87 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1411,7 +1411,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 96.56 66.77 97.92 ; + RECT 73.07 107.44 73.21 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1419,7 +1419,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; + RECT 53.29 107.44 53.43 108.8 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1427,7 +1427,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.67 96.56 77.81 97.92 ; + RECT 78.59 107.44 78.73 108.8 ; END END chany_top_out[19] PIN chanx_right_out[0] @@ -1435,7 +1435,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 24.33 103.04 24.63 ; + RECT 121.9 83.49 123.28 83.79 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1443,7 +1443,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 33.17 103.04 33.47 ; + RECT 121.9 90.97 123.28 91.27 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1451,7 +1451,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.69 103.04 42.99 ; + RECT 121.9 48.13 123.28 48.43 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1459,7 +1459,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.89 103.04 53.19 ; + RECT 121.9 61.05 123.28 61.35 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1467,7 +1467,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.69 103.04 59.99 ; + RECT 121.9 82.13 123.28 82.43 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1475,7 +1475,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 64.45 103.04 64.75 ; + RECT 121.9 79.41 123.28 79.71 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1483,7 +1483,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.85 103.04 51.15 ; + RECT 121.9 54.25 123.28 54.55 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1491,7 +1491,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 58.33 103.04 58.63 ; + RECT 121.9 64.45 123.28 64.75 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1499,7 +1499,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 76.69 103.04 76.99 ; + RECT 121.9 56.97 123.28 57.27 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1507,7 +1507,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 71.25 103.04 71.55 ; + RECT 121.9 50.85 123.28 51.15 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1515,7 +1515,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 47.45 103.04 47.75 ; + RECT 121.9 49.49 123.28 49.79 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1523,7 +1523,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 49.49 103.04 49.79 ; + RECT 121.9 65.81 123.28 66.11 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1531,7 +1531,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 75.33 103.04 75.63 ; + RECT 121.9 45.41 123.28 45.71 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1539,7 +1539,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 78.05 103.04 78.35 ; + RECT 121.9 88.25 123.28 88.55 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1547,7 +1547,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 31.81 103.04 32.11 ; + RECT 121.9 46.77 123.28 47.07 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1555,7 +1555,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 72.61 103.04 72.91 ; + RECT 121.9 42.69 123.28 42.99 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1563,7 +1563,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 121.9 58.33 123.28 58.63 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1571,7 +1571,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 38.61 103.04 38.91 ; + RECT 121.9 52.89 123.28 53.19 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1579,7 +1579,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.25 103.04 54.55 ; + RECT 121.9 62.41 123.28 62.71 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1587,7 +1587,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 65.81 103.04 66.11 ; + RECT 121.9 69.21 123.28 69.51 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1595,7 +1595,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1603,7 +1603,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1611,7 +1611,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 58.81 0 58.95 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1619,7 +1619,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 0 63.55 1.36 ; + RECT 79.51 0 79.65 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1627,7 +1627,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1635,7 +1635,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 87.79 0 87.93 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1643,7 +1643,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1651,7 +1651,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 77.67 0 77.81 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1659,7 +1659,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 85.49 0 85.63 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1667,7 +1667,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 73.07 0 73.21 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1675,7 +1675,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1683,7 +1683,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 76.75 0 76.89 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1691,7 +1691,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1699,7 +1699,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 88.71 0 88.85 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1707,7 +1707,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1715,7 +1715,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 0 81.03 1.36 ; + RECT 89.63 0 89.77 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1723,7 +1723,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 84.57 0 84.71 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1731,7 +1731,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 72.15 0 72.29 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1739,7 +1739,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1747,7 +1747,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 90.55 0 90.69 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1755,7 +1755,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1763,7 +1763,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1771,7 +1771,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1779,7 +1779,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 67.17 1.38 67.47 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1787,7 +1787,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1795,7 +1795,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1803,7 +1803,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1811,7 +1811,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1819,7 +1819,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1827,7 +1827,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1835,7 +1835,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.17 1.38 67.47 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1843,7 +1843,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1851,7 +1851,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1859,7 +1859,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1867,7 +1867,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1875,7 +1875,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1883,7 +1883,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1891,7 +1891,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1899,7 +1899,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1907,7 +1907,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1915,7 +1915,7 @@ MACRO sb_1__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 89.61 1.38 89.91 ; END END ccff_tail[0] PIN VDD @@ -1923,52 +1923,58 @@ MACRO sb_1__1_ USE POWER ; PORT LAYER met1 ; - RECT 18.4 2.48 18.88 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; - RECT 18.4 7.92 18.88 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; - RECT 18.4 13.36 18.88 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 27.6 2.48 28.08 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; + RECT 27.6 7.92 28.08 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 122.8 13.36 123.28 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 102.56 18.8 103.04 19.28 ; + RECT 122.8 18.8 123.28 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 102.56 24.24 103.04 24.72 ; + RECT 122.8 24.24 123.28 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 102.56 29.68 103.04 30.16 ; + RECT 122.8 29.68 123.28 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 102.56 35.12 103.04 35.6 ; + RECT 122.8 35.12 123.28 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 102.56 40.56 103.04 41.04 ; + RECT 122.8 40.56 123.28 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 102.56 46 103.04 46.48 ; + RECT 122.8 46 123.28 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 102.56 51.44 103.04 51.92 ; + RECT 122.8 51.44 123.28 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 102.56 56.88 103.04 57.36 ; + RECT 122.8 56.88 123.28 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 102.56 62.32 103.04 62.8 ; + RECT 122.8 62.32 123.28 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 102.56 67.76 103.04 68.24 ; + RECT 122.8 67.76 123.28 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 102.56 73.2 103.04 73.68 ; + RECT 122.8 73.2 123.28 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 102.56 78.64 103.04 79.12 ; - RECT 18.4 84.08 18.88 84.56 ; - RECT 84.16 84.08 84.64 84.56 ; - RECT 18.4 89.52 18.88 90 ; - RECT 84.16 89.52 84.64 90 ; - RECT 18.4 94.96 18.88 95.44 ; - RECT 84.16 94.96 84.64 95.44 ; + RECT 122.8 78.64 123.28 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 122.8 84.08 123.28 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 122.8 89.52 123.28 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 122.8 94.96 123.28 95.44 ; + RECT 27.6 100.4 28.08 100.88 ; + RECT 95.2 100.4 95.68 100.88 ; + RECT 27.6 105.84 28.08 106.32 ; + RECT 95.2 105.84 95.68 106.32 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 97.32 29.74 97.92 ; - RECT 58.58 97.32 59.18 97.92 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 112.86 10.88 113.46 11.48 ; + RECT 112.86 97.32 113.46 97.92 ; + RECT 39.26 108.2 39.86 108.8 ; + RECT 68.7 108.2 69.3 108.8 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 99.84 26.96 103.04 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 99.84 67.76 103.04 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 120.08 22.2 123.28 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 120.08 63 123.28 66.2 ; END END VDD PIN VSS @@ -1976,162 +1982,464 @@ MACRO sb_1__1_ USE GROUND ; PORT LAYER met1 ; - RECT 18.4 0 84.64 0.24 ; - RECT 18.4 5.2 18.88 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; - RECT 18.4 10.64 18.88 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; - RECT 0 16.08 103.04 16.56 ; + RECT 27.6 0 95.68 0.24 ; + RECT 27.6 5.2 28.08 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; + RECT 0 10.64 123.28 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 122.8 16.08 123.28 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 102.56 21.52 103.04 22 ; + RECT 122.8 21.52 123.28 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 102.56 26.96 103.04 27.44 ; + RECT 122.8 26.96 123.28 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 102.56 32.4 103.04 32.88 ; + RECT 122.8 32.4 123.28 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 102.56 37.84 103.04 38.32 ; + RECT 122.8 37.84 123.28 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 102.56 43.28 103.04 43.76 ; + RECT 122.8 43.28 123.28 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 102.56 48.72 103.04 49.2 ; + RECT 122.8 48.72 123.28 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 102.56 54.16 103.04 54.64 ; + RECT 122.8 54.16 123.28 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 102.56 59.6 103.04 60.08 ; + RECT 122.8 59.6 123.28 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 102.56 65.04 103.04 65.52 ; + RECT 122.8 65.04 123.28 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 102.56 70.48 103.04 70.96 ; + RECT 122.8 70.48 123.28 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 102.56 75.92 103.04 76.4 ; - RECT 0 81.36 103.04 81.84 ; - RECT 18.4 86.8 18.88 87.28 ; - RECT 84.16 86.8 84.64 87.28 ; - RECT 18.4 92.24 18.88 92.72 ; - RECT 84.16 92.24 84.64 92.72 ; - RECT 18.4 97.68 84.64 97.92 ; + RECT 122.8 75.92 123.28 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 122.8 81.36 123.28 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 122.8 86.8 123.28 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 122.8 92.24 123.28 92.72 ; + RECT 0 97.68 123.28 98.16 ; + RECT 27.6 103.12 28.08 103.6 ; + RECT 95.2 103.12 95.68 103.6 ; + RECT 27.6 108.56 95.68 108.8 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 97.32 44.46 97.92 ; - RECT 73.3 97.32 73.9 97.92 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 10.88 10.42 11.48 ; + RECT 9.82 97.32 10.42 97.92 ; + RECT 53.98 108.2 54.58 108.8 ; + RECT 83.42 108.2 84.02 108.8 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 99.84 47.36 103.04 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 120.08 42.6 123.28 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 120.08 83.4 123.28 86.6 ; END END VSS + PIN prog_clk__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE CLOCK ; + PORT + LAYER met2 ; + RECT 57.43 107.44 57.57 108.8 ; + END + END prog_clk__FEEDTHRU_1[0] + PIN Test_en__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 10.88 2.37 12.24 ; + END + END Test_en__FEEDTHRU_0[0] + PIN Test_en__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 96.56 2.37 97.92 ; + END + END Test_en__FEEDTHRU_1[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 0 35.95 1.36 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 107.44 35.95 108.8 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 18.4 97.835 84.64 98.005 ; - RECT 83.72 95.115 84.64 95.285 ; - RECT 18.4 95.115 22.08 95.285 ; - RECT 83.72 92.395 84.64 92.565 ; - RECT 18.4 92.395 22.08 92.565 ; - RECT 83.72 89.675 84.64 89.845 ; - RECT 18.4 89.675 20.24 89.845 ; - RECT 83.72 86.955 84.64 87.125 ; - RECT 18.4 86.955 22.08 87.125 ; - RECT 83.72 84.235 84.64 84.405 ; - RECT 18.4 84.235 22.08 84.405 ; - RECT 81.88 81.515 103.04 81.685 ; - RECT 0 81.515 20.24 81.685 ; - RECT 102.58 78.795 103.04 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 102.12 76.075 103.04 76.245 ; + RECT 27.6 108.715 95.68 108.885 ; + RECT 94.76 105.995 95.68 106.165 ; + RECT 27.6 105.995 31.28 106.165 ; + RECT 94.76 103.275 95.68 103.445 ; + RECT 27.6 103.275 31.28 103.445 ; + RECT 94.76 100.555 95.68 100.725 ; + RECT 27.6 100.555 31.28 100.725 ; + RECT 92.92 97.835 123.28 98.005 ; + RECT 0 97.835 29.44 98.005 ; + RECT 122.36 95.115 123.28 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 122.36 92.395 123.28 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 122.36 89.675 123.28 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 122.36 86.955 123.28 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 122.82 84.235 123.28 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 122.36 81.515 123.28 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 122.36 78.795 123.28 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 122.36 76.075 123.28 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 102.12 73.355 103.04 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 102.12 70.635 103.04 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 102.12 67.915 103.04 68.085 ; + RECT 122.36 73.355 123.28 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 122.36 70.635 123.28 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 122.36 67.915 123.28 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 102.12 65.195 103.04 65.365 ; + RECT 122.36 65.195 123.28 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 102.12 62.475 103.04 62.645 ; + RECT 122.36 62.475 123.28 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 102.12 59.755 103.04 59.925 ; + RECT 122.36 59.755 123.28 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 102.12 57.035 103.04 57.205 ; + RECT 122.36 57.035 123.28 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 102.12 54.315 103.04 54.485 ; - RECT 0 54.315 1.84 54.485 ; - RECT 102.12 51.595 103.04 51.765 ; - RECT 0 51.595 1.84 51.765 ; - RECT 102.12 48.875 103.04 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 102.12 46.155 103.04 46.325 ; + RECT 122.36 54.315 123.28 54.485 ; + RECT 0 54.315 3.68 54.485 ; + RECT 122.36 51.595 123.28 51.765 ; + RECT 0 51.595 3.68 51.765 ; + RECT 122.36 48.875 123.28 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 122.36 46.155 123.28 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 102.12 43.435 103.04 43.605 ; + RECT 122.36 43.435 123.28 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 102.12 40.715 103.04 40.885 ; + RECT 122.36 40.715 123.28 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 99.36 37.995 103.04 38.165 ; + RECT 122.36 37.995 123.28 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 99.36 35.275 103.04 35.445 ; + RECT 122.36 35.275 123.28 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 102.12 32.555 103.04 32.725 ; + RECT 122.82 32.555 123.28 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 99.36 29.835 103.04 30.005 ; - RECT 0 29.835 1.84 30.005 ; - RECT 99.36 27.115 103.04 27.285 ; - RECT 0 27.115 1.84 27.285 ; - RECT 102.12 24.395 103.04 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 102.12 21.675 103.04 21.845 ; + RECT 122.82 29.835 123.28 30.005 ; + RECT 0 29.835 3.68 30.005 ; + RECT 122.82 27.115 123.28 27.285 ; + RECT 0 27.115 3.68 27.285 ; + RECT 119.6 24.395 123.28 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 119.6 21.675 123.28 21.845 ; RECT 0 21.675 3.68 21.845 ; - RECT 102.12 18.955 103.04 19.125 ; + RECT 122.36 18.955 123.28 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 81.88 16.235 103.04 16.405 ; - RECT 0 16.235 22.08 16.405 ; - RECT 83.72 13.515 84.64 13.685 ; - RECT 18.4 13.515 20.24 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; - RECT 18.4 10.795 20.24 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; - RECT 18.4 8.075 20.24 8.245 ; - RECT 83.72 5.355 84.64 5.525 ; - RECT 18.4 5.355 20.24 5.525 ; - RECT 83.72 2.635 84.64 2.805 ; - RECT 18.4 2.635 22.08 2.805 ; - RECT 18.4 -0.085 84.64 0.085 ; + RECT 122.82 16.235 123.28 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 122.36 13.515 123.28 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 92.92 10.795 123.28 10.965 ; + RECT 0 10.795 31.28 10.965 ; + RECT 94.76 8.075 95.68 8.245 ; + RECT 27.6 8.075 31.28 8.245 ; + RECT 94.76 5.355 95.68 5.525 ; + RECT 27.6 5.355 31.28 5.525 ; + RECT 95.22 2.635 95.68 2.805 ; + RECT 27.6 2.635 31.28 2.805 ; + RECT 27.6 -0.085 95.68 0.085 ; LAYER met2 ; - RECT 73.46 97.735 73.74 98.105 ; - RECT 44.02 97.735 44.3 98.105 ; - POLYGON 21.23 96.63 21.23 96.38 21.29 96.38 21.29 96.06 21.03 96.06 21.03 96.28 21.05 96.28 21.05 96.63 ; - RECT 73.01 96.06 73.27 96.38 ; - RECT 60.59 96.06 60.85 96.38 ; - RECT 96.93 17.86 97.19 18.18 ; - RECT 75.77 1.54 76.03 1.86 ; - RECT 61.51 1.54 61.77 1.86 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 97.64 84.36 81.32 102.76 81.32 102.76 16.6 101.09 16.6 101.09 17.96 100.39 17.96 100.39 16.6 99.25 16.6 99.25 17.96 98.55 17.96 98.55 16.6 98.33 16.6 98.33 17.96 97.63 17.96 97.63 16.6 96.95 16.6 96.95 17.96 96.25 17.96 96.25 16.6 95.57 16.6 95.57 17.96 94.87 17.96 94.87 16.6 94.65 16.6 94.65 17.96 93.95 17.96 93.95 16.6 84.36 16.6 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 22.89 0.28 22.89 1.64 22.19 1.64 22.19 0.28 21.97 0.28 21.97 1.64 21.27 1.64 21.27 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 6.79 16.6 6.79 17.96 6.09 17.96 6.09 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.19 97.64 22.19 96.28 22.89 96.28 22.89 97.64 23.11 97.64 23.11 96.28 23.81 96.28 23.81 97.64 24.03 97.64 24.03 96.28 24.73 96.28 24.73 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 49.33 97.64 49.33 96.28 50.03 96.28 50.03 97.64 50.25 97.64 50.25 96.28 50.95 96.28 50.95 97.64 51.17 97.64 51.17 96.28 51.87 96.28 51.87 97.64 52.09 97.64 52.09 96.28 52.79 96.28 52.79 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 53.93 97.64 53.93 96.28 54.63 96.28 54.63 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 55.77 97.64 55.77 96.28 56.47 96.28 56.47 97.64 56.69 97.64 56.69 96.28 57.39 96.28 57.39 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 65.43 97.64 65.43 96.28 66.13 96.28 66.13 97.64 66.35 97.64 66.35 96.28 67.05 96.28 67.05 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 68.65 97.64 68.65 96.28 69.35 96.28 69.35 97.64 69.57 97.64 69.57 96.28 70.27 96.28 70.27 97.64 70.49 97.64 70.49 96.28 71.19 96.28 71.19 97.64 71.41 97.64 71.41 96.28 72.11 96.28 72.11 97.64 72.33 97.64 72.33 96.28 73.03 96.28 73.03 97.64 74.17 97.64 74.17 96.28 74.87 96.28 74.87 97.64 75.09 97.64 75.09 96.28 75.79 96.28 75.79 97.64 76.01 97.64 76.01 96.28 76.71 96.28 76.71 97.64 77.39 97.64 77.39 96.28 78.09 96.28 78.09 97.64 ; + RECT 83.58 108.615 83.86 108.985 ; + RECT 54.14 108.615 54.42 108.985 ; + RECT 82.21 106.94 82.47 107.26 ; + RECT 69.33 106.94 69.59 107.26 ; + RECT 9.98 97.735 10.26 98.105 ; + RECT 9.98 10.695 10.26 11.065 ; + RECT 90.95 1.54 91.21 1.86 ; + RECT 84.97 1.54 85.23 1.86 ; + RECT 53.23 1.54 53.49 1.86 ; + RECT 49.55 1.54 49.81 1.86 ; + RECT 35.29 1.54 35.55 1.86 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + POLYGON 95.4 108.52 95.4 97.64 123 97.64 123 11.16 119.03 11.16 119.03 12.52 118.33 12.52 118.33 11.16 118.11 11.16 118.11 12.52 117.41 12.52 117.41 11.16 117.19 11.16 117.19 12.52 116.49 12.52 116.49 11.16 116.27 11.16 116.27 12.52 115.57 12.52 115.57 11.16 115.35 11.16 115.35 12.52 114.65 12.52 114.65 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.05 11.16 113.05 12.52 112.35 12.52 112.35 11.16 110.29 11.16 110.29 12.52 109.59 12.52 109.59 11.16 95.4 11.16 95.4 0.28 90.97 0.28 90.97 1.64 90.27 1.64 90.27 0.28 90.05 0.28 90.05 1.64 89.35 1.64 89.35 0.28 89.13 0.28 89.13 1.64 88.43 1.64 88.43 0.28 88.21 0.28 88.21 1.64 87.51 1.64 87.51 0.28 85.91 0.28 85.91 1.64 85.21 1.64 85.21 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 5.17 97.64 5.17 96.28 5.87 96.28 5.87 97.64 6.09 97.64 6.09 96.28 6.79 96.28 6.79 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 10.69 97.64 10.69 96.28 11.39 96.28 11.39 97.64 11.61 97.64 11.61 96.28 12.31 96.28 12.31 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 17.59 97.64 17.59 96.28 18.29 96.28 18.29 97.64 27.88 97.64 27.88 108.52 34.61 108.52 34.61 107.16 35.31 107.16 35.31 108.52 35.53 108.52 35.53 107.16 36.23 107.16 36.23 108.52 36.45 108.52 36.45 107.16 37.15 107.16 37.15 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 50.25 108.52 50.25 107.16 50.95 107.16 50.95 108.52 51.17 108.52 51.17 107.16 51.87 107.16 51.87 108.52 52.09 108.52 52.09 107.16 52.79 107.16 52.79 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 55.31 108.52 55.31 107.16 56.01 107.16 56.01 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.53 108.52 58.53 107.16 59.23 107.16 59.23 108.52 59.45 108.52 59.45 107.16 60.15 107.16 60.15 108.52 60.37 108.52 60.37 107.16 61.07 107.16 61.07 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 62.67 108.52 62.67 107.16 63.37 107.16 63.37 108.52 63.59 108.52 63.59 107.16 64.29 107.16 64.29 108.52 64.51 108.52 64.51 107.16 65.21 107.16 65.21 108.52 65.43 108.52 65.43 107.16 66.13 107.16 66.13 108.52 66.35 108.52 66.35 107.16 67.05 107.16 67.05 108.52 67.27 108.52 67.27 107.16 67.97 107.16 67.97 108.52 68.19 108.52 68.19 107.16 68.89 107.16 68.89 108.52 69.57 108.52 69.57 107.16 70.27 107.16 70.27 108.52 70.95 108.52 70.95 107.16 71.65 107.16 71.65 108.52 71.87 108.52 71.87 107.16 72.57 107.16 72.57 108.52 72.79 108.52 72.79 107.16 73.49 107.16 73.49 108.52 73.71 108.52 73.71 107.16 74.41 107.16 74.41 108.52 74.63 108.52 74.63 107.16 75.33 107.16 75.33 108.52 75.55 108.52 75.55 107.16 76.25 107.16 76.25 108.52 76.47 108.52 76.47 107.16 77.17 107.16 77.17 108.52 77.39 108.52 77.39 107.16 78.09 107.16 78.09 108.52 78.31 108.52 78.31 107.16 79.01 107.16 79.01 108.52 79.23 108.52 79.23 107.16 79.93 107.16 79.93 108.52 80.15 108.52 80.15 107.16 80.85 107.16 80.85 108.52 81.07 108.52 81.07 107.16 81.77 107.16 81.77 108.52 82.45 108.52 82.45 107.16 83.15 107.16 83.15 108.52 84.29 108.52 84.29 107.16 84.99 107.16 84.99 108.52 85.21 108.52 85.21 107.16 85.91 107.16 85.91 108.52 86.13 108.52 86.13 107.16 86.83 107.16 86.83 108.52 87.51 108.52 87.51 107.16 88.21 107.16 88.21 108.52 ; LAYER met4 ; - POLYGON 84.24 97.52 84.24 81.2 102.64 81.2 102.64 16.72 98.07 16.72 98.07 18.08 96.97 18.08 96.97 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 55.57 97.52 55.57 96.16 56.67 96.16 56.67 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 60.17 97.52 60.17 96.16 61.27 96.16 61.27 97.52 62.01 97.52 62.01 96.16 63.11 96.16 63.11 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 ; + POLYGON 95.28 108.4 95.28 97.52 112.46 97.52 112.46 96.92 113.86 96.92 113.86 97.52 122.88 97.52 122.88 11.28 113.86 11.28 113.86 11.88 112.46 11.88 112.46 11.28 95.28 11.28 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 28 97.52 28 108.4 38.86 108.4 38.86 107.8 40.26 107.8 40.26 108.4 53.58 108.4 53.58 107.8 54.98 107.8 54.98 108.4 65.69 108.4 65.69 107.04 66.79 107.04 66.79 108.4 68.3 108.4 68.3 107.8 69.7 107.8 69.7 108.4 83.02 108.4 83.02 107.8 84.42 107.8 84.42 108.4 ; LAYER met3 ; - POLYGON 73.765 98.085 73.765 98.08 73.98 98.08 73.98 97.76 73.765 97.76 73.765 97.755 73.435 97.755 73.435 97.76 73.22 97.76 73.22 98.08 73.435 98.08 73.435 98.085 ; - POLYGON 44.325 98.085 44.325 98.08 44.54 98.08 44.54 97.76 44.325 97.76 44.325 97.755 43.995 97.755 43.995 97.76 43.78 97.76 43.78 98.08 43.995 98.08 43.995 98.085 ; - POLYGON 37.87 74.27 37.87 73.97 1.23 73.97 1.23 74.25 1.78 74.25 1.78 74.27 ; - POLYGON 2.005 59.325 2.005 59.32 2.03 59.32 2.03 59 2.005 59 2.005 58.995 1.275 58.995 1.275 59.325 ; - POLYGON 2.005 55.245 2.005 55.23 5.67 55.23 5.67 54.93 2.005 54.93 2.005 54.915 1.675 54.915 1.675 55.245 ; - POLYGON 101.26 51.15 101.26 50.45 101.35 50.45 101.35 50.17 100.13 50.17 100.13 50.47 101.05 50.47 101.05 51.15 ; - POLYGON 33.27 43.67 33.27 43.37 1.78 43.37 1.78 43.39 1.23 43.39 1.23 43.67 ; - POLYGON 101.26 35.51 101.26 35.49 101.81 35.49 101.81 35.21 63.33 35.21 63.33 35.51 ; - POLYGON 1.545 32.805 1.545 32.79 28.21 32.79 28.21 32.49 1.545 32.49 1.545 32.475 1.215 32.475 1.215 32.805 ; - POLYGON 2.03 31.44 2.03 31.43 47.07 31.43 47.07 31.13 2.03 31.13 2.03 31.12 1.65 31.12 1.65 31.44 ; - POLYGON 18.55 24.63 18.55 24.33 1.78 24.33 1.78 24.35 1.23 24.35 1.23 24.63 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 97.52 84.24 81.2 102.64 81.2 102.64 78.75 101.26 78.75 101.26 77.65 102.64 77.65 102.64 77.39 101.26 77.39 101.26 76.29 102.64 76.29 102.64 76.03 101.26 76.03 101.26 74.93 102.64 74.93 102.64 74.67 101.26 74.67 101.26 73.57 102.64 73.57 102.64 73.31 101.26 73.31 101.26 72.21 102.64 72.21 102.64 71.95 101.26 71.95 101.26 70.85 102.64 70.85 102.64 70.59 101.26 70.59 101.26 69.49 102.64 69.49 102.64 69.23 101.26 69.23 101.26 68.13 102.64 68.13 102.64 67.87 101.26 67.87 101.26 66.77 102.64 66.77 102.64 66.51 101.26 66.51 101.26 65.41 102.64 65.41 102.64 65.15 101.26 65.15 101.26 64.05 102.64 64.05 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 60.39 101.26 60.39 101.26 59.29 102.64 59.29 102.64 59.03 101.26 59.03 101.26 57.93 102.64 57.93 102.64 57.67 101.26 57.67 101.26 56.57 102.64 56.57 102.64 56.31 101.26 56.31 101.26 55.21 102.64 55.21 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 51.55 101.26 51.55 101.26 50.45 102.64 50.45 102.64 50.19 101.26 50.19 101.26 49.09 102.64 49.09 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 43.39 101.26 43.39 101.26 42.29 102.64 42.29 102.64 42.03 101.26 42.03 101.26 40.93 102.64 40.93 102.64 40.67 101.26 40.67 101.26 39.57 102.64 39.57 102.64 39.31 101.26 39.31 101.26 38.21 102.64 38.21 102.64 37.95 101.26 37.95 101.26 36.85 102.64 36.85 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 30.47 101.26 30.47 101.26 29.37 102.64 29.37 102.64 29.11 101.26 29.11 101.26 28.01 102.64 28.01 102.64 27.75 101.26 27.75 101.26 26.65 102.64 26.65 102.64 26.39 101.26 26.39 101.26 25.29 102.64 25.29 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 7.61 20.18 7.61 20.18 8.71 18.8 8.71 18.8 16.72 0.4 16.72 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 18.8 81.2 18.8 97.52 ; + POLYGON 83.885 108.965 83.885 108.96 84.1 108.96 84.1 108.64 83.885 108.64 83.885 108.635 83.555 108.635 83.555 108.64 83.34 108.64 83.34 108.96 83.555 108.96 83.555 108.965 ; + POLYGON 54.445 108.965 54.445 108.96 54.66 108.96 54.66 108.64 54.445 108.64 54.445 108.635 54.115 108.635 54.115 108.64 53.9 108.64 53.9 108.96 54.115 108.96 54.115 108.965 ; + POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; + POLYGON 7.05 83.79 7.05 83.49 1.99 83.49 1.99 82.81 1.78 82.81 1.78 83.51 1.69 83.51 1.69 83.79 ; + POLYGON 10.27 74.27 10.27 73.97 1.99 73.97 1.99 73.29 1.78 73.29 1.78 73.99 1.69 73.99 1.69 74.27 ; + POLYGON 7.97 58.63 7.97 58.33 1.99 58.33 1.99 57.65 1.78 57.65 1.78 58.35 1.69 58.35 1.69 58.63 ; + POLYGON 2.03 47.08 2.03 47.07 57.19 47.07 57.19 46.77 2.03 46.77 2.03 46.76 1.65 46.76 1.65 47.08 ; + POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 95.28 108.4 95.28 97.52 122.88 97.52 122.88 93.03 121.5 93.03 121.5 91.93 122.88 91.93 122.88 91.67 121.5 91.67 121.5 90.57 122.88 90.57 122.88 90.31 121.5 90.31 121.5 89.21 122.88 89.21 122.88 88.95 121.5 88.95 121.5 87.85 122.88 87.85 122.88 87.59 121.5 87.59 121.5 86.49 122.88 86.49 122.88 85.55 121.5 85.55 121.5 84.45 122.88 84.45 122.88 84.19 121.5 84.19 121.5 83.09 122.88 83.09 122.88 82.83 121.5 82.83 121.5 81.73 122.88 81.73 122.88 81.47 121.5 81.47 121.5 80.37 122.88 80.37 122.88 80.11 121.5 80.11 121.5 79.01 122.88 79.01 122.88 78.75 121.5 78.75 121.5 77.65 122.88 77.65 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 73.31 121.5 73.31 121.5 72.21 122.88 72.21 122.88 71.95 121.5 71.95 121.5 70.85 122.88 70.85 122.88 69.91 121.5 69.91 121.5 68.81 122.88 68.81 122.88 67.87 121.5 67.87 121.5 66.77 122.88 66.77 122.88 66.51 121.5 66.51 121.5 65.41 122.88 65.41 122.88 65.15 121.5 65.15 121.5 64.05 122.88 64.05 122.88 63.11 121.5 63.11 121.5 62.01 122.88 62.01 122.88 61.75 121.5 61.75 121.5 60.65 122.88 60.65 122.88 60.39 121.5 60.39 121.5 59.29 122.88 59.29 122.88 59.03 121.5 59.03 121.5 57.93 122.88 57.93 122.88 57.67 121.5 57.67 121.5 56.57 122.88 56.57 122.88 56.31 121.5 56.31 121.5 55.21 122.88 55.21 122.88 54.95 121.5 54.95 121.5 53.85 122.88 53.85 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 51.55 121.5 51.55 121.5 50.45 122.88 50.45 122.88 50.19 121.5 50.19 121.5 49.09 122.88 49.09 122.88 48.83 121.5 48.83 121.5 47.73 122.88 47.73 122.88 47.47 121.5 47.47 121.5 46.37 122.88 46.37 122.88 46.11 121.5 46.11 121.5 45.01 122.88 45.01 122.88 44.75 121.5 44.75 121.5 43.65 122.88 43.65 122.88 43.39 121.5 43.39 121.5 42.29 122.88 42.29 122.88 42.03 121.5 42.03 121.5 40.93 122.88 40.93 122.88 40.67 121.5 40.67 121.5 39.57 122.88 39.57 122.88 39.31 121.5 39.31 121.5 38.21 122.88 38.21 122.88 37.95 121.5 37.95 121.5 36.85 122.88 36.85 122.88 36.59 121.5 36.59 121.5 35.49 122.88 35.49 122.88 32.51 121.5 32.51 121.5 31.41 122.88 31.41 122.88 11.28 95.28 11.28 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 97.52 28 97.52 28 108.4 ; LAYER met5 ; - POLYGON 83.04 96.32 83.04 80 101.44 80 101.44 72.56 98.24 72.56 98.24 66.16 101.44 66.16 101.44 52.16 98.24 52.16 98.24 45.76 101.44 45.76 101.44 31.76 98.24 31.76 98.24 25.36 101.44 25.36 101.44 17.92 83.04 17.92 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 20 80 20 96.32 ; + POLYGON 94.08 107.2 94.08 96.32 121.68 96.32 121.68 88.2 118.48 88.2 118.48 81.8 121.68 81.8 121.68 67.8 118.48 67.8 118.48 61.4 121.68 61.4 121.68 47.4 118.48 47.4 118.48 41 121.68 41 121.68 27 118.48 27 118.48 20.6 121.68 20.6 121.68 12.48 94.08 12.48 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 29.2 96.32 29.2 107.2 ; LAYER met1 ; - POLYGON 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 18.68 82.12 18.68 83.8 19.16 83.8 19.16 84.84 18.68 84.84 18.68 86.52 19.16 86.52 19.16 87.56 18.68 87.56 18.68 89.24 19.16 89.24 19.16 90.28 18.68 90.28 18.68 91.96 19.16 91.96 19.16 93 18.68 93 18.68 94.68 19.16 94.68 19.16 95.72 18.68 95.72 18.68 97.4 ; - POLYGON 102.76 81.08 102.76 79.4 102.28 79.4 102.28 78.36 102.76 78.36 102.76 76.68 102.28 76.68 102.28 75.64 102.76 75.64 102.76 73.96 102.28 73.96 102.28 72.92 102.76 72.92 102.76 71.24 102.28 71.24 102.28 70.2 102.76 70.2 102.76 68.52 102.28 68.52 102.28 67.48 102.76 67.48 102.76 65.8 102.28 65.8 102.28 64.76 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; + POLYGON 68.7 98.57 68.7 98.31 68.38 98.31 68.38 98.37 61.325 98.37 61.325 98.325 61.035 98.325 61.035 98.555 61.325 98.555 61.325 98.51 68.38 98.51 68.38 98.57 ; + POLYGON 95.4 108.28 95.4 106.6 94.92 106.6 94.92 105.56 95.4 105.56 95.4 103.88 94.92 103.88 94.92 102.84 95.4 102.84 95.4 101.16 94.92 101.16 94.92 100.12 95.4 100.12 95.4 98.44 27.88 98.44 27.88 100.12 28.36 100.12 28.36 101.16 27.88 101.16 27.88 102.84 28.36 102.84 28.36 103.88 27.88 103.88 27.88 105.56 28.36 105.56 28.36 106.6 27.88 106.6 27.88 108.28 ; + POLYGON 123 97.4 123 95.72 122.52 95.72 122.52 94.68 123 94.68 123 93 122.52 93 122.52 91.96 123 91.96 123 90.28 122.52 90.28 122.52 89.24 123 89.24 123 87.56 122.52 87.56 122.52 86.52 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; LAYER li1 ; - POLYGON 84.47 97.75 84.47 81.43 102.87 81.43 102.87 16.49 84.47 16.49 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 18.57 81.43 18.57 97.75 ; + POLYGON 95.51 108.63 95.51 97.75 123.11 97.75 123.11 11.05 95.51 11.05 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 27.77 97.75 27.77 108.63 ; LAYER mcon ; + RECT 95.365 108.715 95.535 108.885 ; + RECT 94.905 108.715 95.075 108.885 ; + RECT 94.445 108.715 94.615 108.885 ; + RECT 93.985 108.715 94.155 108.885 ; + RECT 93.525 108.715 93.695 108.885 ; + RECT 93.065 108.715 93.235 108.885 ; + RECT 92.605 108.715 92.775 108.885 ; + RECT 92.145 108.715 92.315 108.885 ; + RECT 91.685 108.715 91.855 108.885 ; + RECT 91.225 108.715 91.395 108.885 ; + RECT 90.765 108.715 90.935 108.885 ; + RECT 90.305 108.715 90.475 108.885 ; + RECT 89.845 108.715 90.015 108.885 ; + RECT 89.385 108.715 89.555 108.885 ; + RECT 88.925 108.715 89.095 108.885 ; + RECT 88.465 108.715 88.635 108.885 ; + RECT 88.005 108.715 88.175 108.885 ; + RECT 87.545 108.715 87.715 108.885 ; + RECT 87.085 108.715 87.255 108.885 ; + RECT 86.625 108.715 86.795 108.885 ; + RECT 86.165 108.715 86.335 108.885 ; + RECT 85.705 108.715 85.875 108.885 ; + RECT 85.245 108.715 85.415 108.885 ; + RECT 84.785 108.715 84.955 108.885 ; + RECT 84.325 108.715 84.495 108.885 ; + RECT 83.865 108.715 84.035 108.885 ; + RECT 83.405 108.715 83.575 108.885 ; + RECT 82.945 108.715 83.115 108.885 ; + RECT 82.485 108.715 82.655 108.885 ; + RECT 82.025 108.715 82.195 108.885 ; + RECT 81.565 108.715 81.735 108.885 ; + RECT 81.105 108.715 81.275 108.885 ; + RECT 80.645 108.715 80.815 108.885 ; + RECT 80.185 108.715 80.355 108.885 ; + RECT 79.725 108.715 79.895 108.885 ; + RECT 79.265 108.715 79.435 108.885 ; + RECT 78.805 108.715 78.975 108.885 ; + RECT 78.345 108.715 78.515 108.885 ; + RECT 77.885 108.715 78.055 108.885 ; + RECT 77.425 108.715 77.595 108.885 ; + RECT 76.965 108.715 77.135 108.885 ; + RECT 76.505 108.715 76.675 108.885 ; + RECT 76.045 108.715 76.215 108.885 ; + RECT 75.585 108.715 75.755 108.885 ; + RECT 75.125 108.715 75.295 108.885 ; + RECT 74.665 108.715 74.835 108.885 ; + RECT 74.205 108.715 74.375 108.885 ; + RECT 73.745 108.715 73.915 108.885 ; + RECT 73.285 108.715 73.455 108.885 ; + RECT 72.825 108.715 72.995 108.885 ; + RECT 72.365 108.715 72.535 108.885 ; + RECT 71.905 108.715 72.075 108.885 ; + RECT 71.445 108.715 71.615 108.885 ; + RECT 70.985 108.715 71.155 108.885 ; + RECT 70.525 108.715 70.695 108.885 ; + RECT 70.065 108.715 70.235 108.885 ; + RECT 69.605 108.715 69.775 108.885 ; + RECT 69.145 108.715 69.315 108.885 ; + RECT 68.685 108.715 68.855 108.885 ; + RECT 68.225 108.715 68.395 108.885 ; + RECT 67.765 108.715 67.935 108.885 ; + RECT 67.305 108.715 67.475 108.885 ; + RECT 66.845 108.715 67.015 108.885 ; + RECT 66.385 108.715 66.555 108.885 ; + RECT 65.925 108.715 66.095 108.885 ; + RECT 65.465 108.715 65.635 108.885 ; + RECT 65.005 108.715 65.175 108.885 ; + RECT 64.545 108.715 64.715 108.885 ; + RECT 64.085 108.715 64.255 108.885 ; + RECT 63.625 108.715 63.795 108.885 ; + RECT 63.165 108.715 63.335 108.885 ; + RECT 62.705 108.715 62.875 108.885 ; + RECT 62.245 108.715 62.415 108.885 ; + RECT 61.785 108.715 61.955 108.885 ; + RECT 61.325 108.715 61.495 108.885 ; + RECT 60.865 108.715 61.035 108.885 ; + RECT 60.405 108.715 60.575 108.885 ; + RECT 59.945 108.715 60.115 108.885 ; + RECT 59.485 108.715 59.655 108.885 ; + RECT 59.025 108.715 59.195 108.885 ; + RECT 58.565 108.715 58.735 108.885 ; + RECT 58.105 108.715 58.275 108.885 ; + RECT 57.645 108.715 57.815 108.885 ; + RECT 57.185 108.715 57.355 108.885 ; + RECT 56.725 108.715 56.895 108.885 ; + RECT 56.265 108.715 56.435 108.885 ; + RECT 55.805 108.715 55.975 108.885 ; + RECT 55.345 108.715 55.515 108.885 ; + RECT 54.885 108.715 55.055 108.885 ; + RECT 54.425 108.715 54.595 108.885 ; + RECT 53.965 108.715 54.135 108.885 ; + RECT 53.505 108.715 53.675 108.885 ; + RECT 53.045 108.715 53.215 108.885 ; + RECT 52.585 108.715 52.755 108.885 ; + RECT 52.125 108.715 52.295 108.885 ; + RECT 51.665 108.715 51.835 108.885 ; + RECT 51.205 108.715 51.375 108.885 ; + RECT 50.745 108.715 50.915 108.885 ; + RECT 50.285 108.715 50.455 108.885 ; + RECT 49.825 108.715 49.995 108.885 ; + RECT 49.365 108.715 49.535 108.885 ; + RECT 48.905 108.715 49.075 108.885 ; + RECT 48.445 108.715 48.615 108.885 ; + RECT 47.985 108.715 48.155 108.885 ; + RECT 47.525 108.715 47.695 108.885 ; + RECT 47.065 108.715 47.235 108.885 ; + RECT 46.605 108.715 46.775 108.885 ; + RECT 46.145 108.715 46.315 108.885 ; + RECT 45.685 108.715 45.855 108.885 ; + RECT 45.225 108.715 45.395 108.885 ; + RECT 44.765 108.715 44.935 108.885 ; + RECT 44.305 108.715 44.475 108.885 ; + RECT 43.845 108.715 44.015 108.885 ; + RECT 43.385 108.715 43.555 108.885 ; + RECT 42.925 108.715 43.095 108.885 ; + RECT 42.465 108.715 42.635 108.885 ; + RECT 42.005 108.715 42.175 108.885 ; + RECT 41.545 108.715 41.715 108.885 ; + RECT 41.085 108.715 41.255 108.885 ; + RECT 40.625 108.715 40.795 108.885 ; + RECT 40.165 108.715 40.335 108.885 ; + RECT 39.705 108.715 39.875 108.885 ; + RECT 39.245 108.715 39.415 108.885 ; + RECT 38.785 108.715 38.955 108.885 ; + RECT 38.325 108.715 38.495 108.885 ; + RECT 37.865 108.715 38.035 108.885 ; + RECT 37.405 108.715 37.575 108.885 ; + RECT 36.945 108.715 37.115 108.885 ; + RECT 36.485 108.715 36.655 108.885 ; + RECT 36.025 108.715 36.195 108.885 ; + RECT 35.565 108.715 35.735 108.885 ; + RECT 35.105 108.715 35.275 108.885 ; + RECT 34.645 108.715 34.815 108.885 ; + RECT 34.185 108.715 34.355 108.885 ; + RECT 33.725 108.715 33.895 108.885 ; + RECT 33.265 108.715 33.435 108.885 ; + RECT 32.805 108.715 32.975 108.885 ; + RECT 32.345 108.715 32.515 108.885 ; + RECT 31.885 108.715 32.055 108.885 ; + RECT 31.425 108.715 31.595 108.885 ; + RECT 30.965 108.715 31.135 108.885 ; + RECT 30.505 108.715 30.675 108.885 ; + RECT 30.045 108.715 30.215 108.885 ; + RECT 29.585 108.715 29.755 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 28.205 108.715 28.375 108.885 ; + RECT 27.745 108.715 27.915 108.885 ; + RECT 95.365 105.995 95.535 106.165 ; + RECT 94.905 105.995 95.075 106.165 ; + RECT 28.205 105.995 28.375 106.165 ; + RECT 27.745 105.995 27.915 106.165 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 95.365 100.555 95.535 100.725 ; + RECT 94.905 100.555 95.075 100.725 ; + RECT 28.205 100.555 28.375 100.725 ; + RECT 27.745 100.555 27.915 100.725 ; + RECT 61.095 98.355 61.265 98.525 ; + RECT 122.965 97.835 123.135 98.005 ; + RECT 122.505 97.835 122.675 98.005 ; + RECT 122.045 97.835 122.215 98.005 ; + RECT 121.585 97.835 121.755 98.005 ; + RECT 121.125 97.835 121.295 98.005 ; + RECT 120.665 97.835 120.835 98.005 ; + RECT 120.205 97.835 120.375 98.005 ; + RECT 119.745 97.835 119.915 98.005 ; + RECT 119.285 97.835 119.455 98.005 ; + RECT 118.825 97.835 118.995 98.005 ; + RECT 118.365 97.835 118.535 98.005 ; + RECT 117.905 97.835 118.075 98.005 ; + RECT 117.445 97.835 117.615 98.005 ; + RECT 116.985 97.835 117.155 98.005 ; + RECT 116.525 97.835 116.695 98.005 ; + RECT 116.065 97.835 116.235 98.005 ; + RECT 115.605 97.835 115.775 98.005 ; + RECT 115.145 97.835 115.315 98.005 ; + RECT 114.685 97.835 114.855 98.005 ; + RECT 114.225 97.835 114.395 98.005 ; + RECT 113.765 97.835 113.935 98.005 ; + RECT 113.305 97.835 113.475 98.005 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 111.925 97.835 112.095 98.005 ; + RECT 111.465 97.835 111.635 98.005 ; + RECT 111.005 97.835 111.175 98.005 ; + RECT 110.545 97.835 110.715 98.005 ; + RECT 110.085 97.835 110.255 98.005 ; + RECT 109.625 97.835 109.795 98.005 ; + RECT 109.165 97.835 109.335 98.005 ; + RECT 108.705 97.835 108.875 98.005 ; + RECT 108.245 97.835 108.415 98.005 ; + RECT 107.785 97.835 107.955 98.005 ; + RECT 107.325 97.835 107.495 98.005 ; + RECT 106.865 97.835 107.035 98.005 ; + RECT 106.405 97.835 106.575 98.005 ; + RECT 105.945 97.835 106.115 98.005 ; + RECT 105.485 97.835 105.655 98.005 ; + RECT 105.025 97.835 105.195 98.005 ; + RECT 104.565 97.835 104.735 98.005 ; + RECT 104.105 97.835 104.275 98.005 ; + RECT 103.645 97.835 103.815 98.005 ; + RECT 103.185 97.835 103.355 98.005 ; + RECT 102.725 97.835 102.895 98.005 ; + RECT 102.265 97.835 102.435 98.005 ; + RECT 101.805 97.835 101.975 98.005 ; + RECT 101.345 97.835 101.515 98.005 ; + RECT 100.885 97.835 101.055 98.005 ; + RECT 100.425 97.835 100.595 98.005 ; + RECT 99.965 97.835 100.135 98.005 ; + RECT 99.505 97.835 99.675 98.005 ; + RECT 99.045 97.835 99.215 98.005 ; + RECT 98.585 97.835 98.755 98.005 ; + RECT 98.125 97.835 98.295 98.005 ; + RECT 97.665 97.835 97.835 98.005 ; + RECT 97.205 97.835 97.375 98.005 ; + RECT 96.745 97.835 96.915 98.005 ; + RECT 96.285 97.835 96.455 98.005 ; + RECT 95.825 97.835 95.995 98.005 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; RECT 84.325 97.835 84.495 98.005 ; RECT 83.865 97.835 84.035 98.005 ; RECT 83.405 97.835 83.575 98.005 ; @@ -2276,586 +2584,474 @@ MACRO sb_1__1_ RECT 19.465 97.835 19.635 98.005 ; RECT 19.005 97.835 19.175 98.005 ; RECT 18.545 97.835 18.715 98.005 ; - RECT 84.325 95.115 84.495 95.285 ; - RECT 83.865 95.115 84.035 95.285 ; - RECT 19.005 95.115 19.175 95.285 ; - RECT 18.545 95.115 18.715 95.285 ; - RECT 84.325 92.395 84.495 92.565 ; - RECT 83.865 92.395 84.035 92.565 ; - RECT 19.005 92.395 19.175 92.565 ; - RECT 18.545 92.395 18.715 92.565 ; - RECT 84.325 89.675 84.495 89.845 ; - RECT 83.865 89.675 84.035 89.845 ; - RECT 19.005 89.675 19.175 89.845 ; - RECT 18.545 89.675 18.715 89.845 ; - RECT 84.325 86.955 84.495 87.125 ; - RECT 83.865 86.955 84.035 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 84.325 84.235 84.495 84.405 ; - RECT 83.865 84.235 84.035 84.405 ; - RECT 19.005 84.235 19.175 84.405 ; - RECT 18.545 84.235 18.715 84.405 ; - RECT 102.725 81.515 102.895 81.685 ; - RECT 102.265 81.515 102.435 81.685 ; - RECT 101.805 81.515 101.975 81.685 ; - RECT 101.345 81.515 101.515 81.685 ; - RECT 100.885 81.515 101.055 81.685 ; - RECT 100.425 81.515 100.595 81.685 ; - RECT 99.965 81.515 100.135 81.685 ; - RECT 99.505 81.515 99.675 81.685 ; - RECT 99.045 81.515 99.215 81.685 ; - RECT 98.585 81.515 98.755 81.685 ; - RECT 98.125 81.515 98.295 81.685 ; - RECT 97.665 81.515 97.835 81.685 ; - RECT 97.205 81.515 97.375 81.685 ; - RECT 96.745 81.515 96.915 81.685 ; - RECT 96.285 81.515 96.455 81.685 ; - RECT 95.825 81.515 95.995 81.685 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; - RECT 94.445 81.515 94.615 81.685 ; - RECT 93.985 81.515 94.155 81.685 ; - RECT 93.525 81.515 93.695 81.685 ; - RECT 93.065 81.515 93.235 81.685 ; - RECT 92.605 81.515 92.775 81.685 ; - RECT 92.145 81.515 92.315 81.685 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 90.765 81.515 90.935 81.685 ; - RECT 90.305 81.515 90.475 81.685 ; - RECT 89.845 81.515 90.015 81.685 ; - RECT 89.385 81.515 89.555 81.685 ; - RECT 88.925 81.515 89.095 81.685 ; - RECT 88.465 81.515 88.635 81.685 ; - RECT 88.005 81.515 88.175 81.685 ; - RECT 87.545 81.515 87.715 81.685 ; - RECT 87.085 81.515 87.255 81.685 ; - RECT 86.625 81.515 86.795 81.685 ; - RECT 86.165 81.515 86.335 81.685 ; - RECT 85.705 81.515 85.875 81.685 ; - RECT 85.245 81.515 85.415 81.685 ; - RECT 84.785 81.515 84.955 81.685 ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 122.965 95.115 123.135 95.285 ; + RECT 122.505 95.115 122.675 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 122.965 92.395 123.135 92.565 ; + RECT 122.505 92.395 122.675 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 122.965 89.675 123.135 89.845 ; + RECT 122.505 89.675 122.675 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 122.965 86.955 123.135 87.125 ; + RECT 122.505 86.955 122.675 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 122.965 84.235 123.135 84.405 ; + RECT 122.505 84.235 122.675 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 122.965 81.515 123.135 81.685 ; + RECT 122.505 81.515 122.675 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 102.725 78.795 102.895 78.965 ; - RECT 102.265 78.795 102.435 78.965 ; + RECT 122.965 78.795 123.135 78.965 ; + RECT 122.505 78.795 122.675 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 102.725 76.075 102.895 76.245 ; - RECT 102.265 76.075 102.435 76.245 ; + RECT 122.965 76.075 123.135 76.245 ; + RECT 122.505 76.075 122.675 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 102.725 73.355 102.895 73.525 ; - RECT 102.265 73.355 102.435 73.525 ; + RECT 122.965 73.355 123.135 73.525 ; + RECT 122.505 73.355 122.675 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 102.725 70.635 102.895 70.805 ; - RECT 102.265 70.635 102.435 70.805 ; + RECT 122.965 70.635 123.135 70.805 ; + RECT 122.505 70.635 122.675 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 102.725 67.915 102.895 68.085 ; - RECT 102.265 67.915 102.435 68.085 ; + RECT 122.965 67.915 123.135 68.085 ; + RECT 122.505 67.915 122.675 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 102.725 65.195 102.895 65.365 ; - RECT 102.265 65.195 102.435 65.365 ; + RECT 122.965 65.195 123.135 65.365 ; + RECT 122.505 65.195 122.675 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 102.725 62.475 102.895 62.645 ; - RECT 102.265 62.475 102.435 62.645 ; + RECT 122.965 62.475 123.135 62.645 ; + RECT 122.505 62.475 122.675 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 102.725 59.755 102.895 59.925 ; - RECT 102.265 59.755 102.435 59.925 ; + RECT 122.965 59.755 123.135 59.925 ; + RECT 122.505 59.755 122.675 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 102.725 57.035 102.895 57.205 ; - RECT 102.265 57.035 102.435 57.205 ; + RECT 122.965 57.035 123.135 57.205 ; + RECT 122.505 57.035 122.675 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 102.725 54.315 102.895 54.485 ; - RECT 102.265 54.315 102.435 54.485 ; + RECT 122.965 54.315 123.135 54.485 ; + RECT 122.505 54.315 122.675 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 102.725 51.595 102.895 51.765 ; - RECT 102.265 51.595 102.435 51.765 ; + RECT 122.965 51.595 123.135 51.765 ; + RECT 122.505 51.595 122.675 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 102.725 48.875 102.895 49.045 ; - RECT 102.265 48.875 102.435 49.045 ; + RECT 122.965 48.875 123.135 49.045 ; + RECT 122.505 48.875 122.675 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 102.725 46.155 102.895 46.325 ; - RECT 102.265 46.155 102.435 46.325 ; + RECT 122.965 46.155 123.135 46.325 ; + RECT 122.505 46.155 122.675 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 102.725 43.435 102.895 43.605 ; - RECT 102.265 43.435 102.435 43.605 ; + RECT 122.965 43.435 123.135 43.605 ; + RECT 122.505 43.435 122.675 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 102.725 40.715 102.895 40.885 ; - RECT 102.265 40.715 102.435 40.885 ; + RECT 122.965 40.715 123.135 40.885 ; + RECT 122.505 40.715 122.675 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 102.725 37.995 102.895 38.165 ; - RECT 102.265 37.995 102.435 38.165 ; + RECT 122.965 37.995 123.135 38.165 ; + RECT 122.505 37.995 122.675 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 102.725 35.275 102.895 35.445 ; - RECT 102.265 35.275 102.435 35.445 ; + RECT 122.965 35.275 123.135 35.445 ; + RECT 122.505 35.275 122.675 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 102.725 32.555 102.895 32.725 ; - RECT 102.265 32.555 102.435 32.725 ; + RECT 122.965 32.555 123.135 32.725 ; + RECT 122.505 32.555 122.675 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 102.725 29.835 102.895 30.005 ; - RECT 102.265 29.835 102.435 30.005 ; + RECT 122.965 29.835 123.135 30.005 ; + RECT 122.505 29.835 122.675 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 102.725 27.115 102.895 27.285 ; - RECT 102.265 27.115 102.435 27.285 ; + RECT 122.965 27.115 123.135 27.285 ; + RECT 122.505 27.115 122.675 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 102.725 24.395 102.895 24.565 ; - RECT 102.265 24.395 102.435 24.565 ; + RECT 122.965 24.395 123.135 24.565 ; + RECT 122.505 24.395 122.675 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 102.725 21.675 102.895 21.845 ; - RECT 102.265 21.675 102.435 21.845 ; + RECT 122.965 21.675 123.135 21.845 ; + RECT 122.505 21.675 122.675 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 102.725 18.955 102.895 19.125 ; - RECT 102.265 18.955 102.435 19.125 ; + RECT 122.965 18.955 123.135 19.125 ; + RECT 122.505 18.955 122.675 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 102.725 16.235 102.895 16.405 ; - RECT 102.265 16.235 102.435 16.405 ; - RECT 101.805 16.235 101.975 16.405 ; - RECT 101.345 16.235 101.515 16.405 ; - RECT 100.885 16.235 101.055 16.405 ; - RECT 100.425 16.235 100.595 16.405 ; - RECT 99.965 16.235 100.135 16.405 ; - RECT 99.505 16.235 99.675 16.405 ; - RECT 99.045 16.235 99.215 16.405 ; - RECT 98.585 16.235 98.755 16.405 ; - RECT 98.125 16.235 98.295 16.405 ; - RECT 97.665 16.235 97.835 16.405 ; - RECT 97.205 16.235 97.375 16.405 ; - RECT 96.745 16.235 96.915 16.405 ; - RECT 96.285 16.235 96.455 16.405 ; - RECT 95.825 16.235 95.995 16.405 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; - RECT 94.445 16.235 94.615 16.405 ; - RECT 93.985 16.235 94.155 16.405 ; - RECT 93.525 16.235 93.695 16.405 ; - RECT 93.065 16.235 93.235 16.405 ; - RECT 92.605 16.235 92.775 16.405 ; - RECT 92.145 16.235 92.315 16.405 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 90.765 16.235 90.935 16.405 ; - RECT 90.305 16.235 90.475 16.405 ; - RECT 89.845 16.235 90.015 16.405 ; - RECT 89.385 16.235 89.555 16.405 ; - RECT 88.925 16.235 89.095 16.405 ; - RECT 88.465 16.235 88.635 16.405 ; - RECT 88.005 16.235 88.175 16.405 ; - RECT 87.545 16.235 87.715 16.405 ; - RECT 87.085 16.235 87.255 16.405 ; - RECT 86.625 16.235 86.795 16.405 ; - RECT 86.165 16.235 86.335 16.405 ; - RECT 85.705 16.235 85.875 16.405 ; - RECT 85.245 16.235 85.415 16.405 ; - RECT 84.785 16.235 84.955 16.405 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 122.965 16.235 123.135 16.405 ; + RECT 122.505 16.235 122.675 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; - RECT 19.005 13.515 19.175 13.685 ; - RECT 18.545 13.515 18.715 13.685 ; + RECT 122.965 13.515 123.135 13.685 ; + RECT 122.505 13.515 122.675 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 122.965 10.795 123.135 10.965 ; + RECT 122.505 10.795 122.675 10.965 ; + RECT 122.045 10.795 122.215 10.965 ; + RECT 121.585 10.795 121.755 10.965 ; + RECT 121.125 10.795 121.295 10.965 ; + RECT 120.665 10.795 120.835 10.965 ; + RECT 120.205 10.795 120.375 10.965 ; + RECT 119.745 10.795 119.915 10.965 ; + RECT 119.285 10.795 119.455 10.965 ; + RECT 118.825 10.795 118.995 10.965 ; + RECT 118.365 10.795 118.535 10.965 ; + RECT 117.905 10.795 118.075 10.965 ; + RECT 117.445 10.795 117.615 10.965 ; + RECT 116.985 10.795 117.155 10.965 ; + RECT 116.525 10.795 116.695 10.965 ; + RECT 116.065 10.795 116.235 10.965 ; + RECT 115.605 10.795 115.775 10.965 ; + RECT 115.145 10.795 115.315 10.965 ; + RECT 114.685 10.795 114.855 10.965 ; + RECT 114.225 10.795 114.395 10.965 ; + RECT 113.765 10.795 113.935 10.965 ; + RECT 113.305 10.795 113.475 10.965 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 111.925 10.795 112.095 10.965 ; + RECT 111.465 10.795 111.635 10.965 ; + RECT 111.005 10.795 111.175 10.965 ; + RECT 110.545 10.795 110.715 10.965 ; + RECT 110.085 10.795 110.255 10.965 ; + RECT 109.625 10.795 109.795 10.965 ; + RECT 109.165 10.795 109.335 10.965 ; + RECT 108.705 10.795 108.875 10.965 ; + RECT 108.245 10.795 108.415 10.965 ; + RECT 107.785 10.795 107.955 10.965 ; + RECT 107.325 10.795 107.495 10.965 ; + RECT 106.865 10.795 107.035 10.965 ; + RECT 106.405 10.795 106.575 10.965 ; + RECT 105.945 10.795 106.115 10.965 ; + RECT 105.485 10.795 105.655 10.965 ; + RECT 105.025 10.795 105.195 10.965 ; + RECT 104.565 10.795 104.735 10.965 ; + RECT 104.105 10.795 104.275 10.965 ; + RECT 103.645 10.795 103.815 10.965 ; + RECT 103.185 10.795 103.355 10.965 ; + RECT 102.725 10.795 102.895 10.965 ; + RECT 102.265 10.795 102.435 10.965 ; + RECT 101.805 10.795 101.975 10.965 ; + RECT 101.345 10.795 101.515 10.965 ; + RECT 100.885 10.795 101.055 10.965 ; + RECT 100.425 10.795 100.595 10.965 ; + RECT 99.965 10.795 100.135 10.965 ; + RECT 99.505 10.795 99.675 10.965 ; + RECT 99.045 10.795 99.215 10.965 ; + RECT 98.585 10.795 98.755 10.965 ; + RECT 98.125 10.795 98.295 10.965 ; + RECT 97.665 10.795 97.835 10.965 ; + RECT 97.205 10.795 97.375 10.965 ; + RECT 96.745 10.795 96.915 10.965 ; + RECT 96.285 10.795 96.455 10.965 ; + RECT 95.825 10.795 95.995 10.965 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; RECT 84.325 10.795 84.495 10.965 ; RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; RECT 19.005 10.795 19.175 10.965 ; RECT 18.545 10.795 18.715 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; - RECT 19.005 8.075 19.175 8.245 ; - RECT 18.545 8.075 18.715 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; - RECT 19.005 5.355 19.175 5.525 ; - RECT 18.545 5.355 18.715 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; - RECT 19.005 2.635 19.175 2.805 ; - RECT 18.545 2.635 18.715 2.805 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; + RECT 28.205 8.075 28.375 8.245 ; + RECT 27.745 8.075 27.915 8.245 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; + RECT 28.205 5.355 28.375 5.525 ; + RECT 27.745 5.355 27.915 5.525 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; + RECT 28.205 2.635 28.375 2.805 ; + RECT 27.745 2.635 27.915 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -2980,74 +3176,59 @@ MACRO sb_1__1_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; LAYER via ; - RECT 73.525 97.845 73.675 97.995 ; - RECT 44.085 97.845 44.235 97.995 ; - RECT 68.005 96.145 68.155 96.295 ; - RECT 56.045 96.145 56.195 96.295 ; - RECT 51.445 96.145 51.595 96.295 ; - RECT 45.465 96.145 45.615 96.295 ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 97.905 17.945 98.055 18.095 ; - RECT 94.225 17.945 94.375 18.095 ; - RECT 6.365 17.945 6.515 18.095 ; - RECT 4.525 17.945 4.675 18.095 ; - RECT 73.525 16.245 73.675 16.395 ; - RECT 44.085 16.245 44.235 16.395 ; - RECT 80.885 1.625 81.035 1.775 ; + RECT 83.645 108.725 83.795 108.875 ; + RECT 54.205 108.725 54.355 108.875 ; + RECT 87.785 107.025 87.935 107.175 ; + RECT 35.805 107.025 35.955 107.175 ; + RECT 68.465 98.365 68.615 98.515 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 10.045 97.845 10.195 97.995 ; + RECT 17.865 96.145 18.015 96.295 ; + RECT 12.805 96.145 12.955 96.295 ; + RECT 112.625 12.505 112.775 12.655 ; + RECT 4.065 12.505 4.215 12.655 ; + RECT 83.645 10.805 83.795 10.955 ; + RECT 54.205 10.805 54.355 10.955 ; + RECT 10.045 10.805 10.195 10.955 ; + RECT 88.705 1.625 88.855 1.775 ; + RECT 79.505 1.625 79.655 1.775 ; RECT 63.405 1.625 63.555 1.775 ; - RECT 46.845 1.625 46.995 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 50.985 1.625 51.135 1.775 ; + RECT 48.225 1.625 48.375 1.775 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; LAYER via2 ; - RECT 73.5 97.82 73.7 98.02 ; - RECT 44.06 97.82 44.26 98.02 ; - RECT 1.74 77.42 1.94 77.62 ; - RECT 1.28 67.22 1.48 67.42 ; - RECT 101.56 59.74 101.76 59.94 ; - RECT 1.74 51.58 1.94 51.78 ; - RECT 101.56 49.54 101.76 49.74 ; - RECT 101.1 47.5 101.3 47.7 ; - RECT 1.28 40.02 1.48 40.22 ; - RECT 1.74 38.66 1.94 38.86 ; - RECT 1.28 35.94 1.48 36.14 ; - RECT 101.56 33.22 101.76 33.42 ; - RECT 1.74 33.22 1.94 33.42 ; - RECT 1.74 25.06 1.94 25.26 ; - RECT 1.74 20.98 1.94 21.18 ; - RECT 19.68 6.7 19.88 6.9 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 108.7 83.82 108.9 ; + RECT 54.18 108.7 54.38 108.9 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.28 89.66 1.48 89.86 ; + RECT 121.8 83.54 122 83.74 ; + RECT 121.8 76.74 122 76.94 ; + RECT 121.8 71.3 122 71.5 ; + RECT 1.28 69.26 1.48 69.46 ; + RECT 1.28 65.86 1.48 66.06 ; + RECT 121.34 64.5 121.54 64.7 ; + RECT 1.28 60.42 1.48 60.62 ; + RECT 121.8 55.66 122 55.86 ; + RECT 121.34 52.94 121.54 53.14 ; + RECT 121.8 45.46 122 45.66 ; + RECT 1.28 40.7 1.48 40.9 ; + RECT 121.8 31.86 122 32.06 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER via3 ; - RECT 73.5 97.82 73.7 98.02 ; - RECT 44.06 97.82 44.26 98.02 ; - RECT 1.74 55.66 1.94 55.86 ; - RECT 1.74 34.58 1.94 34.78 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 108.7 83.82 108.9 ; + RECT 54.18 108.7 54.38 108.9 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.74 36.62 1.94 36.82 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER OVERLAP ; - POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 84.64 97.92 84.64 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 ; + POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 27.6 97.92 27.6 108.8 95.68 108.8 95.68 97.92 123.28 97.92 123.28 10.88 95.68 10.88 95.68 0 ; END END sb_1__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef index 44a8877..99a1413 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_1__2__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_1__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 103.04 BY 81.6 ; + SIZE 123.28 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 55.59 0 55.73 1.36 ; END END prog_clk[0] PIN chanx_right_in[0] @@ -371,7 +371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 54.25 103.04 54.55 ; + RECT 121.9 71.25 123.28 71.55 ; END END chanx_right_in[0] PIN chanx_right_in[1] @@ -379,7 +379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 42.01 103.04 42.31 ; + RECT 121.9 34.53 123.28 34.83 ; END END chanx_right_in[1] PIN chanx_right_in[2] @@ -387,7 +387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 56.29 103.04 56.59 ; + RECT 121.9 73.97 123.28 74.27 ; END END chanx_right_in[2] PIN chanx_right_in[3] @@ -395,7 +395,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 26.37 103.04 26.67 ; + RECT 121.9 81.45 123.28 81.75 ; END END chanx_right_in[3] PIN chanx_right_in[4] @@ -403,7 +403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 35.89 103.04 36.19 ; + RECT 121.9 35.89 123.28 36.19 ; END END chanx_right_in[4] PIN chanx_right_in[5] @@ -411,7 +411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 69.21 103.04 69.51 ; + RECT 121.9 17.53 123.28 17.83 ; END END chanx_right_in[5] PIN chanx_right_in[6] @@ -419,7 +419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 33.17 103.04 33.47 ; + RECT 121.9 40.65 123.28 40.95 ; END END chanx_right_in[6] PIN chanx_right_in[7] @@ -427,7 +427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 63.77 103.04 64.07 ; + RECT 121.9 50.17 123.28 50.47 ; END END chanx_right_in[7] PIN chanx_right_in[8] @@ -435,7 +435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 43.37 103.04 43.67 ; + RECT 121.9 76.69 123.28 76.99 ; END END chanx_right_in[8] PIN chanx_right_in[9] @@ -443,7 +443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 76.01 103.04 76.31 ; + RECT 121.9 61.05 123.28 61.35 ; END END chanx_right_in[9] PIN chanx_right_in[10] @@ -451,7 +451,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 40.65 103.04 40.95 ; + RECT 121.9 72.61 123.28 72.91 ; END END chanx_right_in[10] PIN chanx_right_in[11] @@ -459,7 +459,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 77.37 103.04 77.67 ; + RECT 121.9 80.09 123.28 80.39 ; END END chanx_right_in[11] PIN chanx_right_in[12] @@ -467,7 +467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 59.01 103.04 59.31 ; + RECT 121.9 57.65 123.28 57.95 ; END END chanx_right_in[12] PIN chanx_right_in[13] @@ -475,15 +475,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 22.97 103.04 23.27 ; + RECT 121.9 67.85 123.28 68.15 ; END END chanx_right_in[13] PIN chanx_right_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 100.67 16.32 100.81 17.68 ; + LAYER met3 ; + RECT 121.9 54.93 123.28 55.23 ; END END chanx_right_in[14] PIN chanx_right_in[15] @@ -491,7 +491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 67.85 103.04 68.15 ; + RECT 121.9 52.89 123.28 53.19 ; END END chanx_right_in[15] PIN chanx_right_in[16] @@ -499,7 +499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 44.73 103.04 45.03 ; + RECT 121.9 59.69 123.28 59.99 ; END END chanx_right_in[16] PIN chanx_right_in[17] @@ -507,7 +507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 21.61 103.04 21.91 ; + RECT 121.9 84.17 123.28 84.47 ; END END chanx_right_in[17] PIN chanx_right_in[18] @@ -515,7 +515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 61.05 103.04 61.35 ; + RECT 121.9 75.33 123.28 75.63 ; END END chanx_right_in[18] PIN chanx_right_in[19] @@ -523,7 +523,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 65.13 103.04 65.43 ; + RECT 121.9 62.41 123.28 62.71 ; END END chanx_right_in[19] PIN right_top_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 37.25 103.04 37.55 ; + RECT 121.9 37.25 123.28 37.55 ; END END right_top_grid_pin_1_[0] PIN right_bottom_grid_pin_34_[0] @@ -539,7 +539,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 97.91 16.32 98.05 17.68 ; + RECT 114.93 10.88 115.07 12.24 ; END END right_bottom_grid_pin_34_[0] PIN right_bottom_grid_pin_35_[0] @@ -547,15 +547,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 99.75 16.32 99.89 17.68 ; + RECT 115.85 10.88 115.99 12.24 ; END END right_bottom_grid_pin_35_[0] PIN right_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 97.37 16.32 97.67 17.68 ; + LAYER met2 ; + RECT 109.87 10.88 110.01 12.24 ; END END right_bottom_grid_pin_36_[0] PIN right_bottom_grid_pin_37_[0] @@ -563,7 +563,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 94.23 16.32 94.37 17.68 ; + RECT 112.63 10.88 112.77 12.24 ; END END right_bottom_grid_pin_37_[0] PIN right_bottom_grid_pin_38_[0] @@ -571,15 +571,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 95.15 16.32 95.29 17.68 ; + RECT 118.61 10.88 118.75 12.24 ; END END right_bottom_grid_pin_38_[0] PIN right_bottom_grid_pin_39_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 83.26 5.29 84.64 5.59 ; + LAYER met2 ; + RECT 116.77 10.88 116.91 12.24 ; END END right_bottom_grid_pin_39_[0] PIN right_bottom_grid_pin_40_[0] @@ -587,7 +587,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 96.53 16.32 96.67 17.68 ; + RECT 117.69 10.88 117.83 12.24 ; END END right_bottom_grid_pin_40_[0] PIN right_bottom_grid_pin_41_[0] @@ -595,7 +595,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 82.27 0 82.41 1.36 ; + RECT 114.01 10.88 114.15 12.24 ; END END right_bottom_grid_pin_41_[0] PIN chany_bottom_in[0] @@ -603,7 +603,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.53 0 50.67 1.36 ; + RECT 68.47 0 68.61 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -611,7 +611,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.89 0 58.03 1.36 ; + RECT 69.39 0 69.53 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] @@ -619,7 +619,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.97 0 57.11 1.36 ; + RECT 80.43 0 80.57 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.49 0 62.63 1.36 ; + RECT 70.31 0 70.45 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.69 0 48.83 1.36 ; + RECT 60.65 0 60.79 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 0 60.33 1.36 ; + RECT 64.33 0 64.47 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 77.21 0 77.35 1.36 ; + RECT 61.57 0 61.71 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 0 52.51 1.36 ; + RECT 74.45 0 74.59 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 0 61.25 1.36 ; + RECT 67.55 0 67.69 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.05 0 56.19 1.36 ; + RECT 71.23 0 71.37 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.61 0 49.75 1.36 ; + RECT 75.37 0 75.51 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -699,7 +699,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.77 0 47.91 1.36 ; + RECT 66.63 0 66.77 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -707,7 +707,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 71.23 0 71.37 1.36 ; + RECT 48.23 0 48.37 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 75.37 0 75.51 1.36 ; + RECT 81.35 0 81.49 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.59 0 32.73 1.36 ; + RECT 49.15 0 49.29 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 0 51.59 1.36 ; + RECT 59.73 0 59.87 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 74.45 0 74.59 1.36 ; + RECT 63.41 0 63.55 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 76.29 0 76.43 1.36 ; + RECT 65.71 0 65.85 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,7 +755,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 0 54.35 1.36 ; + RECT 78.59 0 78.73 1.36 ; END END chany_bottom_in[19] PIN bottom_left_grid_pin_42_[0] @@ -763,15 +763,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + RECT 11.43 10.88 11.57 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 0 23.15 1.36 ; + LAYER met2 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] @@ -779,7 +779,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.51 16.32 10.65 17.68 ; + RECT 12.35 10.88 12.49 12.24 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -787,7 +787,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 16.32 4.67 17.68 ; + RECT 14.19 10.88 14.33 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -795,31 +795,31 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.69 16.32 2.83 17.68 ; + RECT 16.03 10.88 16.17 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 12.09 19.78 12.39 ; + LAYER met2 ; + RECT 17.87 10.88 18.01 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 6.83 16.32 6.97 17.68 ; + LAYER met4 ; + RECT 5.37 10.88 5.67 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 9.59 16.32 9.73 17.68 ; + LAYER met4 ; + RECT 11.81 10.88 12.11 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -827,7 +827,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -835,7 +835,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -843,7 +843,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -851,7 +851,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -859,7 +859,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -867,7 +867,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -875,7 +875,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -883,7 +883,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -891,7 +891,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -899,7 +899,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -907,7 +907,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -915,7 +915,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -923,7 +923,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -931,7 +931,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 22.29 1.38 22.59 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -939,7 +939,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -947,7 +947,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -955,7 +955,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -963,7 +963,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -971,7 +971,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -979,7 +979,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[19] PIN left_top_grid_pin_1_[0] @@ -987,31 +987,31 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 55.61 1.38 55.91 ; END END left_top_grid_pin_1_[0] PIN left_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 6.65 19.78 6.95 ; + LAYER met2 ; + RECT 15.11 10.88 15.25 12.24 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 16.32 4.75 17.68 ; + LAYER met2 ; + RECT 13.27 10.88 13.41 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 5.29 19.78 5.59 ; + LAYER met2 ; + RECT 4.99 10.88 5.13 12.24 ; END END left_bottom_grid_pin_36_[0] PIN left_bottom_grid_pin_37_[0] @@ -1019,7 +1019,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 16.32 5.59 17.68 ; + RECT 5.91 10.88 6.05 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1027,7 +1027,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 7.75 10.88 7.89 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] @@ -1035,7 +1035,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -1043,7 +1043,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 3.15 10.88 3.29 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1051,7 +1051,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 16.32 7.89 17.68 ; + RECT 6.83 10.88 6.97 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1059,7 +1059,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 47.45 103.04 47.75 ; + RECT 121.9 42.69 123.28 42.99 ; END END ccff_head[0] PIN chanx_right_out[0] @@ -1067,7 +1067,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 52.89 103.04 53.19 ; + RECT 121.9 31.81 123.28 32.11 ; END END chanx_right_out[0] PIN chanx_right_out[1] @@ -1075,7 +1075,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 29.09 103.04 29.39 ; + RECT 121.9 33.17 123.28 33.47 ; END END chanx_right_out[1] PIN chanx_right_out[2] @@ -1083,7 +1083,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 50.17 103.04 50.47 ; + RECT 121.9 29.09 123.28 29.39 ; END END chanx_right_out[2] PIN chanx_right_out[3] @@ -1091,7 +1091,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 31.81 103.04 32.11 ; + RECT 121.9 30.45 123.28 30.75 ; END END chanx_right_out[3] PIN chanx_right_out[4] @@ -1099,7 +1099,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 70.57 103.04 70.87 ; + RECT 121.9 63.77 123.28 64.07 ; END END chanx_right_out[4] PIN chanx_right_out[5] @@ -1107,7 +1107,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 24.33 103.04 24.63 ; + RECT 121.9 19.57 123.28 19.87 ; END END chanx_right_out[5] PIN chanx_right_out[6] @@ -1115,7 +1115,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 66.49 103.04 66.79 ; + RECT 121.9 46.09 123.28 46.39 ; END END chanx_right_out[6] PIN chanx_right_out[7] @@ -1123,7 +1123,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 51.53 103.04 51.83 ; + RECT 121.9 27.73 123.28 28.03 ; END END chanx_right_out[7] PIN chanx_right_out[8] @@ -1131,7 +1131,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 34.53 103.04 34.83 ; + RECT 121.9 48.13 123.28 48.43 ; END END chanx_right_out[8] PIN chanx_right_out[9] @@ -1139,7 +1139,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 20.25 103.04 20.55 ; + RECT 121.9 24.33 123.28 24.63 ; END END chanx_right_out[9] PIN chanx_right_out[10] @@ -1147,7 +1147,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 71.93 103.04 72.23 ; + RECT 121.9 51.53 123.28 51.83 ; END END chanx_right_out[10] PIN chanx_right_out[11] @@ -1155,7 +1155,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 30.45 103.04 30.75 ; + RECT 121.9 22.97 123.28 23.27 ; END END chanx_right_out[11] PIN chanx_right_out[12] @@ -1163,7 +1163,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 39.29 103.04 39.59 ; + RECT 121.9 56.29 123.28 56.59 ; END END chanx_right_out[12] PIN chanx_right_out[13] @@ -1171,7 +1171,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 27.73 103.04 28.03 ; + RECT 121.9 26.37 123.28 26.67 ; END END chanx_right_out[13] PIN chanx_right_out[14] @@ -1179,7 +1179,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 48.81 103.04 49.11 ; + RECT 121.9 44.05 123.28 44.35 ; END END chanx_right_out[14] PIN chanx_right_out[15] @@ -1187,7 +1187,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 74.65 103.04 74.95 ; + RECT 121.9 38.61 123.28 38.91 ; END END chanx_right_out[15] PIN chanx_right_out[16] @@ -1195,7 +1195,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 57.65 103.04 57.95 ; + RECT 121.9 69.89 123.28 70.19 ; END END chanx_right_out[16] PIN chanx_right_out[17] @@ -1203,7 +1203,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 46.09 103.04 46.39 ; + RECT 121.9 82.81 123.28 83.11 ; END END chanx_right_out[17] PIN chanx_right_out[18] @@ -1211,7 +1211,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 73.29 103.04 73.59 ; + RECT 121.9 65.81 123.28 66.11 ; END END chanx_right_out[18] PIN chanx_right_out[19] @@ -1219,7 +1219,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 101.66 62.41 103.04 62.71 ; + RECT 121.9 21.61 123.28 21.91 ; END END chanx_right_out[19] PIN chany_bottom_out[0] @@ -1227,7 +1227,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 72.15 0 72.29 1.36 ; + RECT 57.89 0 58.03 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1235,7 +1235,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 55.13 0 55.27 1.36 ; + RECT 62.49 0 62.63 1.36 ; END END chany_bottom_out[1] PIN chany_bottom_out[2] @@ -1243,7 +1243,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.85 0 46.99 1.36 ; + RECT 58.81 0 58.95 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1251,7 +1251,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.41 0 63.55 1.36 ; + RECT 79.51 0 79.65 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1259,7 +1259,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.93 0 46.07 1.36 ; + RECT 52.83 0 52.97 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1267,7 +1267,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 70.31 0 70.45 1.36 ; + RECT 87.79 0 87.93 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1275,7 +1275,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.51 0 33.65 1.36 ; + RECT 50.07 0 50.21 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1283,7 +1283,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 77.67 0 77.81 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1291,7 +1291,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 0 59.41 1.36 ; + RECT 85.49 0 85.63 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1299,7 +1299,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 65.71 0 65.85 1.36 ; + RECT 73.07 0 73.21 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1307,7 +1307,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 51.91 0 52.05 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1315,7 +1315,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 66.63 0 66.77 1.36 ; + RECT 76.75 0 76.89 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1323,7 +1323,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1331,7 +1331,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 67.55 0 67.69 1.36 ; + RECT 88.71 0 88.85 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1339,7 +1339,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 50.99 0 51.13 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1347,7 +1347,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 80.89 0 81.03 1.36 ; + RECT 89.63 0 89.77 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1355,7 +1355,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + RECT 84.57 0 84.71 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1363,7 +1363,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 68.47 0 68.61 1.36 ; + RECT 72.15 0 72.29 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1371,7 +1371,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.01 0 45.15 1.36 ; + RECT 56.97 0 57.11 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1379,7 +1379,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 69.39 0 69.53 1.36 ; + RECT 90.55 0 90.69 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1387,7 +1387,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1395,7 +1395,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 89.61 1.38 89.91 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1403,7 +1403,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1411,7 +1411,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1419,7 +1419,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1427,7 +1427,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1435,7 +1435,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1443,7 +1443,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1451,15 +1451,15 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 6.29 16.32 6.59 17.68 ; + LAYER met3 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1467,7 +1467,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1475,7 +1475,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1483,7 +1483,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1491,7 +1491,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1499,7 +1499,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1507,7 +1507,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1515,7 +1515,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1523,7 +1523,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1531,7 +1531,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1539,7 +1539,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1547,7 +1547,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 31.81 1.38 32.11 ; END END ccff_tail[0] PIN SC_IN_TOP @@ -1555,7 +1555,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 54.21 80.24 54.35 81.6 ; + RECT 64.33 96.56 64.47 97.92 ; END END SC_IN_TOP PIN SC_IN_BOT @@ -1563,7 +1563,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.29 80.24 53.43 81.6 ; + RECT 63.41 96.56 63.55 97.92 ; END END SC_IN_BOT PIN SC_OUT_TOP @@ -1571,7 +1571,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.37 80.24 52.51 81.6 ; + RECT 62.49 96.56 62.63 97.92 ; END END SC_OUT_TOP PIN SC_OUT_BOT @@ -1579,7 +1579,7 @@ MACRO sb_1__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.45 80.24 51.59 81.6 ; + RECT 61.57 96.56 61.71 97.92 ; END END SC_OUT_BOT PIN VDD @@ -1587,46 +1587,54 @@ MACRO sb_1__2_ USE POWER ; PORT LAYER met1 ; - RECT 18.4 2.48 18.88 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; - RECT 18.4 7.92 18.88 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; - RECT 18.4 13.36 18.88 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 27.6 2.48 28.08 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; + RECT 27.6 7.92 28.08 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 122.8 13.36 123.28 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 102.56 18.8 103.04 19.28 ; + RECT 122.8 18.8 123.28 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 102.56 24.24 103.04 24.72 ; + RECT 122.8 24.24 123.28 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 102.56 29.68 103.04 30.16 ; + RECT 122.8 29.68 123.28 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 102.56 35.12 103.04 35.6 ; + RECT 122.8 35.12 123.28 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 102.56 40.56 103.04 41.04 ; + RECT 122.8 40.56 123.28 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 102.56 46 103.04 46.48 ; + RECT 122.8 46 123.28 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 102.56 51.44 103.04 51.92 ; + RECT 122.8 51.44 123.28 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 102.56 56.88 103.04 57.36 ; + RECT 122.8 56.88 123.28 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 102.56 62.32 103.04 62.8 ; + RECT 122.8 62.32 123.28 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 102.56 67.76 103.04 68.24 ; + RECT 122.8 67.76 123.28 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 102.56 73.2 103.04 73.68 ; + RECT 122.8 73.2 123.28 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 102.56 78.64 103.04 79.12 ; + RECT 122.8 78.64 123.28 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 122.8 84.08 123.28 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 122.8 89.52 123.28 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 122.8 94.96 123.28 95.44 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 81 29.74 81.6 ; - RECT 58.58 81 59.18 81.6 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 112.86 10.88 113.46 11.48 ; + RECT 39.26 97.32 39.86 97.92 ; + RECT 68.7 97.32 69.3 97.92 ; + RECT 112.86 97.32 113.46 97.92 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 99.84 26.96 103.04 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 99.84 67.76 103.04 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 120.08 22.2 123.28 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 120.08 63 123.28 66.2 ; END END VDD PIN VSS @@ -1634,698 +1642,875 @@ MACRO sb_1__2_ USE GROUND ; PORT LAYER met1 ; - RECT 18.4 0 84.64 0.24 ; - RECT 18.4 5.2 18.88 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; - RECT 18.4 10.64 18.88 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; - RECT 0 16.08 103.04 16.56 ; + RECT 27.6 0 95.68 0.24 ; + RECT 27.6 5.2 28.08 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; + RECT 0 10.64 123.28 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 122.8 16.08 123.28 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 102.56 21.52 103.04 22 ; + RECT 122.8 21.52 123.28 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 102.56 26.96 103.04 27.44 ; + RECT 122.8 26.96 123.28 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 102.56 32.4 103.04 32.88 ; + RECT 122.8 32.4 123.28 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 102.56 37.84 103.04 38.32 ; + RECT 122.8 37.84 123.28 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 102.56 43.28 103.04 43.76 ; + RECT 122.8 43.28 123.28 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 102.56 48.72 103.04 49.2 ; + RECT 122.8 48.72 123.28 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 102.56 54.16 103.04 54.64 ; + RECT 122.8 54.16 123.28 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 102.56 59.6 103.04 60.08 ; + RECT 122.8 59.6 123.28 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 102.56 65.04 103.04 65.52 ; + RECT 122.8 65.04 123.28 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 102.56 70.48 103.04 70.96 ; + RECT 122.8 70.48 123.28 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 102.56 75.92 103.04 76.4 ; - RECT 0 81.36 103.04 81.6 ; + RECT 122.8 75.92 123.28 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 122.8 81.36 123.28 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 122.8 86.8 123.28 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 122.8 92.24 123.28 92.72 ; + RECT 0 97.68 123.28 97.92 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 81 44.46 81.6 ; - RECT 73.3 81 73.9 81.6 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 10.88 10.42 11.48 ; + RECT 9.82 97.32 10.42 97.92 ; + RECT 53.98 97.32 54.58 97.92 ; + RECT 83.42 97.32 84.02 97.92 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 99.84 47.36 103.04 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 120.08 42.6 123.28 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 120.08 83.4 123.28 86.6 ; END END VSS + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 35.81 0 35.95 1.36 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] + PIN grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met3 ; + RECT 121.9 14.13 123.28 14.43 ; + END + END grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 0 81.515 103.04 81.685 ; - RECT 102.12 78.795 103.04 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 102.12 76.075 103.04 76.245 ; + RECT 0 97.835 123.28 98.005 ; + RECT 122.82 95.115 123.28 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 122.82 92.395 123.28 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 122.82 89.675 123.28 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 122.82 86.955 123.28 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 122.36 84.235 123.28 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 122.36 81.515 123.28 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 122.82 78.795 123.28 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 121.44 76.075 123.28 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 99.36 73.355 103.04 73.525 ; - RECT 0 73.355 1.84 73.525 ; - RECT 99.36 70.635 103.04 70.805 ; - RECT 0 70.635 1.84 70.805 ; - RECT 102.12 67.915 103.04 68.085 ; - RECT 0 67.915 1.84 68.085 ; - RECT 102.12 65.195 103.04 65.365 ; + RECT 119.6 73.355 123.28 73.525 ; + RECT 0 73.355 3.68 73.525 ; + RECT 119.6 70.635 123.28 70.805 ; + RECT 0 70.635 3.68 70.805 ; + RECT 122.36 67.915 123.28 68.085 ; + RECT 0 67.915 3.68 68.085 ; + RECT 119.6 65.195 123.28 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 102.12 62.475 103.04 62.645 ; + RECT 119.6 62.475 123.28 62.645 ; RECT 0 62.475 1.84 62.645 ; - RECT 102.12 59.755 103.04 59.925 ; + RECT 122.36 59.755 123.28 59.925 ; RECT 0 59.755 1.84 59.925 ; - RECT 102.12 57.035 103.04 57.205 ; + RECT 122.36 57.035 123.28 57.205 ; RECT 0 57.035 1.84 57.205 ; - RECT 102.12 54.315 103.04 54.485 ; + RECT 122.36 54.315 123.28 54.485 ; RECT 0 54.315 1.84 54.485 ; - RECT 102.12 51.595 103.04 51.765 ; + RECT 122.36 51.595 123.28 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 102.12 48.875 103.04 49.045 ; + RECT 122.36 48.875 123.28 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 102.12 46.155 103.04 46.325 ; + RECT 122.36 46.155 123.28 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 102.12 43.435 103.04 43.605 ; + RECT 122.36 43.435 123.28 43.605 ; RECT 0 43.435 1.84 43.605 ; - RECT 102.12 40.715 103.04 40.885 ; + RECT 122.36 40.715 123.28 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 102.12 37.995 103.04 38.165 ; + RECT 122.36 37.995 123.28 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 102.12 35.275 103.04 35.445 ; + RECT 122.36 35.275 123.28 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 102.12 32.555 103.04 32.725 ; + RECT 122.36 32.555 123.28 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 102.12 29.835 103.04 30.005 ; + RECT 122.36 29.835 123.28 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 102.12 27.115 103.04 27.285 ; + RECT 122.36 27.115 123.28 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 102.12 24.395 103.04 24.565 ; + RECT 122.36 24.395 123.28 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 102.12 21.675 103.04 21.845 ; + RECT 122.36 21.675 123.28 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 102.12 18.955 103.04 19.125 ; - RECT 0 18.955 3.68 19.125 ; - RECT 82.34 16.235 103.04 16.405 ; - RECT 0 16.235 22.08 16.405 ; - RECT 83.72 13.515 84.64 13.685 ; - RECT 18.4 13.515 22.08 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; - RECT 18.4 10.795 22.08 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; - RECT 18.4 8.075 22.08 8.245 ; - RECT 83.72 5.355 84.64 5.525 ; - RECT 18.4 5.355 22.08 5.525 ; - RECT 83.72 2.635 84.64 2.805 ; - RECT 18.4 2.635 22.08 2.805 ; - RECT 18.4 -0.085 84.64 0.085 ; + RECT 122.36 18.955 123.28 19.125 ; + RECT 0 18.955 1.84 19.125 ; + RECT 122.36 16.235 123.28 16.405 ; + RECT 0 16.235 1.84 16.405 ; + RECT 122.36 13.515 123.28 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 92.92 10.795 123.28 10.965 ; + RECT 0 10.795 29.44 10.965 ; + RECT 94.76 8.075 95.68 8.245 ; + RECT 27.6 8.075 29.44 8.245 ; + RECT 94.76 5.355 95.68 5.525 ; + RECT 27.6 5.355 31.28 5.525 ; + RECT 95.22 2.635 95.68 2.805 ; + RECT 27.6 2.635 31.28 2.805 ; + RECT 27.6 -0.085 95.68 0.085 ; LAYER met2 ; - RECT 73.46 81.415 73.74 81.785 ; - RECT 44.02 81.415 44.3 81.785 ; - RECT 53.69 1.54 53.95 1.86 ; - RECT 47.25 1.54 47.51 1.86 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 102.76 81.32 102.76 16.6 101.09 16.6 101.09 17.96 100.39 17.96 100.39 16.6 100.17 16.6 100.17 17.96 99.47 17.96 99.47 16.6 98.33 16.6 98.33 17.96 97.63 17.96 97.63 16.6 96.95 16.6 96.95 17.96 96.25 17.96 96.25 16.6 95.57 16.6 95.57 17.96 94.87 17.96 94.87 16.6 94.65 16.6 94.65 17.96 93.95 17.96 93.95 16.6 84.36 16.6 84.36 0.28 82.69 0.28 82.69 1.64 81.99 1.64 81.99 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 76.71 0.28 76.71 1.64 76.01 1.64 76.01 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.53 0.28 61.53 1.64 60.83 1.64 60.83 0.28 60.61 0.28 60.61 1.64 59.91 1.64 59.91 0.28 59.69 0.28 59.69 1.64 58.99 1.64 58.99 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.47 0.28 56.47 1.64 55.77 1.64 55.77 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 54.63 0.28 54.63 1.64 53.93 1.64 53.93 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 45.43 0.28 45.43 1.64 44.73 1.64 44.73 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 33.01 0.28 33.01 1.64 32.31 1.64 32.31 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 10.93 16.6 10.93 17.96 10.23 17.96 10.23 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 3.11 16.6 3.11 17.96 2.41 17.96 2.41 16.6 0.28 16.6 0.28 81.32 51.17 81.32 51.17 79.96 51.87 79.96 51.87 81.32 52.09 81.32 52.09 79.96 52.79 79.96 52.79 81.32 53.01 81.32 53.01 79.96 53.71 79.96 53.71 81.32 53.93 81.32 53.93 79.96 54.63 79.96 54.63 81.32 ; + RECT 83.58 97.735 83.86 98.105 ; + RECT 54.14 97.735 54.42 98.105 ; + RECT 9.98 97.735 10.26 98.105 ; + RECT 9.98 10.695 10.26 11.065 ; + RECT 62.89 1.54 63.15 1.86 ; + RECT 61.05 1.54 61.31 1.86 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + POLYGON 123 97.64 123 11.16 119.03 11.16 119.03 12.52 118.33 12.52 118.33 11.16 118.11 11.16 118.11 12.52 117.41 12.52 117.41 11.16 117.19 11.16 117.19 12.52 116.49 12.52 116.49 11.16 116.27 11.16 116.27 12.52 115.57 12.52 115.57 11.16 115.35 11.16 115.35 12.52 114.65 12.52 114.65 11.16 114.43 11.16 114.43 12.52 113.73 12.52 113.73 11.16 113.05 11.16 113.05 12.52 112.35 12.52 112.35 11.16 110.29 11.16 110.29 12.52 109.59 12.52 109.59 11.16 95.4 11.16 95.4 0.28 90.97 0.28 90.97 1.64 90.27 1.64 90.27 0.28 90.05 0.28 90.05 1.64 89.35 1.64 89.35 0.28 89.13 0.28 89.13 1.64 88.43 1.64 88.43 0.28 88.21 0.28 88.21 1.64 87.51 1.64 87.51 0.28 85.91 0.28 85.91 1.64 85.21 1.64 85.21 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 81.77 0.28 81.77 1.64 81.07 1.64 81.07 0.28 80.85 0.28 80.85 1.64 80.15 1.64 80.15 0.28 79.93 0.28 79.93 1.64 79.23 1.64 79.23 0.28 79.01 0.28 79.01 1.64 78.31 1.64 78.31 0.28 78.09 0.28 78.09 1.64 77.39 1.64 77.39 0.28 77.17 0.28 77.17 1.64 76.47 1.64 76.47 0.28 75.79 0.28 75.79 1.64 75.09 1.64 75.09 0.28 74.87 0.28 74.87 1.64 74.17 1.64 74.17 0.28 73.49 0.28 73.49 1.64 72.79 1.64 72.79 0.28 72.57 0.28 72.57 1.64 71.87 1.64 71.87 0.28 71.65 0.28 71.65 1.64 70.95 1.64 70.95 0.28 70.73 0.28 70.73 1.64 70.03 1.64 70.03 0.28 69.81 0.28 69.81 1.64 69.11 1.64 69.11 0.28 68.89 0.28 68.89 1.64 68.19 1.64 68.19 0.28 67.97 0.28 67.97 1.64 67.27 1.64 67.27 0.28 67.05 0.28 67.05 1.64 66.35 1.64 66.35 0.28 66.13 0.28 66.13 1.64 65.43 1.64 65.43 0.28 64.75 0.28 64.75 1.64 64.05 1.64 64.05 0.28 63.83 0.28 63.83 1.64 63.13 1.64 63.13 0.28 62.91 0.28 62.91 1.64 62.21 1.64 62.21 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 59.23 0.28 59.23 1.64 58.53 1.64 58.53 0.28 58.31 0.28 58.31 1.64 57.61 1.64 57.61 0.28 57.39 0.28 57.39 1.64 56.69 1.64 56.69 0.28 56.01 0.28 56.01 1.64 55.31 1.64 55.31 0.28 53.25 0.28 53.25 1.64 52.55 1.64 52.55 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 0.28 11.16 0.28 97.64 61.29 97.64 61.29 96.28 61.99 96.28 61.99 97.64 62.21 97.64 62.21 96.28 62.91 96.28 62.91 97.64 63.13 97.64 63.13 96.28 63.83 96.28 63.83 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 ; LAYER met3 ; - POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; - POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 8.89 72.91 8.89 72.61 1.99 72.61 1.99 71.93 1.78 71.93 1.78 72.63 1.69 72.63 1.69 72.91 ; - POLYGON 101.81 49.79 101.81 49.51 101.26 49.51 101.26 49.49 99.67 49.49 99.67 49.79 ; - POLYGON 101.365 38.925 101.365 38.595 101.035 38.595 101.035 38.61 91.85 38.61 91.85 38.91 101.035 38.91 101.035 38.925 ; - POLYGON 1.545 36.205 1.545 36.2 2.03 36.2 2.03 35.88 1.545 35.88 1.545 35.875 1.215 35.875 1.215 36.205 ; - POLYGON 2.005 28.045 2.005 28.04 2.03 28.04 2.03 27.72 2.005 27.72 2.005 27.715 1.675 27.715 1.675 27.72 0.97 27.72 0.97 28.04 1.675 28.04 1.675 28.045 ; - POLYGON 101.81 23.95 101.81 23.67 101.26 23.67 101.26 23.65 51.37 23.65 51.37 23.95 ; - POLYGON 20.405 13.085 20.405 13.08 20.43 13.08 20.43 12.76 20.405 12.76 20.405 12.755 19.675 12.755 19.675 13.085 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 102.64 81.2 102.64 78.07 101.26 78.07 101.26 76.97 102.64 76.97 102.64 76.71 101.26 76.71 101.26 75.61 102.64 75.61 102.64 75.35 101.26 75.35 101.26 74.25 102.64 74.25 102.64 73.99 101.26 73.99 101.26 72.89 102.64 72.89 102.64 72.63 101.26 72.63 101.26 71.53 102.64 71.53 102.64 71.27 101.26 71.27 101.26 70.17 102.64 70.17 102.64 69.91 101.26 69.91 101.26 68.81 102.64 68.81 102.64 68.55 101.26 68.55 101.26 67.45 102.64 67.45 102.64 67.19 101.26 67.19 101.26 66.09 102.64 66.09 102.64 65.83 101.26 65.83 101.26 64.73 102.64 64.73 102.64 64.47 101.26 64.47 101.26 63.37 102.64 63.37 102.64 63.11 101.26 63.11 101.26 62.01 102.64 62.01 102.64 61.75 101.26 61.75 101.26 60.65 102.64 60.65 102.64 59.71 101.26 59.71 101.26 58.61 102.64 58.61 102.64 58.35 101.26 58.35 101.26 57.25 102.64 57.25 102.64 56.99 101.26 56.99 101.26 55.89 102.64 55.89 102.64 54.95 101.26 54.95 101.26 53.85 102.64 53.85 102.64 53.59 101.26 53.59 101.26 52.49 102.64 52.49 102.64 52.23 101.26 52.23 101.26 51.13 102.64 51.13 102.64 50.87 101.26 50.87 101.26 49.77 102.64 49.77 102.64 49.51 101.26 49.51 101.26 48.41 102.64 48.41 102.64 48.15 101.26 48.15 101.26 47.05 102.64 47.05 102.64 46.79 101.26 46.79 101.26 45.69 102.64 45.69 102.64 45.43 101.26 45.43 101.26 44.33 102.64 44.33 102.64 44.07 101.26 44.07 101.26 42.97 102.64 42.97 102.64 42.71 101.26 42.71 101.26 41.61 102.64 41.61 102.64 41.35 101.26 41.35 101.26 40.25 102.64 40.25 102.64 39.99 101.26 39.99 101.26 38.89 102.64 38.89 102.64 37.95 101.26 37.95 101.26 36.85 102.64 36.85 102.64 36.59 101.26 36.59 101.26 35.49 102.64 35.49 102.64 35.23 101.26 35.23 101.26 34.13 102.64 34.13 102.64 33.87 101.26 33.87 101.26 32.77 102.64 32.77 102.64 32.51 101.26 32.51 101.26 31.41 102.64 31.41 102.64 31.15 101.26 31.15 101.26 30.05 102.64 30.05 102.64 29.79 101.26 29.79 101.26 28.69 102.64 28.69 102.64 28.43 101.26 28.43 101.26 27.33 102.64 27.33 102.64 27.07 101.26 27.07 101.26 25.97 102.64 25.97 102.64 25.03 101.26 25.03 101.26 23.93 102.64 23.93 102.64 23.67 101.26 23.67 101.26 22.57 102.64 22.57 102.64 22.31 101.26 22.31 101.26 21.21 102.64 21.21 102.64 20.95 101.26 20.95 101.26 19.85 102.64 19.85 102.64 16.72 84.24 16.72 84.24 5.99 82.86 5.99 82.86 4.89 84.24 4.89 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 11.69 20.18 11.69 20.18 12.79 18.8 12.79 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 ; + POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; + POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; + POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; + POLYGON 2.91 60.67 2.91 60.37 1.99 60.37 1.99 59.69 1.78 59.69 1.78 60.39 1.69 60.39 1.69 60.67 ; + POLYGON 70.99 59.31 70.99 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; + POLYGON 2.005 53.885 2.005 53.88 2.03 53.88 2.03 53.56 2.005 53.56 2.005 53.555 1.275 53.555 1.275 53.885 ; + POLYGON 121.5 43.67 121.5 43.65 122.97 43.65 122.97 43.37 118.99 43.37 118.99 43.67 ; + POLYGON 1.545 17.165 1.545 17.15 30.51 17.15 30.51 16.85 1.545 16.85 1.545 16.835 1.215 16.835 1.215 17.165 ; + POLYGON 121.63 17.16 121.63 16.84 121.25 16.84 121.25 16.85 91.39 16.85 91.39 17.15 121.25 17.15 121.25 17.16 ; + POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 122.88 97.52 122.88 84.87 121.5 84.87 121.5 83.77 122.88 83.77 122.88 83.51 121.5 83.51 121.5 82.41 122.88 82.41 122.88 82.15 121.5 82.15 121.5 81.05 122.88 81.05 122.88 80.79 121.5 80.79 121.5 79.69 122.88 79.69 122.88 77.39 121.5 77.39 121.5 76.29 122.88 76.29 122.88 76.03 121.5 76.03 121.5 74.93 122.88 74.93 122.88 74.67 121.5 74.67 121.5 73.57 122.88 73.57 122.88 73.31 121.5 73.31 121.5 72.21 122.88 72.21 122.88 71.95 121.5 71.95 121.5 70.85 122.88 70.85 122.88 70.59 121.5 70.59 121.5 69.49 122.88 69.49 122.88 68.55 121.5 68.55 121.5 67.45 122.88 67.45 122.88 66.51 121.5 66.51 121.5 65.41 122.88 65.41 122.88 64.47 121.5 64.47 121.5 63.37 122.88 63.37 122.88 63.11 121.5 63.11 121.5 62.01 122.88 62.01 122.88 61.75 121.5 61.75 121.5 60.65 122.88 60.65 122.88 60.39 121.5 60.39 121.5 59.29 122.88 59.29 122.88 58.35 121.5 58.35 121.5 57.25 122.88 57.25 122.88 56.99 121.5 56.99 121.5 55.89 122.88 55.89 122.88 55.63 121.5 55.63 121.5 54.53 122.88 54.53 122.88 53.59 121.5 53.59 121.5 52.49 122.88 52.49 122.88 52.23 121.5 52.23 121.5 51.13 122.88 51.13 122.88 50.87 121.5 50.87 121.5 49.77 122.88 49.77 122.88 48.83 121.5 48.83 121.5 47.73 122.88 47.73 122.88 46.79 121.5 46.79 121.5 45.69 122.88 45.69 122.88 44.75 121.5 44.75 121.5 43.65 122.88 43.65 122.88 43.39 121.5 43.39 121.5 42.29 122.88 42.29 122.88 41.35 121.5 41.35 121.5 40.25 122.88 40.25 122.88 39.31 121.5 39.31 121.5 38.21 122.88 38.21 122.88 37.95 121.5 37.95 121.5 36.85 122.88 36.85 122.88 36.59 121.5 36.59 121.5 35.49 122.88 35.49 122.88 35.23 121.5 35.23 121.5 34.13 122.88 34.13 122.88 33.87 121.5 33.87 121.5 32.77 122.88 32.77 122.88 32.51 121.5 32.51 121.5 31.41 122.88 31.41 122.88 31.15 121.5 31.15 121.5 30.05 122.88 30.05 122.88 29.79 121.5 29.79 121.5 28.69 122.88 28.69 122.88 28.43 121.5 28.43 121.5 27.33 122.88 27.33 122.88 27.07 121.5 27.07 121.5 25.97 122.88 25.97 122.88 25.03 121.5 25.03 121.5 23.93 122.88 23.93 122.88 23.67 121.5 23.67 121.5 22.57 122.88 22.57 122.88 22.31 121.5 22.31 121.5 21.21 122.88 21.21 122.88 20.27 121.5 20.27 121.5 19.17 122.88 19.17 122.88 18.23 121.5 18.23 121.5 17.13 122.88 17.13 122.88 14.83 121.5 14.83 121.5 13.73 122.88 13.73 122.88 11.28 95.28 11.28 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; LAYER met4 ; - POLYGON 102.64 81.2 102.64 16.72 98.07 16.72 98.07 18.08 96.97 18.08 96.97 16.72 84.24 16.72 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 122.88 97.52 122.88 11.28 113.86 11.28 113.86 11.88 112.46 11.88 112.46 11.28 95.28 11.28 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 112.46 97.52 112.46 96.92 113.86 96.92 113.86 97.52 ; LAYER met5 ; - POLYGON 101.44 80 101.44 72.56 98.24 72.56 98.24 66.16 101.44 66.16 101.44 52.16 98.24 52.16 98.24 45.76 101.44 45.76 101.44 31.76 98.24 31.76 98.24 25.36 101.44 25.36 101.44 17.92 83.04 17.92 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; + POLYGON 121.68 96.32 121.68 88.2 118.48 88.2 118.48 81.8 121.68 81.8 121.68 67.8 118.48 67.8 118.48 61.4 121.68 61.4 121.68 47.4 118.48 47.4 118.48 41 121.68 41 121.68 27 118.48 27 118.48 20.6 121.68 20.6 121.68 12.48 94.08 12.48 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; - POLYGON 102.76 81.08 102.76 79.4 102.28 79.4 102.28 78.36 102.76 78.36 102.76 76.68 102.28 76.68 102.28 75.64 102.76 75.64 102.76 73.96 102.28 73.96 102.28 72.92 102.76 72.92 102.76 71.24 102.28 71.24 102.28 70.2 102.76 70.2 102.76 68.52 102.28 68.52 102.28 67.48 102.76 67.48 102.76 65.8 102.28 65.8 102.28 64.76 102.76 64.76 102.76 63.08 102.28 63.08 102.28 62.04 102.76 62.04 102.76 60.36 102.28 60.36 102.28 59.32 102.76 59.32 102.76 57.64 102.28 57.64 102.28 56.6 102.76 56.6 102.76 54.92 102.28 54.92 102.28 53.88 102.76 53.88 102.76 52.2 102.28 52.2 102.28 51.16 102.76 51.16 102.76 49.48 102.28 49.48 102.28 48.44 102.76 48.44 102.76 46.76 102.28 46.76 102.28 45.72 102.76 45.72 102.76 44.04 102.28 44.04 102.28 43 102.76 43 102.76 41.32 102.28 41.32 102.28 40.28 102.76 40.28 102.76 38.6 102.28 38.6 102.28 37.56 102.76 37.56 102.76 35.88 102.28 35.88 102.28 34.84 102.76 34.84 102.76 33.16 102.28 33.16 102.28 32.12 102.76 32.12 102.76 30.44 102.28 30.44 102.28 29.4 102.76 29.4 102.76 27.72 102.28 27.72 102.28 26.68 102.76 26.68 102.76 25 102.28 25 102.28 23.96 102.76 23.96 102.76 22.28 102.28 22.28 102.28 21.24 102.76 21.24 102.76 19.56 102.28 19.56 102.28 18.52 102.76 18.52 102.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; + POLYGON 123 97.4 123 95.72 122.52 95.72 122.52 94.68 123 94.68 123 93 122.52 93 122.52 91.96 123 91.96 123 90.28 122.52 90.28 122.52 89.24 123 89.24 123 87.56 122.52 87.56 122.52 86.52 123 86.52 123 84.84 122.52 84.84 122.52 83.8 123 83.8 123 82.12 122.52 82.12 122.52 81.08 123 81.08 123 79.4 122.52 79.4 122.52 78.36 123 78.36 123 76.68 122.52 76.68 122.52 75.64 123 75.64 123 73.96 122.52 73.96 122.52 72.92 123 72.92 123 71.24 122.52 71.24 122.52 70.2 123 70.2 123 68.52 122.52 68.52 122.52 67.48 123 67.48 123 65.8 122.52 65.8 122.52 64.76 123 64.76 123 63.08 122.52 63.08 122.52 62.04 123 62.04 123 60.36 122.52 60.36 122.52 59.32 123 59.32 123 57.64 122.52 57.64 122.52 56.6 123 56.6 123 54.92 122.52 54.92 122.52 53.88 123 53.88 123 52.2 122.52 52.2 122.52 51.16 123 51.16 123 49.48 122.52 49.48 122.52 48.44 123 48.44 123 46.76 122.52 46.76 122.52 45.72 123 45.72 123 44.04 122.52 44.04 122.52 43 123 43 123 41.32 122.52 41.32 122.52 40.28 123 40.28 123 38.6 122.52 38.6 122.52 37.56 123 37.56 123 35.88 122.52 35.88 122.52 34.84 123 34.84 123 33.16 122.52 33.16 122.52 32.12 123 32.12 123 30.44 122.52 30.44 122.52 29.4 123 29.4 123 27.72 122.52 27.72 122.52 26.68 123 26.68 123 25 122.52 25 122.52 23.96 123 23.96 123 22.28 122.52 22.28 122.52 21.24 123 21.24 123 19.56 122.52 19.56 122.52 18.52 123 18.52 123 16.84 122.52 16.84 122.52 15.8 123 15.8 123 14.12 122.52 14.12 122.52 13.08 123 13.08 123 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; LAYER li1 ; - POLYGON 102.87 81.43 102.87 16.49 84.47 16.49 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 ; + POLYGON 123.11 97.75 123.11 11.05 95.51 11.05 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 102.725 81.515 102.895 81.685 ; - RECT 102.265 81.515 102.435 81.685 ; - RECT 101.805 81.515 101.975 81.685 ; - RECT 101.345 81.515 101.515 81.685 ; - RECT 100.885 81.515 101.055 81.685 ; - RECT 100.425 81.515 100.595 81.685 ; - RECT 99.965 81.515 100.135 81.685 ; - RECT 99.505 81.515 99.675 81.685 ; - RECT 99.045 81.515 99.215 81.685 ; - RECT 98.585 81.515 98.755 81.685 ; - RECT 98.125 81.515 98.295 81.685 ; - RECT 97.665 81.515 97.835 81.685 ; - RECT 97.205 81.515 97.375 81.685 ; - RECT 96.745 81.515 96.915 81.685 ; - RECT 96.285 81.515 96.455 81.685 ; - RECT 95.825 81.515 95.995 81.685 ; - RECT 95.365 81.515 95.535 81.685 ; - RECT 94.905 81.515 95.075 81.685 ; - RECT 94.445 81.515 94.615 81.685 ; - RECT 93.985 81.515 94.155 81.685 ; - RECT 93.525 81.515 93.695 81.685 ; - RECT 93.065 81.515 93.235 81.685 ; - RECT 92.605 81.515 92.775 81.685 ; - RECT 92.145 81.515 92.315 81.685 ; - RECT 91.685 81.515 91.855 81.685 ; - RECT 91.225 81.515 91.395 81.685 ; - RECT 90.765 81.515 90.935 81.685 ; - RECT 90.305 81.515 90.475 81.685 ; - RECT 89.845 81.515 90.015 81.685 ; - RECT 89.385 81.515 89.555 81.685 ; - RECT 88.925 81.515 89.095 81.685 ; - RECT 88.465 81.515 88.635 81.685 ; - RECT 88.005 81.515 88.175 81.685 ; - RECT 87.545 81.515 87.715 81.685 ; - RECT 87.085 81.515 87.255 81.685 ; - RECT 86.625 81.515 86.795 81.685 ; - RECT 86.165 81.515 86.335 81.685 ; - RECT 85.705 81.515 85.875 81.685 ; - RECT 85.245 81.515 85.415 81.685 ; - RECT 84.785 81.515 84.955 81.685 ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 122.965 97.835 123.135 98.005 ; + RECT 122.505 97.835 122.675 98.005 ; + RECT 122.045 97.835 122.215 98.005 ; + RECT 121.585 97.835 121.755 98.005 ; + RECT 121.125 97.835 121.295 98.005 ; + RECT 120.665 97.835 120.835 98.005 ; + RECT 120.205 97.835 120.375 98.005 ; + RECT 119.745 97.835 119.915 98.005 ; + RECT 119.285 97.835 119.455 98.005 ; + RECT 118.825 97.835 118.995 98.005 ; + RECT 118.365 97.835 118.535 98.005 ; + RECT 117.905 97.835 118.075 98.005 ; + RECT 117.445 97.835 117.615 98.005 ; + RECT 116.985 97.835 117.155 98.005 ; + RECT 116.525 97.835 116.695 98.005 ; + RECT 116.065 97.835 116.235 98.005 ; + RECT 115.605 97.835 115.775 98.005 ; + RECT 115.145 97.835 115.315 98.005 ; + RECT 114.685 97.835 114.855 98.005 ; + RECT 114.225 97.835 114.395 98.005 ; + RECT 113.765 97.835 113.935 98.005 ; + RECT 113.305 97.835 113.475 98.005 ; + RECT 112.845 97.835 113.015 98.005 ; + RECT 112.385 97.835 112.555 98.005 ; + RECT 111.925 97.835 112.095 98.005 ; + RECT 111.465 97.835 111.635 98.005 ; + RECT 111.005 97.835 111.175 98.005 ; + RECT 110.545 97.835 110.715 98.005 ; + RECT 110.085 97.835 110.255 98.005 ; + RECT 109.625 97.835 109.795 98.005 ; + RECT 109.165 97.835 109.335 98.005 ; + RECT 108.705 97.835 108.875 98.005 ; + RECT 108.245 97.835 108.415 98.005 ; + RECT 107.785 97.835 107.955 98.005 ; + RECT 107.325 97.835 107.495 98.005 ; + RECT 106.865 97.835 107.035 98.005 ; + RECT 106.405 97.835 106.575 98.005 ; + RECT 105.945 97.835 106.115 98.005 ; + RECT 105.485 97.835 105.655 98.005 ; + RECT 105.025 97.835 105.195 98.005 ; + RECT 104.565 97.835 104.735 98.005 ; + RECT 104.105 97.835 104.275 98.005 ; + RECT 103.645 97.835 103.815 98.005 ; + RECT 103.185 97.835 103.355 98.005 ; + RECT 102.725 97.835 102.895 98.005 ; + RECT 102.265 97.835 102.435 98.005 ; + RECT 101.805 97.835 101.975 98.005 ; + RECT 101.345 97.835 101.515 98.005 ; + RECT 100.885 97.835 101.055 98.005 ; + RECT 100.425 97.835 100.595 98.005 ; + RECT 99.965 97.835 100.135 98.005 ; + RECT 99.505 97.835 99.675 98.005 ; + RECT 99.045 97.835 99.215 98.005 ; + RECT 98.585 97.835 98.755 98.005 ; + RECT 98.125 97.835 98.295 98.005 ; + RECT 97.665 97.835 97.835 98.005 ; + RECT 97.205 97.835 97.375 98.005 ; + RECT 96.745 97.835 96.915 98.005 ; + RECT 96.285 97.835 96.455 98.005 ; + RECT 95.825 97.835 95.995 98.005 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 25.445 97.835 25.615 98.005 ; + RECT 24.985 97.835 25.155 98.005 ; + RECT 24.525 97.835 24.695 98.005 ; + RECT 24.065 97.835 24.235 98.005 ; + RECT 23.605 97.835 23.775 98.005 ; + RECT 23.145 97.835 23.315 98.005 ; + RECT 22.685 97.835 22.855 98.005 ; + RECT 22.225 97.835 22.395 98.005 ; + RECT 21.765 97.835 21.935 98.005 ; + RECT 21.305 97.835 21.475 98.005 ; + RECT 20.845 97.835 21.015 98.005 ; + RECT 20.385 97.835 20.555 98.005 ; + RECT 19.925 97.835 20.095 98.005 ; + RECT 19.465 97.835 19.635 98.005 ; + RECT 19.005 97.835 19.175 98.005 ; + RECT 18.545 97.835 18.715 98.005 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 122.965 95.115 123.135 95.285 ; + RECT 122.505 95.115 122.675 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 122.965 92.395 123.135 92.565 ; + RECT 122.505 92.395 122.675 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 122.965 89.675 123.135 89.845 ; + RECT 122.505 89.675 122.675 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 122.965 86.955 123.135 87.125 ; + RECT 122.505 86.955 122.675 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 122.965 84.235 123.135 84.405 ; + RECT 122.505 84.235 122.675 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 122.965 81.515 123.135 81.685 ; + RECT 122.505 81.515 122.675 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 102.725 78.795 102.895 78.965 ; - RECT 102.265 78.795 102.435 78.965 ; + RECT 122.965 78.795 123.135 78.965 ; + RECT 122.505 78.795 122.675 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 102.725 76.075 102.895 76.245 ; - RECT 102.265 76.075 102.435 76.245 ; + RECT 122.965 76.075 123.135 76.245 ; + RECT 122.505 76.075 122.675 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 102.725 73.355 102.895 73.525 ; - RECT 102.265 73.355 102.435 73.525 ; + RECT 122.965 73.355 123.135 73.525 ; + RECT 122.505 73.355 122.675 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 102.725 70.635 102.895 70.805 ; - RECT 102.265 70.635 102.435 70.805 ; + RECT 122.965 70.635 123.135 70.805 ; + RECT 122.505 70.635 122.675 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 102.725 67.915 102.895 68.085 ; - RECT 102.265 67.915 102.435 68.085 ; + RECT 122.965 67.915 123.135 68.085 ; + RECT 122.505 67.915 122.675 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 102.725 65.195 102.895 65.365 ; - RECT 102.265 65.195 102.435 65.365 ; + RECT 122.965 65.195 123.135 65.365 ; + RECT 122.505 65.195 122.675 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 102.725 62.475 102.895 62.645 ; - RECT 102.265 62.475 102.435 62.645 ; + RECT 122.965 62.475 123.135 62.645 ; + RECT 122.505 62.475 122.675 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 102.725 59.755 102.895 59.925 ; - RECT 102.265 59.755 102.435 59.925 ; + RECT 122.965 59.755 123.135 59.925 ; + RECT 122.505 59.755 122.675 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 102.725 57.035 102.895 57.205 ; - RECT 102.265 57.035 102.435 57.205 ; + RECT 122.965 57.035 123.135 57.205 ; + RECT 122.505 57.035 122.675 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 102.725 54.315 102.895 54.485 ; - RECT 102.265 54.315 102.435 54.485 ; + RECT 122.965 54.315 123.135 54.485 ; + RECT 122.505 54.315 122.675 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 102.725 51.595 102.895 51.765 ; - RECT 102.265 51.595 102.435 51.765 ; + RECT 122.965 51.595 123.135 51.765 ; + RECT 122.505 51.595 122.675 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 102.725 48.875 102.895 49.045 ; - RECT 102.265 48.875 102.435 49.045 ; + RECT 122.965 48.875 123.135 49.045 ; + RECT 122.505 48.875 122.675 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 102.725 46.155 102.895 46.325 ; - RECT 102.265 46.155 102.435 46.325 ; + RECT 122.965 46.155 123.135 46.325 ; + RECT 122.505 46.155 122.675 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 102.725 43.435 102.895 43.605 ; - RECT 102.265 43.435 102.435 43.605 ; + RECT 122.965 43.435 123.135 43.605 ; + RECT 122.505 43.435 122.675 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 102.725 40.715 102.895 40.885 ; - RECT 102.265 40.715 102.435 40.885 ; + RECT 122.965 40.715 123.135 40.885 ; + RECT 122.505 40.715 122.675 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 102.725 37.995 102.895 38.165 ; - RECT 102.265 37.995 102.435 38.165 ; + RECT 122.965 37.995 123.135 38.165 ; + RECT 122.505 37.995 122.675 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 102.725 35.275 102.895 35.445 ; - RECT 102.265 35.275 102.435 35.445 ; + RECT 122.965 35.275 123.135 35.445 ; + RECT 122.505 35.275 122.675 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 102.725 32.555 102.895 32.725 ; - RECT 102.265 32.555 102.435 32.725 ; + RECT 122.965 32.555 123.135 32.725 ; + RECT 122.505 32.555 122.675 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 102.725 29.835 102.895 30.005 ; - RECT 102.265 29.835 102.435 30.005 ; + RECT 122.965 29.835 123.135 30.005 ; + RECT 122.505 29.835 122.675 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 102.725 27.115 102.895 27.285 ; - RECT 102.265 27.115 102.435 27.285 ; + RECT 122.965 27.115 123.135 27.285 ; + RECT 122.505 27.115 122.675 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 102.725 24.395 102.895 24.565 ; - RECT 102.265 24.395 102.435 24.565 ; + RECT 122.965 24.395 123.135 24.565 ; + RECT 122.505 24.395 122.675 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 102.725 21.675 102.895 21.845 ; - RECT 102.265 21.675 102.435 21.845 ; + RECT 122.965 21.675 123.135 21.845 ; + RECT 122.505 21.675 122.675 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 102.725 18.955 102.895 19.125 ; - RECT 102.265 18.955 102.435 19.125 ; + RECT 122.965 18.955 123.135 19.125 ; + RECT 122.505 18.955 122.675 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 102.725 16.235 102.895 16.405 ; - RECT 102.265 16.235 102.435 16.405 ; - RECT 101.805 16.235 101.975 16.405 ; - RECT 101.345 16.235 101.515 16.405 ; - RECT 100.885 16.235 101.055 16.405 ; - RECT 100.425 16.235 100.595 16.405 ; - RECT 99.965 16.235 100.135 16.405 ; - RECT 99.505 16.235 99.675 16.405 ; - RECT 99.045 16.235 99.215 16.405 ; - RECT 98.585 16.235 98.755 16.405 ; - RECT 98.125 16.235 98.295 16.405 ; - RECT 97.665 16.235 97.835 16.405 ; - RECT 97.205 16.235 97.375 16.405 ; - RECT 96.745 16.235 96.915 16.405 ; - RECT 96.285 16.235 96.455 16.405 ; - RECT 95.825 16.235 95.995 16.405 ; - RECT 95.365 16.235 95.535 16.405 ; - RECT 94.905 16.235 95.075 16.405 ; - RECT 94.445 16.235 94.615 16.405 ; - RECT 93.985 16.235 94.155 16.405 ; - RECT 93.525 16.235 93.695 16.405 ; - RECT 93.065 16.235 93.235 16.405 ; - RECT 92.605 16.235 92.775 16.405 ; - RECT 92.145 16.235 92.315 16.405 ; - RECT 91.685 16.235 91.855 16.405 ; - RECT 91.225 16.235 91.395 16.405 ; - RECT 90.765 16.235 90.935 16.405 ; - RECT 90.305 16.235 90.475 16.405 ; - RECT 89.845 16.235 90.015 16.405 ; - RECT 89.385 16.235 89.555 16.405 ; - RECT 88.925 16.235 89.095 16.405 ; - RECT 88.465 16.235 88.635 16.405 ; - RECT 88.005 16.235 88.175 16.405 ; - RECT 87.545 16.235 87.715 16.405 ; - RECT 87.085 16.235 87.255 16.405 ; - RECT 86.625 16.235 86.795 16.405 ; - RECT 86.165 16.235 86.335 16.405 ; - RECT 85.705 16.235 85.875 16.405 ; - RECT 85.245 16.235 85.415 16.405 ; - RECT 84.785 16.235 84.955 16.405 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 122.965 16.235 123.135 16.405 ; + RECT 122.505 16.235 122.675 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; - RECT 19.005 13.515 19.175 13.685 ; - RECT 18.545 13.515 18.715 13.685 ; + RECT 122.965 13.515 123.135 13.685 ; + RECT 122.505 13.515 122.675 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 122.965 10.795 123.135 10.965 ; + RECT 122.505 10.795 122.675 10.965 ; + RECT 122.045 10.795 122.215 10.965 ; + RECT 121.585 10.795 121.755 10.965 ; + RECT 121.125 10.795 121.295 10.965 ; + RECT 120.665 10.795 120.835 10.965 ; + RECT 120.205 10.795 120.375 10.965 ; + RECT 119.745 10.795 119.915 10.965 ; + RECT 119.285 10.795 119.455 10.965 ; + RECT 118.825 10.795 118.995 10.965 ; + RECT 118.365 10.795 118.535 10.965 ; + RECT 117.905 10.795 118.075 10.965 ; + RECT 117.445 10.795 117.615 10.965 ; + RECT 116.985 10.795 117.155 10.965 ; + RECT 116.525 10.795 116.695 10.965 ; + RECT 116.065 10.795 116.235 10.965 ; + RECT 115.605 10.795 115.775 10.965 ; + RECT 115.145 10.795 115.315 10.965 ; + RECT 114.685 10.795 114.855 10.965 ; + RECT 114.225 10.795 114.395 10.965 ; + RECT 113.765 10.795 113.935 10.965 ; + RECT 113.305 10.795 113.475 10.965 ; + RECT 112.845 10.795 113.015 10.965 ; + RECT 112.385 10.795 112.555 10.965 ; + RECT 111.925 10.795 112.095 10.965 ; + RECT 111.465 10.795 111.635 10.965 ; + RECT 111.005 10.795 111.175 10.965 ; + RECT 110.545 10.795 110.715 10.965 ; + RECT 110.085 10.795 110.255 10.965 ; + RECT 109.625 10.795 109.795 10.965 ; + RECT 109.165 10.795 109.335 10.965 ; + RECT 108.705 10.795 108.875 10.965 ; + RECT 108.245 10.795 108.415 10.965 ; + RECT 107.785 10.795 107.955 10.965 ; + RECT 107.325 10.795 107.495 10.965 ; + RECT 106.865 10.795 107.035 10.965 ; + RECT 106.405 10.795 106.575 10.965 ; + RECT 105.945 10.795 106.115 10.965 ; + RECT 105.485 10.795 105.655 10.965 ; + RECT 105.025 10.795 105.195 10.965 ; + RECT 104.565 10.795 104.735 10.965 ; + RECT 104.105 10.795 104.275 10.965 ; + RECT 103.645 10.795 103.815 10.965 ; + RECT 103.185 10.795 103.355 10.965 ; + RECT 102.725 10.795 102.895 10.965 ; + RECT 102.265 10.795 102.435 10.965 ; + RECT 101.805 10.795 101.975 10.965 ; + RECT 101.345 10.795 101.515 10.965 ; + RECT 100.885 10.795 101.055 10.965 ; + RECT 100.425 10.795 100.595 10.965 ; + RECT 99.965 10.795 100.135 10.965 ; + RECT 99.505 10.795 99.675 10.965 ; + RECT 99.045 10.795 99.215 10.965 ; + RECT 98.585 10.795 98.755 10.965 ; + RECT 98.125 10.795 98.295 10.965 ; + RECT 97.665 10.795 97.835 10.965 ; + RECT 97.205 10.795 97.375 10.965 ; + RECT 96.745 10.795 96.915 10.965 ; + RECT 96.285 10.795 96.455 10.965 ; + RECT 95.825 10.795 95.995 10.965 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; RECT 84.325 10.795 84.495 10.965 ; RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; RECT 19.005 10.795 19.175 10.965 ; RECT 18.545 10.795 18.715 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; - RECT 19.005 8.075 19.175 8.245 ; - RECT 18.545 8.075 18.715 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; - RECT 19.005 5.355 19.175 5.525 ; - RECT 18.545 5.355 18.715 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; - RECT 19.005 2.635 19.175 2.805 ; - RECT 18.545 2.635 18.715 2.805 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; + RECT 28.205 8.075 28.375 8.245 ; + RECT 27.745 8.075 27.915 8.245 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; + RECT 28.205 5.355 28.375 5.525 ; + RECT 27.745 5.355 27.915 5.525 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; + RECT 28.205 2.635 28.375 2.805 ; + RECT 27.745 2.635 27.915 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -2450,64 +2635,53 @@ MACRO sb_1__2_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; LAYER via ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 96.525 17.945 96.675 18.095 ; - RECT 10.505 17.945 10.655 18.095 ; - RECT 4.525 17.945 4.675 18.095 ; - RECT 73.525 16.245 73.675 16.395 ; - RECT 44.085 16.245 44.235 16.395 ; - RECT 48.685 1.625 48.835 1.775 ; - RECT 46.845 1.625 46.995 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 10.045 97.845 10.195 97.995 ; + RECT 115.845 12.505 115.995 12.655 ; + RECT 14.185 12.505 14.335 12.655 ; + RECT 83.645 10.805 83.795 10.955 ; + RECT 54.205 10.805 54.355 10.955 ; + RECT 10.045 10.805 10.195 10.955 ; + RECT 77.665 1.625 77.815 1.775 ; + RECT 58.805 1.625 58.955 1.775 ; + RECT 52.825 1.625 52.975 1.775 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; LAYER via2 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 1.28 77.42 1.48 77.62 ; - RECT 101.1 66.54 101.3 66.74 ; - RECT 1.28 57.7 1.48 57.9 ; - RECT 101.1 52.94 101.3 53.14 ; - RECT 1.74 46.14 1.94 46.34 ; - RECT 1.74 39.34 1.94 39.54 ; - RECT 101.56 31.86 101.76 32.06 ; - RECT 1.74 31.18 1.94 31.38 ; - RECT 1.74 25.74 1.94 25.94 ; - RECT 101.56 24.38 101.76 24.58 ; - RECT 1.74 24.38 1.94 24.58 ; - RECT 19.68 12.14 19.88 12.34 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.28 89.66 1.48 89.86 ; + RECT 121.8 74.02 122 74.22 ; + RECT 1.74 72.66 1.94 72.86 ; + RECT 121.8 61.1 122 61.3 ; + RECT 121.8 56.34 122 56.54 ; + RECT 1.28 54.3 1.48 54.5 ; + RECT 1.28 51.58 1.48 51.78 ; + RECT 1.74 48.86 1.94 49.06 ; + RECT 1.28 44.78 1.48 44.98 ; + RECT 121.8 42.74 122 42.94 ; + RECT 121.8 38.66 122 38.86 ; + RECT 1.74 37.3 1.94 37.5 ; + RECT 1.28 34.58 1.48 34.78 ; + RECT 121.8 29.14 122 29.34 ; + RECT 121.34 27.78 121.54 27.98 ; + RECT 1.28 20.3 1.48 20.5 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER via3 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 101.1 40.7 101.3 40.9 ; - RECT 20.14 6.7 20.34 6.9 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 121.34 81.5 121.54 81.7 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER OVERLAP ; - POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 103.04 81.6 103.04 16.32 84.64 16.32 84.64 0 ; + POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 123.28 97.92 123.28 10.88 95.68 10.88 95.68 0 ; END END sb_1__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef index 61898b7..76a983c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__0__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_2__0_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 81.6 ; + SIZE 95.68 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 2.23 63.92 2.37 65.28 ; + LAYER met3 ; + RECT 0 13.45 1.38 13.75 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,15 +371,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 80.24 56.65 81.6 ; + RECT 61.11 96.56 61.25 97.92 ; END END chany_top_in[0] PIN chany_top_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 33.05 80.24 33.19 81.6 ; + LAYER met4 ; + RECT 63.33 96.56 63.63 97.92 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 56.89 80.24 57.19 81.6 ; + RECT 61.49 96.56 61.79 97.92 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 80.24 32.27 81.6 ; + RECT 51.91 96.56 52.05 97.92 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 80.24 23.07 81.6 ; + RECT 57.43 96.56 57.57 97.92 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 80.24 49.29 81.6 ; + RECT 62.03 96.56 62.17 97.92 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 80.24 64.01 81.6 ; + RECT 68.01 96.56 68.15 97.92 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 80.24 57.57 81.6 ; + RECT 49.15 96.56 49.29 97.92 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 80.24 62.17 81.6 ; + RECT 66.17 96.56 66.31 97.92 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 80.24 46.15 81.6 ; + RECT 45.85 96.56 46.15 97.92 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met4 ; - RECT 48.61 80.24 48.91 81.6 ; + RECT 44.01 96.56 44.31 97.92 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 80.24 48.37 81.6 ; + RECT 78.13 96.56 78.27 97.92 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 80.24 52.97 81.6 ; + RECT 58.35 96.56 58.49 97.92 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 80.24 64.93 81.6 ; + RECT 59.27 96.56 59.41 97.92 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 80.24 61.25 81.6 ; + RECT 70.77 96.56 70.91 97.92 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 80.24 59.41 81.6 ; + RECT 64.33 96.56 64.47 97.92 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 80.24 50.21 81.6 ; + RECT 80.89 96.56 81.03 97.92 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 80.24 63.09 81.6 ; + RECT 79.97 96.56 80.11 97.92 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 80.24 58.49 81.6 ; + RECT 60.19 96.56 60.33 97.92 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,15 +523,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 80.24 60.33 81.6 ; + RECT 79.05 96.56 79.19 97.92 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 80.24 24.99 81.6 ; + LAYER met2 ; + RECT 17.87 85.68 18.01 87.04 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] @@ -539,15 +539,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 63.92 11.11 65.28 ; + RECT 12.81 85.68 12.95 87.04 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 80.24 23.15 81.6 ; + LAYER met2 ; + RECT 8.21 85.68 8.35 87.04 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,7 +555,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 63.92 13.41 65.28 ; + RECT 11.89 85.68 12.03 87.04 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] @@ -563,7 +563,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 80.24 20.77 81.6 ; + RECT 6.37 85.68 6.51 87.04 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 63.92 8.81 65.28 ; + RECT 10.97 85.68 11.11 87.04 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,15 +579,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 80.24 21.69 81.6 ; + RECT 7.29 85.68 7.43 87.04 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 26.53 80.24 26.83 81.6 ; + LAYER met2 ; + RECT 5.45 85.68 5.59 87.04 ; END END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] @@ -595,7 +595,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 80.24 23.99 81.6 ; + RECT 44.55 96.56 44.69 97.92 ; END END top_right_grid_pin_1_[0] PIN chanx_left_in[0] @@ -603,7 +603,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 3.93 1.38 4.23 ; + RECT 0 76.69 1.38 76.99 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -611,7 +611,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -619,7 +619,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 12.09 1.38 12.39 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 16.17 1.38 16.47 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 55.61 1.38 55.91 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 6.65 1.38 6.95 ; + RECT 0 29.77 1.38 30.07 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 9.37 1.38 9.67 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 10.05 1.38 10.35 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -683,15 +683,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[10] PIN chanx_left_in[11] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.53 63.92 4.67 65.28 ; + LAYER met3 ; + RECT 0 33.85 1.38 34.15 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -699,23 +699,23 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 5.29 1.38 5.59 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_in[12] PIN chanx_left_in[13] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 63.92 4.75 65.28 ; + LAYER met3 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_in[13] PIN chanx_left_in[14] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.61 63.92 3.75 65.28 ; + LAYER met3 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 32.49 1.38 32.79 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 31.13 1.38 31.43 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -755,7 +755,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_1_[0] @@ -763,7 +763,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; + RECT 0 54.25 1.38 54.55 ; END END left_bottom_grid_pin_1_[0] PIN left_bottom_grid_pin_3_[0] @@ -771,7 +771,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 51.53 1.38 51.83 ; END END left_bottom_grid_pin_3_[0] PIN left_bottom_grid_pin_5_[0] @@ -779,7 +779,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 40.65 1.38 40.95 ; END END left_bottom_grid_pin_5_[0] PIN left_bottom_grid_pin_7_[0] @@ -787,7 +787,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 67.85 1.38 68.15 ; END END left_bottom_grid_pin_7_[0] PIN left_bottom_grid_pin_9_[0] @@ -795,7 +795,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 42.01 1.38 42.31 ; END END left_bottom_grid_pin_9_[0] PIN left_bottom_grid_pin_11_[0] @@ -803,7 +803,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 48.13 1.38 48.43 ; END END left_bottom_grid_pin_11_[0] PIN ccff_head[0] @@ -811,7 +811,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 80.24 39.17 81.6 ; + RECT 35.35 96.56 35.49 97.92 ; END END ccff_head[0] PIN chany_top_out[0] @@ -819,7 +819,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 80.24 41.01 81.6 ; + RECT 53.29 96.56 53.43 97.92 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -827,7 +827,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 80.24 34.11 81.6 ; + RECT 50.99 96.56 51.13 97.92 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -835,7 +835,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 80.24 46.53 81.6 ; + RECT 55.13 96.56 55.27 97.92 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -843,7 +843,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 80.24 52.05 81.6 ; + RECT 39.03 96.56 39.17 97.92 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -851,7 +851,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + RECT 41.79 96.56 41.93 97.92 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -859,7 +859,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 80.24 25.83 81.6 ; + RECT 39.95 96.56 40.09 97.92 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -867,7 +867,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 80.24 35.49 81.6 ; + RECT 77.21 96.56 77.35 97.92 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -875,7 +875,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 80.24 47.45 81.6 ; + RECT 38.11 96.56 38.25 97.92 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -883,7 +883,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 80.24 37.79 81.6 ; + RECT 65.25 96.56 65.39 97.92 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -891,7 +891,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 80.24 51.13 81.6 ; + RECT 63.41 96.56 63.55 97.92 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -899,7 +899,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 80.24 36.87 81.6 ; + RECT 48.23 96.56 48.37 97.92 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -907,7 +907,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 80.24 53.89 81.6 ; + RECT 37.19 96.56 37.33 97.92 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -915,7 +915,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 80.24 29.51 81.6 ; + RECT 50.07 96.56 50.21 97.92 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -923,7 +923,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 80.24 40.09 81.6 ; + RECT 47.31 96.56 47.45 97.92 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -931,7 +931,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 80.24 26.75 81.6 ; + RECT 67.09 96.56 67.23 97.92 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -939,7 +939,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 80.24 45.61 81.6 ; + RECT 42.71 96.56 42.85 97.92 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -947,7 +947,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 80.24 24.91 81.6 ; + RECT 43.63 96.56 43.77 97.92 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -955,7 +955,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 80.24 28.59 81.6 ; + RECT 40.87 96.56 41.01 97.92 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -963,7 +963,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + RECT 46.39 96.56 46.53 97.92 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -971,7 +971,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 80.24 27.67 81.6 ; + RECT 45.47 96.56 45.61 97.92 ; END END chany_top_out[19] PIN chanx_left_out[0] @@ -979,7 +979,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -995,15 +995,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[2] PIN chanx_left_out[3] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 5.45 63.92 5.59 65.28 ; + LAYER met3 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1011,7 +1011,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1026,8 +1026,8 @@ MACRO sb_2__0_ DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 3.15 0 3.29 1.36 ; + LAYER met3 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1035,7 +1035,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 8.69 1.38 8.99 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1043,15 +1043,15 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 35.21 1.38 35.51 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 0 2.37 1.36 ; + LAYER met3 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1059,7 +1059,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 18.89 1.38 19.19 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1067,7 +1067,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1075,7 +1075,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1083,7 +1083,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 8.01 1.38 8.31 ; + RECT 0 16.17 1.38 16.47 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1091,7 +1091,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 28.41 1.38 28.71 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1099,7 +1099,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 17.53 1.38 17.83 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1107,7 +1107,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1115,7 +1115,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 14.81 1.38 15.11 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1123,7 +1123,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 66.49 1.38 66.79 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1131,7 +1131,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 10.73 1.38 11.03 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1139,7 +1139,7 @@ MACRO sb_2__0_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 13.45 1.38 13.75 ; + RECT 0 11.41 1.38 11.71 ; END END ccff_tail[0] PIN VDD @@ -1148,45 +1148,51 @@ MACRO sb_2__0_ PORT LAYER met1 ; RECT 0 2.48 0.48 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; RECT 0 7.92 0.48 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; RECT 0 13.36 0.48 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; - RECT 18.4 67.76 18.88 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; - RECT 18.4 73.2 18.88 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; - RECT 18.4 78.64 18.88 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; + RECT 95.2 62.32 95.68 62.8 ; + RECT 0 67.76 0.48 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; + RECT 0 73.2 0.48 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; + RECT 0 78.64 0.48 79.12 ; + RECT 95.2 78.64 95.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; + RECT 27.6 89.52 28.08 90 ; + RECT 95.2 89.52 95.68 90 ; + RECT 27.6 94.96 28.08 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 81 29.74 81.6 ; - RECT 58.58 81 59.18 81.6 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 39.26 97.32 39.86 97.92 ; + RECT 68.7 97.32 69.3 97.92 ; LAYER met5 ; - RECT 0 10.64 3.2 13.84 ; - RECT 81.44 10.64 84.64 13.84 ; - RECT 0 51.44 3.2 54.64 ; - RECT 81.44 51.44 84.64 54.64 ; + RECT 0 11.32 3.2 14.52 ; + RECT 92.48 11.32 95.68 14.52 ; + RECT 0 52.12 3.2 55.32 ; + RECT 92.48 52.12 95.68 55.32 ; END END VDD PIN VSS @@ -1194,570 +1200,679 @@ MACRO sb_2__0_ USE GROUND ; PORT LAYER met1 ; - RECT 0 0 84.64 0.24 ; + RECT 0 0 95.68 0.24 ; RECT 0 5.2 0.48 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; RECT 0 10.64 0.48 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; + RECT 95.2 10.64 95.68 11.12 ; RECT 0 16.08 0.48 16.56 ; - RECT 84.16 16.08 84.64 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; - RECT 0 65.04 84.64 65.52 ; - RECT 18.4 70.48 18.88 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; - RECT 18.4 75.92 18.88 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 18.4 81.36 84.64 81.6 ; + RECT 95.2 59.6 95.68 60.08 ; + RECT 0 65.04 0.48 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; + RECT 0 70.48 0.48 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; + RECT 0 75.92 0.48 76.4 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; + RECT 0 86.8 95.68 87.28 ; + RECT 27.6 92.24 28.08 92.72 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 27.6 97.68 95.68 97.92 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 81 44.46 81.6 ; - RECT 73.3 81 73.9 81.6 ; + RECT 9.82 0 10.42 0.6 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 86.44 10.42 87.04 ; + RECT 53.98 97.32 54.58 97.92 ; + RECT 83.42 97.32 84.02 97.92 ; LAYER met5 ; - RECT 0 31.04 3.2 34.24 ; - RECT 81.44 31.04 84.64 34.24 ; + RECT 0 31.72 3.2 34.92 ; + RECT 92.48 31.72 95.68 34.92 ; + RECT 0 72.52 3.2 75.72 ; + RECT 92.48 72.52 95.68 75.72 ; END END VSS OBS LAYER li1 ; - RECT 18.4 81.515 84.64 81.685 ; - RECT 80.96 78.795 84.64 78.965 ; - RECT 18.4 78.795 22.08 78.965 ; - RECT 80.96 76.075 84.64 76.245 ; - RECT 18.4 76.075 22.08 76.245 ; - RECT 80.96 73.355 84.64 73.525 ; - RECT 18.4 73.355 22.08 73.525 ; - RECT 80.96 70.635 84.64 70.805 ; - RECT 18.4 70.635 20.24 70.805 ; - RECT 80.96 67.915 84.64 68.085 ; - RECT 18.4 67.915 22.08 68.085 ; - RECT 80.96 65.195 84.64 65.365 ; - RECT 0 65.195 22.08 65.365 ; - RECT 84.18 62.475 84.64 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 84.18 59.755 84.64 59.925 ; - RECT 0 59.755 3.68 59.925 ; - RECT 80.96 57.035 84.64 57.205 ; - RECT 0 57.035 3.68 57.205 ; - RECT 80.96 54.315 84.64 54.485 ; + RECT 27.6 97.835 95.68 98.005 ; + RECT 92 95.115 95.68 95.285 ; + RECT 27.6 95.115 31.28 95.285 ; + RECT 92 92.395 95.68 92.565 ; + RECT 27.6 92.395 31.28 92.565 ; + RECT 95.22 89.675 95.68 89.845 ; + RECT 27.6 89.675 31.28 89.845 ; + RECT 95.22 86.955 95.68 87.125 ; + RECT 0 86.955 29.44 87.125 ; + RECT 95.22 84.235 95.68 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 94.76 81.515 95.68 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 94.76 78.795 95.68 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 94.76 76.075 95.68 76.245 ; + RECT 0 76.075 1.84 76.245 ; + RECT 94.76 73.355 95.68 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 95.22 70.635 95.68 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 94.76 67.915 95.68 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 94.76 65.195 95.68 65.365 ; + RECT 0 65.195 1.84 65.365 ; + RECT 95.22 62.475 95.68 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 92 59.755 95.68 59.925 ; + RECT 0 59.755 1.84 59.925 ; + RECT 92 57.035 95.68 57.205 ; + RECT 0 57.035 1.84 57.205 ; + RECT 93.84 54.315 95.68 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 80.96 51.595 84.64 51.765 ; + RECT 95.22 51.595 95.68 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 80.96 48.875 84.64 49.045 ; - RECT 0 48.875 3.68 49.045 ; - RECT 80.96 46.155 84.64 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 83.72 43.435 84.64 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 84.18 40.715 84.64 40.885 ; + RECT 95.22 48.875 95.68 49.045 ; + RECT 0 48.875 1.84 49.045 ; + RECT 92 46.155 95.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 92 43.435 95.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 93.84 40.715 95.68 40.885 ; RECT 0 40.715 1.84 40.885 ; - RECT 84.18 37.995 84.64 38.165 ; + RECT 93.84 37.995 95.68 38.165 ; RECT 0 37.995 1.84 38.165 ; - RECT 84.18 35.275 84.64 35.445 ; + RECT 95.22 35.275 95.68 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; + RECT 95.22 32.555 95.68 32.725 ; RECT 0 32.555 1.84 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 95.22 29.835 95.68 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 83.72 27.115 84.64 27.285 ; + RECT 95.22 27.115 95.68 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 80.96 24.395 84.64 24.565 ; + RECT 95.22 24.395 95.68 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 80.96 21.675 84.64 21.845 ; + RECT 95.22 21.675 95.68 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 82.8 18.955 84.64 19.125 ; + RECT 95.22 18.955 95.68 19.125 ; RECT 0 18.955 1.84 19.125 ; - RECT 80.96 16.235 84.64 16.405 ; + RECT 95.22 16.235 95.68 16.405 ; RECT 0 16.235 1.84 16.405 ; - RECT 80.96 13.515 84.64 13.685 ; + RECT 95.22 13.515 95.68 13.685 ; RECT 0 13.515 1.84 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; + RECT 95.22 10.795 95.68 10.965 ; RECT 0 10.795 1.84 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; - RECT 0 8.075 1.84 8.245 ; - RECT 83.72 5.355 84.64 5.525 ; + RECT 95.22 8.075 95.68 8.245 ; + RECT 0 8.075 3.68 8.245 ; + RECT 95.22 5.355 95.68 5.525 ; RECT 0 5.355 3.68 5.525 ; - RECT 84.18 2.635 84.64 2.805 ; + RECT 95.22 2.635 95.68 2.805 ; RECT 0 2.635 3.68 2.805 ; - RECT 0 -0.085 84.64 0.085 ; - LAYER met2 ; - RECT 73.46 81.415 73.74 81.785 ; - RECT 44.02 81.415 44.3 81.785 ; - RECT 34.37 79.74 34.63 80.06 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 0.28 3.57 0.28 3.57 1.64 2.87 1.64 2.87 0.28 2.65 0.28 2.65 1.64 1.95 1.64 1.95 0.28 0.28 0.28 0.28 65 1.95 65 1.95 63.64 2.65 63.64 2.65 65 3.33 65 3.33 63.64 4.03 63.64 4.03 65 4.25 65 4.25 63.64 4.95 63.64 4.95 65 5.17 65 5.17 63.64 5.87 63.64 5.87 65 8.39 65 8.39 63.64 9.09 63.64 9.09 65 10.69 65 10.69 63.64 11.39 63.64 11.39 65 12.99 65 12.99 63.64 13.69 63.64 13.69 65 18.68 65 18.68 81.32 20.35 81.32 20.35 79.96 21.05 79.96 21.05 81.32 21.27 81.32 21.27 79.96 21.97 79.96 21.97 81.32 22.65 81.32 22.65 79.96 23.35 79.96 23.35 81.32 23.57 81.32 23.57 79.96 24.27 79.96 24.27 81.32 24.49 81.32 24.49 79.96 25.19 79.96 25.19 81.32 25.41 81.32 25.41 79.96 26.11 79.96 26.11 81.32 26.33 81.32 26.33 79.96 27.03 79.96 27.03 81.32 27.25 81.32 27.25 79.96 27.95 79.96 27.95 81.32 28.17 81.32 28.17 79.96 28.87 79.96 28.87 81.32 29.09 81.32 29.09 79.96 29.79 79.96 29.79 81.32 31.85 81.32 31.85 79.96 32.55 79.96 32.55 81.32 32.77 81.32 32.77 79.96 33.47 79.96 33.47 81.32 33.69 81.32 33.69 79.96 34.39 79.96 34.39 81.32 35.07 81.32 35.07 79.96 35.77 79.96 35.77 81.32 36.45 81.32 36.45 79.96 37.15 79.96 37.15 81.32 37.37 81.32 37.37 79.96 38.07 79.96 38.07 81.32 38.75 81.32 38.75 79.96 39.45 79.96 39.45 81.32 39.67 81.32 39.67 79.96 40.37 79.96 40.37 81.32 40.59 81.32 40.59 79.96 41.29 79.96 41.29 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 45.19 81.32 45.19 79.96 45.89 79.96 45.89 81.32 46.11 81.32 46.11 79.96 46.81 79.96 46.81 81.32 47.03 81.32 47.03 79.96 47.73 79.96 47.73 81.32 47.95 81.32 47.95 79.96 48.65 79.96 48.65 81.32 48.87 81.32 48.87 79.96 49.57 79.96 49.57 81.32 49.79 81.32 49.79 79.96 50.49 79.96 50.49 81.32 50.71 81.32 50.71 79.96 51.41 79.96 51.41 81.32 51.63 81.32 51.63 79.96 52.33 79.96 52.33 81.32 52.55 81.32 52.55 79.96 53.25 79.96 53.25 81.32 53.47 81.32 53.47 79.96 54.17 79.96 54.17 81.32 56.23 81.32 56.23 79.96 56.93 79.96 56.93 81.32 57.15 81.32 57.15 79.96 57.85 79.96 57.85 81.32 58.07 81.32 58.07 79.96 58.77 79.96 58.77 81.32 58.99 81.32 58.99 79.96 59.69 79.96 59.69 81.32 59.91 81.32 59.91 79.96 60.61 79.96 60.61 81.32 60.83 81.32 60.83 79.96 61.53 79.96 61.53 81.32 61.75 81.32 61.75 79.96 62.45 79.96 62.45 81.32 62.67 81.32 62.67 79.96 63.37 79.96 63.37 81.32 63.59 81.32 63.59 79.96 64.29 79.96 64.29 81.32 64.51 81.32 64.51 79.96 65.21 79.96 65.21 81.32 ; - LAYER met4 ; - POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 0.4 0.4 0.4 64.88 4.05 64.88 4.05 63.52 5.15 63.52 5.15 64.88 18.8 64.88 18.8 81.2 22.45 81.2 22.45 79.84 23.55 79.84 23.55 81.2 24.29 81.2 24.29 79.84 25.39 79.84 25.39 81.2 26.13 81.2 26.13 79.84 27.23 79.84 27.23 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 45.45 81.2 45.45 79.84 46.55 79.84 46.55 81.2 48.21 81.2 48.21 79.84 49.31 79.84 49.31 81.2 56.49 81.2 56.49 79.84 57.59 79.84 57.59 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + RECT 0 -0.085 95.68 0.085 ; LAYER met3 ; - POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; - POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 0.4 0.4 0.4 0.4 3.53 1.78 3.53 1.78 4.63 0.4 4.63 0.4 4.89 1.78 4.89 1.78 5.99 0.4 5.99 0.4 6.25 1.78 6.25 1.78 7.35 0.4 7.35 0.4 7.61 1.78 7.61 1.78 8.71 0.4 8.71 0.4 8.97 1.78 8.97 1.78 10.07 0.4 10.07 0.4 10.33 1.78 10.33 1.78 11.43 0.4 11.43 0.4 11.69 1.78 11.69 1.78 12.79 0.4 12.79 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 14.41 1.78 14.41 1.78 15.51 0.4 15.51 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 64.88 18.8 64.88 18.8 81.2 ; + POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; + POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; + POLYGON 10.285 87.205 10.285 87.2 10.5 87.2 10.5 86.88 10.285 86.88 10.285 86.875 9.955 86.875 9.955 86.88 9.74 86.88 9.74 87.2 9.955 87.2 9.955 87.205 ; + POLYGON 11.65 66.11 11.65 65.81 1.99 65.81 1.99 65.13 1.78 65.13 1.78 65.83 1.69 65.83 1.69 66.11 ; + POLYGON 7.51 59.31 7.51 59.01 1.78 59.01 1.78 59.03 1.23 59.03 1.23 59.31 ; + POLYGON 1.99 45.03 1.99 44.35 6.59 44.35 6.59 44.05 1.69 44.05 1.69 44.33 1.78 44.33 1.78 45.03 ; + POLYGON 1.99 39.59 1.99 38.91 21.77 38.91 21.77 38.61 1.69 38.61 1.69 38.89 1.78 38.89 1.78 39.59 ; + POLYGON 2.005 28.045 2.005 28.03 15.79 28.03 15.79 27.73 2.005 27.73 2.005 27.715 1.675 27.715 1.675 28.045 ; + POLYGON 6.59 25.99 6.59 25.69 1.99 25.69 1.99 25.01 1.78 25.01 1.78 25.71 1.69 25.71 1.69 25.99 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 10.285 0.165 10.285 0.16 10.5 0.16 10.5 -0.16 10.285 -0.16 10.285 -0.165 9.955 -0.165 9.955 -0.16 9.74 -0.16 9.74 0.16 9.955 0.16 9.955 0.165 ; + POLYGON 95.28 97.52 95.28 0.4 0.4 0.4 0.4 8.29 1.78 8.29 1.78 9.39 0.4 9.39 0.4 9.65 1.78 9.65 1.78 10.75 0.4 10.75 0.4 11.01 1.78 11.01 1.78 12.11 0.4 12.11 0.4 13.05 1.78 13.05 1.78 14.15 0.4 14.15 0.4 15.77 1.78 15.77 1.78 16.87 0.4 16.87 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.73 1.78 47.73 1.78 48.83 0.4 48.83 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 86.64 28 86.64 28 97.52 ; + LAYER met2 ; + RECT 83.58 97.735 83.86 98.105 ; + RECT 54.14 97.735 54.42 98.105 ; + RECT 68.41 96.06 68.67 96.38 ; + RECT 49.55 96.06 49.81 96.38 ; + RECT 9.98 86.855 10.26 87.225 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + RECT 9.98 -0.185 10.26 0.185 ; + POLYGON 95.4 97.64 95.4 0.28 0.28 0.28 0.28 86.76 5.17 86.76 5.17 85.4 5.87 85.4 5.87 86.76 6.09 86.76 6.09 85.4 6.79 85.4 6.79 86.76 7.01 86.76 7.01 85.4 7.71 85.4 7.71 86.76 7.93 86.76 7.93 85.4 8.63 85.4 8.63 86.76 10.69 86.76 10.69 85.4 11.39 85.4 11.39 86.76 11.61 86.76 11.61 85.4 12.31 85.4 12.31 86.76 12.53 86.76 12.53 85.4 13.23 85.4 13.23 86.76 17.59 86.76 17.59 85.4 18.29 85.4 18.29 86.76 27.88 86.76 27.88 97.64 35.07 97.64 35.07 96.28 35.77 96.28 35.77 97.64 36.91 97.64 36.91 96.28 37.61 96.28 37.61 97.64 37.83 97.64 37.83 96.28 38.53 96.28 38.53 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.51 97.64 41.51 96.28 42.21 96.28 42.21 97.64 42.43 97.64 42.43 96.28 43.13 96.28 43.13 97.64 43.35 97.64 43.35 96.28 44.05 96.28 44.05 97.64 44.27 97.64 44.27 96.28 44.97 96.28 44.97 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 53.01 97.64 53.01 96.28 53.71 96.28 53.71 97.64 54.85 97.64 54.85 96.28 55.55 96.28 55.55 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 63.13 97.64 63.13 96.28 63.83 96.28 63.83 97.64 64.05 97.64 64.05 96.28 64.75 96.28 64.75 97.64 64.97 97.64 64.97 96.28 65.67 96.28 65.67 97.64 65.89 97.64 65.89 96.28 66.59 96.28 66.59 97.64 66.81 97.64 66.81 96.28 67.51 96.28 67.51 97.64 67.73 97.64 67.73 96.28 68.43 96.28 68.43 97.64 70.49 97.64 70.49 96.28 71.19 96.28 71.19 97.64 76.93 97.64 76.93 96.28 77.63 96.28 77.63 97.64 77.85 97.64 77.85 96.28 78.55 96.28 78.55 97.64 78.77 97.64 78.77 96.28 79.47 96.28 79.47 97.64 79.69 97.64 79.69 96.28 80.39 96.28 80.39 97.64 80.61 97.64 80.61 96.28 81.31 96.28 81.31 97.64 ; + LAYER met4 ; + POLYGON 95.28 97.52 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 10.82 0.4 10.82 1 9.42 1 9.42 0.4 0.4 0.4 0.4 86.64 9.42 86.64 9.42 86.04 10.82 86.04 10.82 86.64 28 86.64 28 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 43.61 97.52 43.61 96.16 44.71 96.16 44.71 97.52 45.45 97.52 45.45 96.16 46.55 96.16 46.55 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 61.09 97.52 61.09 96.16 62.19 96.16 62.19 97.52 62.93 97.52 62.93 96.16 64.03 96.16 64.03 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; LAYER met5 ; - POLYGON 83.04 80 83.04 56.24 79.84 56.24 79.84 49.84 83.04 49.84 83.04 35.84 79.84 35.84 79.84 29.44 83.04 29.44 83.04 15.44 79.84 15.44 79.84 9.04 83.04 9.04 83.04 1.6 1.6 1.6 1.6 9.04 4.8 9.04 4.8 15.44 1.6 15.44 1.6 29.44 4.8 29.44 4.8 35.84 1.6 35.84 1.6 49.84 4.8 49.84 4.8 56.24 1.6 56.24 1.6 63.68 20 63.68 20 80 ; + POLYGON 94.08 96.32 94.08 77.32 90.88 77.32 90.88 70.92 94.08 70.92 94.08 56.92 90.88 56.92 90.88 50.52 94.08 50.52 94.08 36.52 90.88 36.52 90.88 30.12 94.08 30.12 94.08 16.12 90.88 16.12 90.88 9.72 94.08 9.72 94.08 1.6 1.6 1.6 1.6 9.72 4.8 9.72 4.8 16.12 1.6 16.12 1.6 30.12 4.8 30.12 4.8 36.52 1.6 36.52 1.6 50.52 4.8 50.52 4.8 56.92 1.6 56.92 1.6 70.92 4.8 70.92 4.8 77.32 1.6 77.32 1.6 85.44 29.2 85.44 29.2 96.32 ; LAYER met1 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 18.68 65.8 18.68 67.48 19.16 67.48 19.16 68.52 18.68 68.52 18.68 70.2 19.16 70.2 19.16 71.24 18.68 71.24 18.68 72.92 19.16 72.92 19.16 73.96 18.68 73.96 18.68 75.64 19.16 75.64 19.16 76.68 18.68 76.68 18.68 78.36 19.16 78.36 19.16 79.4 18.68 79.4 18.68 81.08 ; - POLYGON 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 83.88 16.84 83.88 15.8 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 27.88 87.56 27.88 89.24 28.36 89.24 28.36 90.28 27.88 90.28 27.88 91.96 28.36 91.96 28.36 93 27.88 93 27.88 94.68 28.36 94.68 28.36 95.72 27.88 95.72 27.88 97.4 ; + POLYGON 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 94.92 11.4 94.92 10.36 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 0.28 0.52 0.28 2.2 0.76 2.2 0.76 3.24 0.28 3.24 0.28 4.92 0.76 4.92 0.76 5.96 0.28 5.96 0.28 7.64 0.76 7.64 0.76 8.68 0.28 8.68 0.28 10.36 0.76 10.36 0.76 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 ; LAYER li1 ; - POLYGON 84.47 81.43 84.47 0.17 0.17 0.17 0.17 65.11 18.57 65.11 18.57 81.43 ; + POLYGON 95.51 97.75 95.51 0.17 0.17 0.17 0.17 86.87 27.77 86.87 27.77 97.75 ; LAYER mcon ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; - RECT 19.005 78.795 19.175 78.965 ; - RECT 18.545 78.795 18.715 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; - RECT 19.005 76.075 19.175 76.245 ; - RECT 18.545 76.075 18.715 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; - RECT 19.005 73.355 19.175 73.525 ; - RECT 18.545 73.355 18.715 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; - RECT 19.005 70.635 19.175 70.805 ; - RECT 18.545 70.635 18.715 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; - RECT 19.005 67.915 19.175 68.085 ; - RECT 18.545 67.915 18.715 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; - RECT 83.405 65.195 83.575 65.365 ; - RECT 82.945 65.195 83.115 65.365 ; - RECT 82.485 65.195 82.655 65.365 ; - RECT 82.025 65.195 82.195 65.365 ; - RECT 81.565 65.195 81.735 65.365 ; - RECT 81.105 65.195 81.275 65.365 ; - RECT 80.645 65.195 80.815 65.365 ; - RECT 80.185 65.195 80.355 65.365 ; - RECT 79.725 65.195 79.895 65.365 ; - RECT 79.265 65.195 79.435 65.365 ; - RECT 78.805 65.195 78.975 65.365 ; - RECT 78.345 65.195 78.515 65.365 ; - RECT 77.885 65.195 78.055 65.365 ; - RECT 77.425 65.195 77.595 65.365 ; - RECT 76.965 65.195 77.135 65.365 ; - RECT 76.505 65.195 76.675 65.365 ; - RECT 76.045 65.195 76.215 65.365 ; - RECT 75.585 65.195 75.755 65.365 ; - RECT 75.125 65.195 75.295 65.365 ; - RECT 74.665 65.195 74.835 65.365 ; - RECT 74.205 65.195 74.375 65.365 ; - RECT 73.745 65.195 73.915 65.365 ; - RECT 73.285 65.195 73.455 65.365 ; - RECT 72.825 65.195 72.995 65.365 ; - RECT 72.365 65.195 72.535 65.365 ; - RECT 71.905 65.195 72.075 65.365 ; - RECT 71.445 65.195 71.615 65.365 ; - RECT 70.985 65.195 71.155 65.365 ; - RECT 70.525 65.195 70.695 65.365 ; - RECT 70.065 65.195 70.235 65.365 ; - RECT 69.605 65.195 69.775 65.365 ; - RECT 69.145 65.195 69.315 65.365 ; - RECT 68.685 65.195 68.855 65.365 ; - RECT 68.225 65.195 68.395 65.365 ; - RECT 67.765 65.195 67.935 65.365 ; - RECT 67.305 65.195 67.475 65.365 ; - RECT 66.845 65.195 67.015 65.365 ; - RECT 66.385 65.195 66.555 65.365 ; - RECT 65.925 65.195 66.095 65.365 ; - RECT 65.465 65.195 65.635 65.365 ; - RECT 65.005 65.195 65.175 65.365 ; - RECT 64.545 65.195 64.715 65.365 ; - RECT 64.085 65.195 64.255 65.365 ; - RECT 63.625 65.195 63.795 65.365 ; - RECT 63.165 65.195 63.335 65.365 ; - RECT 62.705 65.195 62.875 65.365 ; - RECT 62.245 65.195 62.415 65.365 ; - RECT 61.785 65.195 61.955 65.365 ; - RECT 61.325 65.195 61.495 65.365 ; - RECT 60.865 65.195 61.035 65.365 ; - RECT 60.405 65.195 60.575 65.365 ; - RECT 59.945 65.195 60.115 65.365 ; - RECT 59.485 65.195 59.655 65.365 ; - RECT 59.025 65.195 59.195 65.365 ; - RECT 58.565 65.195 58.735 65.365 ; - RECT 58.105 65.195 58.275 65.365 ; - RECT 57.645 65.195 57.815 65.365 ; - RECT 57.185 65.195 57.355 65.365 ; - RECT 56.725 65.195 56.895 65.365 ; - RECT 56.265 65.195 56.435 65.365 ; - RECT 55.805 65.195 55.975 65.365 ; - RECT 55.345 65.195 55.515 65.365 ; - RECT 54.885 65.195 55.055 65.365 ; - RECT 54.425 65.195 54.595 65.365 ; - RECT 53.965 65.195 54.135 65.365 ; - RECT 53.505 65.195 53.675 65.365 ; - RECT 53.045 65.195 53.215 65.365 ; - RECT 52.585 65.195 52.755 65.365 ; - RECT 52.125 65.195 52.295 65.365 ; - RECT 51.665 65.195 51.835 65.365 ; - RECT 51.205 65.195 51.375 65.365 ; - RECT 50.745 65.195 50.915 65.365 ; - RECT 50.285 65.195 50.455 65.365 ; - RECT 49.825 65.195 49.995 65.365 ; - RECT 49.365 65.195 49.535 65.365 ; - RECT 48.905 65.195 49.075 65.365 ; - RECT 48.445 65.195 48.615 65.365 ; - RECT 47.985 65.195 48.155 65.365 ; - RECT 47.525 65.195 47.695 65.365 ; - RECT 47.065 65.195 47.235 65.365 ; - RECT 46.605 65.195 46.775 65.365 ; - RECT 46.145 65.195 46.315 65.365 ; - RECT 45.685 65.195 45.855 65.365 ; - RECT 45.225 65.195 45.395 65.365 ; - RECT 44.765 65.195 44.935 65.365 ; - RECT 44.305 65.195 44.475 65.365 ; - RECT 43.845 65.195 44.015 65.365 ; - RECT 43.385 65.195 43.555 65.365 ; - RECT 42.925 65.195 43.095 65.365 ; - RECT 42.465 65.195 42.635 65.365 ; - RECT 42.005 65.195 42.175 65.365 ; - RECT 41.545 65.195 41.715 65.365 ; - RECT 41.085 65.195 41.255 65.365 ; - RECT 40.625 65.195 40.795 65.365 ; - RECT 40.165 65.195 40.335 65.365 ; - RECT 39.705 65.195 39.875 65.365 ; - RECT 39.245 65.195 39.415 65.365 ; - RECT 38.785 65.195 38.955 65.365 ; - RECT 38.325 65.195 38.495 65.365 ; - RECT 37.865 65.195 38.035 65.365 ; - RECT 37.405 65.195 37.575 65.365 ; - RECT 36.945 65.195 37.115 65.365 ; - RECT 36.485 65.195 36.655 65.365 ; - RECT 36.025 65.195 36.195 65.365 ; - RECT 35.565 65.195 35.735 65.365 ; - RECT 35.105 65.195 35.275 65.365 ; - RECT 34.645 65.195 34.815 65.365 ; - RECT 34.185 65.195 34.355 65.365 ; - RECT 33.725 65.195 33.895 65.365 ; - RECT 33.265 65.195 33.435 65.365 ; - RECT 32.805 65.195 32.975 65.365 ; - RECT 32.345 65.195 32.515 65.365 ; - RECT 31.885 65.195 32.055 65.365 ; - RECT 31.425 65.195 31.595 65.365 ; - RECT 30.965 65.195 31.135 65.365 ; - RECT 30.505 65.195 30.675 65.365 ; - RECT 30.045 65.195 30.215 65.365 ; - RECT 29.585 65.195 29.755 65.365 ; - RECT 29.125 65.195 29.295 65.365 ; - RECT 28.665 65.195 28.835 65.365 ; - RECT 28.205 65.195 28.375 65.365 ; - RECT 27.745 65.195 27.915 65.365 ; - RECT 27.285 65.195 27.455 65.365 ; - RECT 26.825 65.195 26.995 65.365 ; - RECT 26.365 65.195 26.535 65.365 ; - RECT 25.905 65.195 26.075 65.365 ; - RECT 25.445 65.195 25.615 65.365 ; - RECT 24.985 65.195 25.155 65.365 ; - RECT 24.525 65.195 24.695 65.365 ; - RECT 24.065 65.195 24.235 65.365 ; - RECT 23.605 65.195 23.775 65.365 ; - RECT 23.145 65.195 23.315 65.365 ; - RECT 22.685 65.195 22.855 65.365 ; - RECT 22.225 65.195 22.395 65.365 ; - RECT 21.765 65.195 21.935 65.365 ; - RECT 21.305 65.195 21.475 65.365 ; - RECT 20.845 65.195 21.015 65.365 ; - RECT 20.385 65.195 20.555 65.365 ; - RECT 19.925 65.195 20.095 65.365 ; - RECT 19.465 65.195 19.635 65.365 ; - RECT 19.005 65.195 19.175 65.365 ; - RECT 18.545 65.195 18.715 65.365 ; - RECT 18.085 65.195 18.255 65.365 ; - RECT 17.625 65.195 17.795 65.365 ; - RECT 17.165 65.195 17.335 65.365 ; - RECT 16.705 65.195 16.875 65.365 ; - RECT 16.245 65.195 16.415 65.365 ; - RECT 15.785 65.195 15.955 65.365 ; - RECT 15.325 65.195 15.495 65.365 ; - RECT 14.865 65.195 15.035 65.365 ; - RECT 14.405 65.195 14.575 65.365 ; - RECT 13.945 65.195 14.115 65.365 ; - RECT 13.485 65.195 13.655 65.365 ; - RECT 13.025 65.195 13.195 65.365 ; - RECT 12.565 65.195 12.735 65.365 ; - RECT 12.105 65.195 12.275 65.365 ; - RECT 11.645 65.195 11.815 65.365 ; - RECT 11.185 65.195 11.355 65.365 ; - RECT 10.725 65.195 10.895 65.365 ; - RECT 10.265 65.195 10.435 65.365 ; - RECT 9.805 65.195 9.975 65.365 ; - RECT 9.345 65.195 9.515 65.365 ; - RECT 8.885 65.195 9.055 65.365 ; - RECT 8.425 65.195 8.595 65.365 ; - RECT 7.965 65.195 8.135 65.365 ; - RECT 7.505 65.195 7.675 65.365 ; - RECT 7.045 65.195 7.215 65.365 ; - RECT 6.585 65.195 6.755 65.365 ; - RECT 6.125 65.195 6.295 65.365 ; - RECT 5.665 65.195 5.835 65.365 ; - RECT 5.205 65.195 5.375 65.365 ; - RECT 4.745 65.195 4.915 65.365 ; - RECT 4.285 65.195 4.455 65.365 ; - RECT 3.825 65.195 3.995 65.365 ; - RECT 3.365 65.195 3.535 65.365 ; - RECT 2.905 65.195 3.075 65.365 ; - RECT 2.445 65.195 2.615 65.365 ; - RECT 1.985 65.195 2.155 65.365 ; - RECT 1.525 65.195 1.695 65.365 ; - RECT 1.065 65.195 1.235 65.365 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; + RECT 28.205 95.115 28.375 95.285 ; + RECT 27.745 95.115 27.915 95.285 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; + RECT 28.205 92.395 28.375 92.565 ; + RECT 27.745 92.395 27.915 92.565 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; + RECT 28.205 89.675 28.375 89.845 ; + RECT 27.745 89.675 27.915 89.845 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 94.445 86.955 94.615 87.125 ; + RECT 93.985 86.955 94.155 87.125 ; + RECT 93.525 86.955 93.695 87.125 ; + RECT 93.065 86.955 93.235 87.125 ; + RECT 92.605 86.955 92.775 87.125 ; + RECT 92.145 86.955 92.315 87.125 ; + RECT 91.685 86.955 91.855 87.125 ; + RECT 91.225 86.955 91.395 87.125 ; + RECT 90.765 86.955 90.935 87.125 ; + RECT 90.305 86.955 90.475 87.125 ; + RECT 89.845 86.955 90.015 87.125 ; + RECT 89.385 86.955 89.555 87.125 ; + RECT 88.925 86.955 89.095 87.125 ; + RECT 88.465 86.955 88.635 87.125 ; + RECT 88.005 86.955 88.175 87.125 ; + RECT 87.545 86.955 87.715 87.125 ; + RECT 87.085 86.955 87.255 87.125 ; + RECT 86.625 86.955 86.795 87.125 ; + RECT 86.165 86.955 86.335 87.125 ; + RECT 85.705 86.955 85.875 87.125 ; + RECT 85.245 86.955 85.415 87.125 ; + RECT 84.785 86.955 84.955 87.125 ; + RECT 84.325 86.955 84.495 87.125 ; + RECT 83.865 86.955 84.035 87.125 ; + RECT 83.405 86.955 83.575 87.125 ; + RECT 82.945 86.955 83.115 87.125 ; + RECT 82.485 86.955 82.655 87.125 ; + RECT 82.025 86.955 82.195 87.125 ; + RECT 81.565 86.955 81.735 87.125 ; + RECT 81.105 86.955 81.275 87.125 ; + RECT 80.645 86.955 80.815 87.125 ; + RECT 80.185 86.955 80.355 87.125 ; + RECT 79.725 86.955 79.895 87.125 ; + RECT 79.265 86.955 79.435 87.125 ; + RECT 78.805 86.955 78.975 87.125 ; + RECT 78.345 86.955 78.515 87.125 ; + RECT 77.885 86.955 78.055 87.125 ; + RECT 77.425 86.955 77.595 87.125 ; + RECT 76.965 86.955 77.135 87.125 ; + RECT 76.505 86.955 76.675 87.125 ; + RECT 76.045 86.955 76.215 87.125 ; + RECT 75.585 86.955 75.755 87.125 ; + RECT 75.125 86.955 75.295 87.125 ; + RECT 74.665 86.955 74.835 87.125 ; + RECT 74.205 86.955 74.375 87.125 ; + RECT 73.745 86.955 73.915 87.125 ; + RECT 73.285 86.955 73.455 87.125 ; + RECT 72.825 86.955 72.995 87.125 ; + RECT 72.365 86.955 72.535 87.125 ; + RECT 71.905 86.955 72.075 87.125 ; + RECT 71.445 86.955 71.615 87.125 ; + RECT 70.985 86.955 71.155 87.125 ; + RECT 70.525 86.955 70.695 87.125 ; + RECT 70.065 86.955 70.235 87.125 ; + RECT 69.605 86.955 69.775 87.125 ; + RECT 69.145 86.955 69.315 87.125 ; + RECT 68.685 86.955 68.855 87.125 ; + RECT 68.225 86.955 68.395 87.125 ; + RECT 67.765 86.955 67.935 87.125 ; + RECT 67.305 86.955 67.475 87.125 ; + RECT 66.845 86.955 67.015 87.125 ; + RECT 66.385 86.955 66.555 87.125 ; + RECT 65.925 86.955 66.095 87.125 ; + RECT 65.465 86.955 65.635 87.125 ; + RECT 65.005 86.955 65.175 87.125 ; + RECT 64.545 86.955 64.715 87.125 ; + RECT 64.085 86.955 64.255 87.125 ; + RECT 63.625 86.955 63.795 87.125 ; + RECT 63.165 86.955 63.335 87.125 ; + RECT 62.705 86.955 62.875 87.125 ; + RECT 62.245 86.955 62.415 87.125 ; + RECT 61.785 86.955 61.955 87.125 ; + RECT 61.325 86.955 61.495 87.125 ; + RECT 60.865 86.955 61.035 87.125 ; + RECT 60.405 86.955 60.575 87.125 ; + RECT 59.945 86.955 60.115 87.125 ; + RECT 59.485 86.955 59.655 87.125 ; + RECT 59.025 86.955 59.195 87.125 ; + RECT 58.565 86.955 58.735 87.125 ; + RECT 58.105 86.955 58.275 87.125 ; + RECT 57.645 86.955 57.815 87.125 ; + RECT 57.185 86.955 57.355 87.125 ; + RECT 56.725 86.955 56.895 87.125 ; + RECT 56.265 86.955 56.435 87.125 ; + RECT 55.805 86.955 55.975 87.125 ; + RECT 55.345 86.955 55.515 87.125 ; + RECT 54.885 86.955 55.055 87.125 ; + RECT 54.425 86.955 54.595 87.125 ; + RECT 53.965 86.955 54.135 87.125 ; + RECT 53.505 86.955 53.675 87.125 ; + RECT 53.045 86.955 53.215 87.125 ; + RECT 52.585 86.955 52.755 87.125 ; + RECT 52.125 86.955 52.295 87.125 ; + RECT 51.665 86.955 51.835 87.125 ; + RECT 51.205 86.955 51.375 87.125 ; + RECT 50.745 86.955 50.915 87.125 ; + RECT 50.285 86.955 50.455 87.125 ; + RECT 49.825 86.955 49.995 87.125 ; + RECT 49.365 86.955 49.535 87.125 ; + RECT 48.905 86.955 49.075 87.125 ; + RECT 48.445 86.955 48.615 87.125 ; + RECT 47.985 86.955 48.155 87.125 ; + RECT 47.525 86.955 47.695 87.125 ; + RECT 47.065 86.955 47.235 87.125 ; + RECT 46.605 86.955 46.775 87.125 ; + RECT 46.145 86.955 46.315 87.125 ; + RECT 45.685 86.955 45.855 87.125 ; + RECT 45.225 86.955 45.395 87.125 ; + RECT 44.765 86.955 44.935 87.125 ; + RECT 44.305 86.955 44.475 87.125 ; + RECT 43.845 86.955 44.015 87.125 ; + RECT 43.385 86.955 43.555 87.125 ; + RECT 42.925 86.955 43.095 87.125 ; + RECT 42.465 86.955 42.635 87.125 ; + RECT 42.005 86.955 42.175 87.125 ; + RECT 41.545 86.955 41.715 87.125 ; + RECT 41.085 86.955 41.255 87.125 ; + RECT 40.625 86.955 40.795 87.125 ; + RECT 40.165 86.955 40.335 87.125 ; + RECT 39.705 86.955 39.875 87.125 ; + RECT 39.245 86.955 39.415 87.125 ; + RECT 38.785 86.955 38.955 87.125 ; + RECT 38.325 86.955 38.495 87.125 ; + RECT 37.865 86.955 38.035 87.125 ; + RECT 37.405 86.955 37.575 87.125 ; + RECT 36.945 86.955 37.115 87.125 ; + RECT 36.485 86.955 36.655 87.125 ; + RECT 36.025 86.955 36.195 87.125 ; + RECT 35.565 86.955 35.735 87.125 ; + RECT 35.105 86.955 35.275 87.125 ; + RECT 34.645 86.955 34.815 87.125 ; + RECT 34.185 86.955 34.355 87.125 ; + RECT 33.725 86.955 33.895 87.125 ; + RECT 33.265 86.955 33.435 87.125 ; + RECT 32.805 86.955 32.975 87.125 ; + RECT 32.345 86.955 32.515 87.125 ; + RECT 31.885 86.955 32.055 87.125 ; + RECT 31.425 86.955 31.595 87.125 ; + RECT 30.965 86.955 31.135 87.125 ; + RECT 30.505 86.955 30.675 87.125 ; + RECT 30.045 86.955 30.215 87.125 ; + RECT 29.585 86.955 29.755 87.125 ; + RECT 29.125 86.955 29.295 87.125 ; + RECT 28.665 86.955 28.835 87.125 ; + RECT 28.205 86.955 28.375 87.125 ; + RECT 27.745 86.955 27.915 87.125 ; + RECT 27.285 86.955 27.455 87.125 ; + RECT 26.825 86.955 26.995 87.125 ; + RECT 26.365 86.955 26.535 87.125 ; + RECT 25.905 86.955 26.075 87.125 ; + RECT 25.445 86.955 25.615 87.125 ; + RECT 24.985 86.955 25.155 87.125 ; + RECT 24.525 86.955 24.695 87.125 ; + RECT 24.065 86.955 24.235 87.125 ; + RECT 23.605 86.955 23.775 87.125 ; + RECT 23.145 86.955 23.315 87.125 ; + RECT 22.685 86.955 22.855 87.125 ; + RECT 22.225 86.955 22.395 87.125 ; + RECT 21.765 86.955 21.935 87.125 ; + RECT 21.305 86.955 21.475 87.125 ; + RECT 20.845 86.955 21.015 87.125 ; + RECT 20.385 86.955 20.555 87.125 ; + RECT 19.925 86.955 20.095 87.125 ; + RECT 19.465 86.955 19.635 87.125 ; + RECT 19.005 86.955 19.175 87.125 ; + RECT 18.545 86.955 18.715 87.125 ; + RECT 18.085 86.955 18.255 87.125 ; + RECT 17.625 86.955 17.795 87.125 ; + RECT 17.165 86.955 17.335 87.125 ; + RECT 16.705 86.955 16.875 87.125 ; + RECT 16.245 86.955 16.415 87.125 ; + RECT 15.785 86.955 15.955 87.125 ; + RECT 15.325 86.955 15.495 87.125 ; + RECT 14.865 86.955 15.035 87.125 ; + RECT 14.405 86.955 14.575 87.125 ; + RECT 13.945 86.955 14.115 87.125 ; + RECT 13.485 86.955 13.655 87.125 ; + RECT 13.025 86.955 13.195 87.125 ; + RECT 12.565 86.955 12.735 87.125 ; + RECT 12.105 86.955 12.275 87.125 ; + RECT 11.645 86.955 11.815 87.125 ; + RECT 11.185 86.955 11.355 87.125 ; + RECT 10.725 86.955 10.895 87.125 ; + RECT 10.265 86.955 10.435 87.125 ; + RECT 9.805 86.955 9.975 87.125 ; + RECT 9.345 86.955 9.515 87.125 ; + RECT 8.885 86.955 9.055 87.125 ; + RECT 8.425 86.955 8.595 87.125 ; + RECT 7.965 86.955 8.135 87.125 ; + RECT 7.505 86.955 7.675 87.125 ; + RECT 7.045 86.955 7.215 87.125 ; + RECT 6.585 86.955 6.755 87.125 ; + RECT 6.125 86.955 6.295 87.125 ; + RECT 5.665 86.955 5.835 87.125 ; + RECT 5.205 86.955 5.375 87.125 ; + RECT 4.745 86.955 4.915 87.125 ; + RECT 4.285 86.955 4.455 87.125 ; + RECT 3.825 86.955 3.995 87.125 ; + RECT 3.365 86.955 3.535 87.125 ; + RECT 2.905 86.955 3.075 87.125 ; + RECT 2.445 86.955 2.615 87.125 ; + RECT 1.985 86.955 2.155 87.125 ; + RECT 1.525 86.955 1.695 87.125 ; + RECT 1.065 86.955 1.235 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; + RECT 0.605 81.515 0.775 81.685 ; + RECT 0.145 81.515 0.315 81.685 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; + RECT 0.605 78.795 0.775 78.965 ; + RECT 0.145 78.795 0.315 78.965 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; + RECT 0.605 76.075 0.775 76.245 ; + RECT 0.145 76.075 0.315 76.245 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; + RECT 0.605 73.355 0.775 73.525 ; + RECT 0.145 73.355 0.315 73.525 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; + RECT 0.605 70.635 0.775 70.805 ; + RECT 0.145 70.635 0.315 70.805 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; + RECT 0.605 67.915 0.775 68.085 ; + RECT 0.145 67.915 0.315 68.085 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; RECT 0.605 13.515 0.775 13.685 ; RECT 0.145 13.515 0.315 13.685 ; - RECT 84.325 10.795 84.495 10.965 ; - RECT 83.865 10.795 84.035 10.965 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; RECT 0.605 10.795 0.775 10.965 ; RECT 0.145 10.795 0.315 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; RECT 0.605 8.075 0.775 8.245 ; RECT 0.145 8.075 0.315 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; RECT 0.605 5.355 0.775 5.525 ; RECT 0.145 5.355 0.315 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; RECT 0.605 2.635 0.775 2.805 ; RECT 0.145 2.635 0.315 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -1943,32 +2058,43 @@ MACRO sb_2__0_ RECT 0.605 -0.085 0.775 0.085 ; RECT 0.145 -0.085 0.315 0.085 ; LAYER via ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 49.145 79.825 49.295 79.975 ; - RECT 73.525 65.205 73.675 65.355 ; - RECT 44.085 65.205 44.235 65.355 ; - RECT 4.525 63.505 4.675 63.655 ; - RECT 3.605 63.505 3.755 63.655 ; - RECT 2.225 1.625 2.375 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 67.085 96.145 67.235 96.295 ; + RECT 46.385 96.145 46.535 96.295 ; + RECT 38.105 96.145 38.255 96.295 ; + RECT 83.645 86.965 83.795 87.115 ; + RECT 54.205 86.965 54.355 87.115 ; + RECT 10.045 86.965 10.195 87.115 ; + RECT 8.205 85.265 8.355 85.415 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; + RECT 10.045 -0.075 10.195 0.075 ; LAYER via2 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 86.94 10.22 87.14 ; + RECT 1.28 76.74 1.48 76.94 ; + RECT 1.74 74.02 1.94 74.22 ; + RECT 1.74 61.1 1.94 61.3 ; RECT 1.28 57.02 1.48 57.22 ; - RECT 1.28 41.38 1.48 41.58 ; - RECT 1.74 24.38 1.94 24.58 ; - RECT 1.74 8.06 1.94 8.26 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 1.28 52.94 1.48 53.14 ; + RECT 1.28 33.9 1.48 34.1 ; + RECT 1.28 26.42 1.48 26.62 ; + RECT 1.74 20.3 1.94 20.5 ; + RECT 1.28 13.5 1.48 13.7 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; + RECT 10.02 -0.1 10.22 0.1 ; LAYER via3 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 86.94 10.22 87.14 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; + RECT 10.02 -0.1 10.22 0.1 ; LAYER OVERLAP ; - POLYGON 0 0 0 65.28 18.4 65.28 18.4 81.6 84.64 81.6 84.64 0 ; + POLYGON 0 0 0 87.04 27.6 87.04 27.6 97.92 95.68 97.92 95.68 0 ; END END sb_2__0_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef index c443aa8..3bd2d87 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__1__icv_in_design.lef @@ -356,14 +356,14 @@ END unithddbl MACRO sb_2__1_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 97.92 ; + SIZE 95.68 BY 108.8 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT - LAYER met2 ; - RECT 2.23 80.24 2.37 81.6 ; + LAYER met3 ; + RECT 0 17.53 1.38 17.83 ; END END prog_clk[0] PIN chany_top_in[0] @@ -371,15 +371,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 96.56 56.65 97.92 ; + RECT 61.11 107.44 61.25 108.8 ; END END chany_top_in[0] PIN chany_top_in[1] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 33.05 96.56 33.19 97.92 ; + LAYER met4 ; + RECT 63.33 107.44 63.63 108.8 ; END END chany_top_in[1] PIN chany_top_in[2] @@ -387,7 +387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 56.89 96.56 57.19 97.92 ; + RECT 61.49 107.44 61.79 108.8 ; END END chany_top_in[2] PIN chany_top_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 96.56 32.27 97.92 ; + RECT 51.91 107.44 52.05 108.8 ; END END chany_top_in[3] PIN chany_top_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 96.56 23.07 97.92 ; + RECT 57.43 107.44 57.57 108.8 ; END END chany_top_in[4] PIN chany_top_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 96.56 49.29 97.92 ; + RECT 62.03 107.44 62.17 108.8 ; END END chany_top_in[5] PIN chany_top_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 96.56 64.01 97.92 ; + RECT 68.01 107.44 68.15 108.8 ; END END chany_top_in[6] PIN chany_top_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 96.56 57.57 97.92 ; + RECT 49.15 107.44 49.29 108.8 ; END END chany_top_in[7] PIN chany_top_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.03 96.56 62.17 97.92 ; + RECT 66.17 107.44 66.31 108.8 ; END END chany_top_in[8] PIN chany_top_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 45.85 96.56 46.15 97.92 ; + RECT 45.85 107.44 46.15 108.8 ; END END chany_top_in[9] PIN chany_top_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met4 ; - RECT 48.61 96.56 48.91 97.92 ; + RECT 44.01 107.44 44.31 108.8 ; END END chany_top_in[10] PIN chany_top_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 96.56 48.37 97.92 ; + RECT 78.13 107.44 78.27 108.8 ; END END chany_top_in[11] PIN chany_top_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 52.83 96.56 52.97 97.92 ; + RECT 58.35 107.44 58.49 108.8 ; END END chany_top_in[12] PIN chany_top_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 96.56 64.93 97.92 ; + RECT 59.27 107.44 59.41 108.8 ; END END chany_top_in[13] PIN chany_top_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.11 96.56 61.25 97.92 ; + RECT 70.77 107.44 70.91 108.8 ; END END chany_top_in[14] PIN chany_top_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.27 96.56 59.41 97.92 ; + RECT 64.33 107.44 64.47 108.8 ; END END chany_top_in[15] PIN chany_top_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 96.56 50.21 97.92 ; + RECT 80.89 107.44 81.03 108.8 ; END END chany_top_in[16] PIN chany_top_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 96.56 63.09 97.92 ; + RECT 79.97 107.44 80.11 108.8 ; END END chany_top_in[17] PIN chany_top_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 96.56 58.49 97.92 ; + RECT 60.19 107.44 60.33 108.8 ; END END chany_top_in[18] PIN chany_top_in[19] @@ -523,31 +523,31 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.19 96.56 60.33 97.92 ; + RECT 79.05 107.44 79.19 108.8 ; END END chany_top_in[19] PIN top_left_grid_pin_42_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 96.56 24.99 97.92 ; + LAYER met2 ; + RECT 17.87 96.56 18.01 97.92 ; END END top_left_grid_pin_42_[0] PIN top_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 36.65 96.56 36.95 97.92 ; + LAYER met2 ; + RECT 12.81 96.56 12.95 97.92 ; END END top_left_grid_pin_43_[0] PIN top_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 96.56 23.15 97.92 ; + LAYER met2 ; + RECT 8.21 96.56 8.35 97.92 ; END END top_left_grid_pin_44_[0] PIN top_left_grid_pin_45_[0] @@ -555,15 +555,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 21.55 96.56 21.69 97.92 ; + RECT 11.89 96.56 12.03 97.92 ; END END top_left_grid_pin_45_[0] PIN top_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 34.81 96.56 35.11 97.92 ; + LAYER met2 ; + RECT 6.37 96.56 6.51 97.92 ; END END top_left_grid_pin_46_[0] PIN top_left_grid_pin_47_[0] @@ -571,7 +571,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 80.24 8.81 81.6 ; + RECT 10.97 96.56 11.11 97.92 ; END END top_left_grid_pin_47_[0] PIN top_left_grid_pin_48_[0] @@ -579,7 +579,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 96.56 20.77 97.92 ; + RECT 7.29 96.56 7.43 97.92 ; END END top_left_grid_pin_48_[0] PIN top_left_grid_pin_49_[0] @@ -587,7 +587,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 13.27 80.24 13.41 81.6 ; + RECT 5.45 96.56 5.59 97.92 ; END END top_left_grid_pin_49_[0] PIN top_right_grid_pin_1_[0] @@ -595,15 +595,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 96.56 23.99 97.92 ; + RECT 44.55 107.44 44.69 108.8 ; END END top_right_grid_pin_1_[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + LAYER met4 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -611,15 +611,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + LAYER met4 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 79.97 0 80.11 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 84.57 0 84.71 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -683,7 +683,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -691,7 +691,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -699,7 +699,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -707,7 +707,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -715,7 +715,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 68.01 0 68.15 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -755,7 +755,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; + RECT 80.89 0 81.03 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -763,7 +763,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END bottom_right_grid_pin_1_[0] PIN bottom_left_grid_pin_42_[0] @@ -771,23 +771,23 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + RECT 11.43 10.88 11.57 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 0 23.15 1.36 ; + LAYER met2 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 22.29 1.38 22.59 ; + LAYER met2 ; + RECT 12.35 10.88 12.49 12.24 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] @@ -795,7 +795,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 4.53 16.32 4.67 17.68 ; + RECT 14.19 10.88 14.33 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] @@ -803,31 +803,31 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 2.69 16.32 2.83 17.68 ; + RECT 16.03 10.88 16.17 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 20.93 1.38 21.23 ; + LAYER met2 ; + RECT 17.87 10.88 18.01 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 6.83 16.32 6.97 17.68 ; + LAYER met4 ; + RECT 5.37 10.88 5.67 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 0 19.57 1.38 19.87 ; + LAYER met4 ; + RECT 11.81 10.88 12.11 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -835,7 +835,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 51.53 1.38 51.83 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -843,7 +843,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 23.65 1.38 23.95 ; + RECT 0 71.93 1.38 72.23 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -851,7 +851,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.69 1.38 42.99 ; + RECT 0 85.53 1.38 85.83 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -859,7 +859,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 34.53 1.38 34.83 ; + RECT 0 36.57 1.38 36.87 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -867,7 +867,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.89 1.38 36.19 ; + RECT 0 42.01 1.38 42.31 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -875,15 +875,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 30.45 1.38 30.75 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[5] PIN chanx_left_in[6] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 16.32 4.75 17.68 ; + LAYER met3 ; + RECT 0 90.97 1.38 91.27 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -891,7 +891,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.81 1.38 66.11 ; + RECT 0 60.37 1.38 60.67 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -899,7 +899,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.89 1.38 70.19 ; + RECT 0 56.29 1.38 56.59 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -907,7 +907,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 61.05 1.38 61.35 ; + RECT 0 84.17 1.38 84.47 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -915,7 +915,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 41.33 1.38 41.63 ; + RECT 0 88.25 1.38 88.55 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -923,7 +923,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 58.33 1.38 58.63 ; + RECT 0 86.89 1.38 87.19 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -931,7 +931,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 64.45 1.38 64.75 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -939,7 +939,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -947,7 +947,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 61.73 1.38 62.03 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -955,7 +955,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.89 1.38 53.19 ; + RECT 0 76.01 1.38 76.31 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -963,7 +963,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 81.45 1.38 81.75 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -971,7 +971,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -979,7 +979,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 74.65 1.38 74.95 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -987,23 +987,23 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.09 1.38 29.39 ; + RECT 0 37.93 1.38 38.23 ; END END chanx_left_in[19] PIN left_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 6.65 19.78 6.95 ; + LAYER met2 ; + RECT 15.11 10.88 15.25 12.24 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 5.29 19.78 5.59 ; + LAYER met2 ; + RECT 13.27 10.88 13.41 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -1011,7 +1011,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + RECT 4.99 10.88 5.13 12.24 ; END END left_bottom_grid_pin_36_[0] PIN left_bottom_grid_pin_37_[0] @@ -1019,7 +1019,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 16.32 5.59 17.68 ; + RECT 5.91 10.88 6.05 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -1027,7 +1027,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 7.75 10.88 7.89 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] @@ -1035,15 +1035,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 16.32 9.73 17.68 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 24.69 0 24.99 1.36 ; + LAYER met2 ; + RECT 3.15 10.88 3.29 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -1051,7 +1051,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 16.32 7.89 17.68 ; + RECT 6.83 10.88 6.97 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] @@ -1059,7 +1059,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.03 96.56 39.17 97.92 ; + RECT 35.35 107.44 35.49 108.8 ; END END ccff_head[0] PIN chany_top_out[0] @@ -1067,7 +1067,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.87 96.56 41.01 97.92 ; + RECT 53.29 107.44 53.43 108.8 ; END END chany_top_out[0] PIN chany_top_out[1] @@ -1075,7 +1075,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.97 96.56 34.11 97.92 ; + RECT 50.99 107.44 51.13 108.8 ; END END chany_top_out[1] PIN chany_top_out[2] @@ -1083,7 +1083,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 96.56 46.53 97.92 ; + RECT 55.13 107.44 55.27 108.8 ; END END chany_top_out[2] PIN chany_top_out[3] @@ -1091,7 +1091,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 96.56 52.05 97.92 ; + RECT 39.03 107.44 39.17 108.8 ; END END chany_top_out[3] PIN chany_top_out[4] @@ -1099,7 +1099,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 96.56 43.31 97.92 ; + RECT 41.79 107.44 41.93 108.8 ; END END chany_top_out[4] PIN chany_top_out[5] @@ -1107,7 +1107,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 96.56 25.83 97.92 ; + RECT 39.95 107.44 40.09 108.8 ; END END chany_top_out[5] PIN chany_top_out[6] @@ -1115,7 +1115,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 35.35 96.56 35.49 97.92 ; + RECT 77.21 107.44 77.35 108.8 ; END END chany_top_out[6] PIN chany_top_out[7] @@ -1123,7 +1123,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 96.56 47.45 97.92 ; + RECT 38.11 107.44 38.25 108.8 ; END END chany_top_out[7] PIN chany_top_out[8] @@ -1131,7 +1131,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 96.56 37.79 97.92 ; + RECT 65.25 107.44 65.39 108.8 ; END END chany_top_out[8] PIN chany_top_out[9] @@ -1139,7 +1139,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.99 96.56 51.13 97.92 ; + RECT 63.41 107.44 63.55 108.8 ; END END chany_top_out[9] PIN chany_top_out[10] @@ -1147,7 +1147,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 96.56 36.87 97.92 ; + RECT 48.23 107.44 48.37 108.8 ; END END chany_top_out[10] PIN chany_top_out[11] @@ -1155,7 +1155,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 53.75 96.56 53.89 97.92 ; + RECT 37.19 107.44 37.33 108.8 ; END END chany_top_out[11] PIN chany_top_out[12] @@ -1163,7 +1163,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 96.56 29.51 97.92 ; + RECT 50.07 107.44 50.21 108.8 ; END END chany_top_out[12] PIN chany_top_out[13] @@ -1171,7 +1171,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.95 96.56 40.09 97.92 ; + RECT 47.31 107.44 47.45 108.8 ; END END chany_top_out[13] PIN chany_top_out[14] @@ -1179,7 +1179,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 96.56 26.75 97.92 ; + RECT 67.09 107.44 67.23 108.8 ; END END chany_top_out[14] PIN chany_top_out[15] @@ -1187,7 +1187,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 96.56 45.61 97.92 ; + RECT 42.71 107.44 42.85 108.8 ; END END chany_top_out[15] PIN chany_top_out[16] @@ -1195,7 +1195,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 96.56 24.91 97.92 ; + RECT 43.63 107.44 43.77 108.8 ; END END chany_top_out[16] PIN chany_top_out[17] @@ -1203,7 +1203,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 96.56 28.59 97.92 ; + RECT 40.87 107.44 41.01 108.8 ; END END chany_top_out[17] PIN chany_top_out[18] @@ -1211,7 +1211,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 96.56 42.39 97.92 ; + RECT 46.39 107.44 46.53 108.8 ; END END chany_top_out[18] PIN chany_top_out[19] @@ -1219,7 +1219,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 96.56 27.67 97.92 ; + RECT 45.47 107.44 45.61 108.8 ; END END chany_top_out[19] PIN chany_bottom_out[0] @@ -1227,7 +1227,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -1243,7 +1243,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -1251,7 +1251,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -1259,7 +1259,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -1267,7 +1267,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -1275,7 +1275,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -1283,7 +1283,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -1291,7 +1291,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -1299,7 +1299,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -1307,7 +1307,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -1315,7 +1315,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -1323,7 +1323,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -1331,7 +1331,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -1339,7 +1339,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -1347,7 +1347,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -1355,7 +1355,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -1363,7 +1363,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -1371,7 +1371,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -1379,7 +1379,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1387,7 +1387,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 45.41 1.38 45.71 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1395,7 +1395,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 56.97 1.38 57.27 ; + RECT 0 70.57 1.38 70.87 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1403,7 +1403,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.25 1.38 71.55 ; + RECT 0 82.81 1.38 83.11 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1411,7 +1411,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.73 1.38 28.03 ; + RECT 0 67.17 1.38 67.47 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1419,7 +1419,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1427,7 +1427,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.77 1.38 47.07 ; + RECT 0 69.21 1.38 69.51 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1435,7 +1435,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 38.61 1.38 38.91 ; + RECT 0 54.93 1.38 55.23 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1443,7 +1443,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 54.25 1.38 54.55 ; + RECT 0 40.65 1.38 40.95 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1451,7 +1451,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.05 1.38 44.35 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[8] PIN chanx_left_out[9] @@ -1459,7 +1459,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.17 1.38 33.47 ; + RECT 0 57.65 1.38 57.95 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1467,7 +1467,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.17 1.38 67.47 ; + RECT 0 63.09 1.38 63.39 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1475,7 +1475,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.17 1.38 50.47 ; + RECT 0 65.81 1.38 66.11 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1483,15 +1483,15 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 26.37 1.38 26.67 ; + RECT 0 64.45 1.38 64.75 ; END END chanx_left_out[12] PIN chanx_left_out[13] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 6.29 16.32 6.59 17.68 ; + LAYER met3 ; + RECT 0 73.29 1.38 73.59 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1499,7 +1499,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.01 1.38 25.31 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1507,7 +1507,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.97 1.38 40.27 ; + RECT 0 77.37 1.38 77.67 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1515,7 +1515,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.69 1.38 59.99 ; + RECT 0 80.09 1.38 80.39 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1523,7 +1523,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.25 1.38 37.55 ; + RECT 0 39.29 1.38 39.59 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1531,7 +1531,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.81 1.38 32.11 ; + RECT 0 59.01 1.38 59.31 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1539,7 +1539,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 68.53 1.38 68.83 ; + RECT 0 78.73 1.38 79.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1547,7 +1547,7 @@ MACRO sb_2__1_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.09 1.38 63.39 ; + RECT 0 89.61 1.38 89.91 ; END END ccff_tail[0] PIN VDD @@ -1555,52 +1555,56 @@ MACRO sb_2__1_ USE POWER ; PORT LAYER met1 ; - RECT 18.4 2.48 18.88 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; - RECT 18.4 7.92 18.88 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; - RECT 18.4 13.36 18.88 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 27.6 2.48 28.08 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; + RECT 27.6 7.92 28.08 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; + RECT 95.2 62.32 95.68 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; - RECT 18.4 84.08 18.88 84.56 ; - RECT 84.16 84.08 84.64 84.56 ; - RECT 18.4 89.52 18.88 90 ; - RECT 84.16 89.52 84.64 90 ; - RECT 18.4 94.96 18.88 95.44 ; - RECT 84.16 94.96 84.64 95.44 ; + RECT 95.2 78.64 95.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 95.2 89.52 95.68 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; + RECT 27.6 100.4 28.08 100.88 ; + RECT 95.2 100.4 95.68 100.88 ; + RECT 27.6 105.84 28.08 106.32 ; + RECT 95.2 105.84 95.68 106.32 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 97.32 29.74 97.92 ; - RECT 58.58 97.32 59.18 97.92 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 39.26 108.2 39.86 108.8 ; + RECT 68.7 108.2 69.3 108.8 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 81.44 26.96 84.64 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 81.44 67.76 84.64 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 92.48 22.2 95.68 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 92.48 63 95.68 66.2 ; END END VDD PIN VSS @@ -1608,154 +1612,379 @@ MACRO sb_2__1_ USE GROUND ; PORT LAYER met1 ; - RECT 18.4 0 84.64 0.24 ; - RECT 18.4 5.2 18.88 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; - RECT 18.4 10.64 18.88 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; - RECT 0 16.08 84.64 16.56 ; + RECT 27.6 0 95.68 0.24 ; + RECT 27.6 5.2 28.08 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; + RECT 0 10.64 95.68 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; + RECT 95.2 59.6 95.68 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 84.16 65.04 84.64 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 0 81.36 84.64 81.84 ; - RECT 18.4 86.8 18.88 87.28 ; - RECT 84.16 86.8 84.64 87.28 ; - RECT 18.4 92.24 18.88 92.72 ; - RECT 84.16 92.24 84.64 92.72 ; - RECT 18.4 97.68 84.64 97.92 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 95.2 86.8 95.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 0 97.68 95.68 98.16 ; + RECT 27.6 103.12 28.08 103.6 ; + RECT 95.2 103.12 95.68 103.6 ; + RECT 27.6 108.56 95.68 108.8 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 97.32 44.46 97.92 ; - RECT 73.3 97.32 73.9 97.92 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 10.88 10.42 11.48 ; + RECT 9.82 97.32 10.42 97.92 ; + RECT 53.98 108.2 54.58 108.8 ; + RECT 83.42 108.2 84.02 108.8 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 81.44 47.36 84.64 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 92.48 42.6 95.68 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 92.48 83.4 95.68 86.6 ; END END VSS + PIN Test_en__FEEDTHRU_0[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 10.88 2.37 12.24 ; + END + END Test_en__FEEDTHRU_0[0] + PIN Test_en__FEEDTHRU_1[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + PORT + LAYER met2 ; + RECT 2.23 96.56 2.37 97.92 ; + END + END Test_en__FEEDTHRU_1[0] OBS LAYER li1 ; - RECT 18.4 97.835 84.64 98.005 ; - RECT 84.18 95.115 84.64 95.285 ; - RECT 18.4 95.115 22.08 95.285 ; - RECT 84.18 92.395 84.64 92.565 ; - RECT 18.4 92.395 20.24 92.565 ; - RECT 83.72 89.675 84.64 89.845 ; - RECT 18.4 89.675 22.08 89.845 ; - RECT 83.72 86.955 84.64 87.125 ; - RECT 18.4 86.955 22.08 87.125 ; - RECT 80.96 84.235 84.64 84.405 ; - RECT 18.4 84.235 20.24 84.405 ; - RECT 80.96 81.515 84.64 81.685 ; - RECT 0 81.515 20.24 81.685 ; - RECT 80.96 78.795 84.64 78.965 ; - RECT 0 78.795 3.68 78.965 ; - RECT 80.96 76.075 84.64 76.245 ; + RECT 27.6 108.715 95.68 108.885 ; + RECT 94.76 105.995 95.68 106.165 ; + RECT 27.6 105.995 31.28 106.165 ; + RECT 94.76 103.275 95.68 103.445 ; + RECT 27.6 103.275 29.44 103.445 ; + RECT 95.22 100.555 95.68 100.725 ; + RECT 27.6 100.555 29.44 100.725 ; + RECT 95.22 97.835 95.68 98.005 ; + RECT 0 97.835 29.44 98.005 ; + RECT 95.22 95.115 95.68 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 93.84 92.395 95.68 92.565 ; + RECT 0 92.395 1.84 92.565 ; + RECT 93.84 89.675 95.68 89.845 ; + RECT 0 89.675 1.84 89.845 ; + RECT 95.22 86.955 95.68 87.125 ; + RECT 0 86.955 1.84 87.125 ; + RECT 92 84.235 95.68 84.405 ; + RECT 0 84.235 1.84 84.405 ; + RECT 92 81.515 95.68 81.685 ; + RECT 0 81.515 1.84 81.685 ; + RECT 94.76 78.795 95.68 78.965 ; + RECT 0 78.795 1.84 78.965 ; + RECT 94.76 76.075 95.68 76.245 ; RECT 0 76.075 1.84 76.245 ; - RECT 83.72 73.355 84.64 73.525 ; + RECT 94.76 73.355 95.68 73.525 ; RECT 0 73.355 1.84 73.525 ; - RECT 80.96 70.635 84.64 70.805 ; + RECT 92 70.635 95.68 70.805 ; RECT 0 70.635 1.84 70.805 ; - RECT 80.96 67.915 84.64 68.085 ; + RECT 92 67.915 95.68 68.085 ; RECT 0 67.915 1.84 68.085 ; - RECT 83.72 65.195 84.64 65.365 ; + RECT 92 65.195 95.68 65.365 ; RECT 0 65.195 1.84 65.365 ; - RECT 83.72 62.475 84.64 62.645 ; - RECT 0 62.475 3.68 62.645 ; - RECT 83.72 59.755 84.64 59.925 ; + RECT 92 62.475 95.68 62.645 ; + RECT 0 62.475 1.84 62.645 ; + RECT 95.22 59.755 95.68 59.925 ; RECT 0 59.755 3.68 59.925 ; - RECT 83.72 57.035 84.64 57.205 ; + RECT 95.22 57.035 95.68 57.205 ; RECT 0 57.035 3.68 57.205 ; - RECT 83.72 54.315 84.64 54.485 ; - RECT 0 54.315 3.68 54.485 ; - RECT 83.72 51.595 84.64 51.765 ; + RECT 95.22 54.315 95.68 54.485 ; + RECT 0 54.315 1.84 54.485 ; + RECT 95.22 51.595 95.68 51.765 ; RECT 0 51.595 1.84 51.765 ; - RECT 83.72 48.875 84.64 49.045 ; + RECT 94.76 48.875 95.68 49.045 ; RECT 0 48.875 1.84 49.045 ; - RECT 83.72 46.155 84.64 46.325 ; + RECT 94.76 46.155 95.68 46.325 ; RECT 0 46.155 1.84 46.325 ; - RECT 83.72 43.435 84.64 43.605 ; - RECT 0 43.435 3.68 43.605 ; - RECT 83.72 40.715 84.64 40.885 ; - RECT 0 40.715 3.68 40.885 ; - RECT 83.72 37.995 84.64 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 83.72 35.275 84.64 35.445 ; + RECT 95.22 43.435 95.68 43.605 ; + RECT 0 43.435 1.84 43.605 ; + RECT 94.76 40.715 95.68 40.885 ; + RECT 0 40.715 1.84 40.885 ; + RECT 94.76 37.995 95.68 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 95.22 35.275 95.68 35.445 ; RECT 0 35.275 3.68 35.445 ; - RECT 83.72 32.555 84.64 32.725 ; - RECT 0 32.555 1.84 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 94.76 32.555 95.68 32.725 ; + RECT 0 32.555 3.68 32.725 ; + RECT 94.76 29.835 95.68 30.005 ; RECT 0 29.835 1.84 30.005 ; - RECT 83.72 27.115 84.64 27.285 ; + RECT 92 27.115 95.68 27.285 ; RECT 0 27.115 1.84 27.285 ; - RECT 83.72 24.395 84.64 24.565 ; + RECT 92 24.395 95.68 24.565 ; RECT 0 24.395 1.84 24.565 ; - RECT 83.72 21.675 84.64 21.845 ; + RECT 95.22 21.675 95.68 21.845 ; RECT 0 21.675 1.84 21.845 ; - RECT 83.72 18.955 84.64 19.125 ; + RECT 92 18.955 95.68 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 83.72 16.235 84.64 16.405 ; - RECT 0 16.235 22.08 16.405 ; - RECT 83.72 13.515 84.64 13.685 ; - RECT 18.4 13.515 20.24 13.685 ; - RECT 83.72 10.795 84.64 10.965 ; - RECT 18.4 10.795 22.08 10.965 ; - RECT 83.72 8.075 84.64 8.245 ; - RECT 18.4 8.075 22.08 8.245 ; - RECT 84.18 5.355 84.64 5.525 ; - RECT 18.4 5.355 20.24 5.525 ; - RECT 84.18 2.635 84.64 2.805 ; - RECT 18.4 2.635 22.08 2.805 ; - RECT 18.4 -0.085 84.64 0.085 ; - LAYER met2 ; - RECT 73.46 97.735 73.74 98.105 ; - RECT 44.02 97.735 44.3 98.105 ; - RECT 33.45 96.06 33.71 96.38 ; - RECT 41.73 1.54 41.99 1.86 ; - RECT 28.85 1.54 29.11 1.86 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 97.64 84.36 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 7.25 16.6 7.25 17.96 6.55 17.96 6.55 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 3.11 16.6 3.11 17.96 2.41 17.96 2.41 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 8.39 81.32 8.39 79.96 9.09 79.96 9.09 81.32 12.99 81.32 12.99 79.96 13.69 79.96 13.69 81.32 18.68 81.32 18.68 97.64 20.35 97.64 20.35 96.28 21.05 96.28 21.05 97.64 21.27 97.64 21.27 96.28 21.97 96.28 21.97 97.64 22.65 97.64 22.65 96.28 23.35 96.28 23.35 97.64 23.57 97.64 23.57 96.28 24.27 96.28 24.27 97.64 24.49 97.64 24.49 96.28 25.19 96.28 25.19 97.64 25.41 97.64 25.41 96.28 26.11 96.28 26.11 97.64 26.33 97.64 26.33 96.28 27.03 96.28 27.03 97.64 27.25 97.64 27.25 96.28 27.95 96.28 27.95 97.64 28.17 97.64 28.17 96.28 28.87 96.28 28.87 97.64 29.09 97.64 29.09 96.28 29.79 96.28 29.79 97.64 31.85 97.64 31.85 96.28 32.55 96.28 32.55 97.64 32.77 97.64 32.77 96.28 33.47 96.28 33.47 97.64 33.69 97.64 33.69 96.28 34.39 96.28 34.39 97.64 35.07 97.64 35.07 96.28 35.77 96.28 35.77 97.64 36.45 97.64 36.45 96.28 37.15 96.28 37.15 97.64 37.37 97.64 37.37 96.28 38.07 96.28 38.07 97.64 38.75 97.64 38.75 96.28 39.45 96.28 39.45 97.64 39.67 97.64 39.67 96.28 40.37 96.28 40.37 97.64 40.59 97.64 40.59 96.28 41.29 96.28 41.29 97.64 41.97 97.64 41.97 96.28 42.67 96.28 42.67 97.64 42.89 97.64 42.89 96.28 43.59 96.28 43.59 97.64 45.19 97.64 45.19 96.28 45.89 96.28 45.89 97.64 46.11 97.64 46.11 96.28 46.81 96.28 46.81 97.64 47.03 97.64 47.03 96.28 47.73 96.28 47.73 97.64 47.95 97.64 47.95 96.28 48.65 96.28 48.65 97.64 48.87 97.64 48.87 96.28 49.57 96.28 49.57 97.64 49.79 97.64 49.79 96.28 50.49 96.28 50.49 97.64 50.71 97.64 50.71 96.28 51.41 96.28 51.41 97.64 51.63 97.64 51.63 96.28 52.33 96.28 52.33 97.64 52.55 97.64 52.55 96.28 53.25 96.28 53.25 97.64 53.47 97.64 53.47 96.28 54.17 96.28 54.17 97.64 56.23 97.64 56.23 96.28 56.93 96.28 56.93 97.64 57.15 97.64 57.15 96.28 57.85 96.28 57.85 97.64 58.07 97.64 58.07 96.28 58.77 96.28 58.77 97.64 58.99 97.64 58.99 96.28 59.69 96.28 59.69 97.64 59.91 97.64 59.91 96.28 60.61 96.28 60.61 97.64 60.83 97.64 60.83 96.28 61.53 96.28 61.53 97.64 61.75 97.64 61.75 96.28 62.45 96.28 62.45 97.64 62.67 97.64 62.67 96.28 63.37 96.28 63.37 97.64 63.59 97.64 63.59 96.28 64.29 96.28 64.29 97.64 64.51 97.64 64.51 96.28 65.21 96.28 65.21 97.64 ; - LAYER met4 ; - POLYGON 84.24 97.52 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 25.39 0.4 25.39 1.76 24.29 1.76 24.29 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 18.8 81.2 18.8 97.52 22.45 97.52 22.45 96.16 23.55 96.16 23.55 97.52 24.29 97.52 24.29 96.16 25.39 96.16 25.39 97.52 28.74 97.52 28.74 96.92 30.14 96.92 30.14 97.52 34.41 97.52 34.41 96.16 35.51 96.16 35.51 97.52 36.25 97.52 36.25 96.16 37.35 96.16 37.35 97.52 43.46 97.52 43.46 96.92 44.86 96.92 44.86 97.52 45.45 97.52 45.45 96.16 46.55 96.16 46.55 97.52 48.21 97.52 48.21 96.16 49.31 96.16 49.31 97.52 56.49 97.52 56.49 96.16 57.59 96.16 57.59 97.52 58.18 97.52 58.18 96.92 59.58 96.92 59.58 97.52 72.9 97.52 72.9 96.92 74.3 96.92 74.3 97.52 ; + RECT 92 16.235 95.68 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 94.76 13.515 95.68 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 94.76 10.795 95.68 10.965 ; + RECT 0 10.795 29.44 10.965 ; + RECT 95.22 8.075 95.68 8.245 ; + RECT 27.6 8.075 29.44 8.245 ; + RECT 95.22 5.355 95.68 5.525 ; + RECT 27.6 5.355 29.44 5.525 ; + RECT 95.22 2.635 95.68 2.805 ; + RECT 27.6 2.635 31.28 2.805 ; + RECT 27.6 -0.085 95.68 0.085 ; LAYER met3 ; - POLYGON 73.765 98.085 73.765 98.08 73.98 98.08 73.98 97.76 73.765 97.76 73.765 97.755 73.435 97.755 73.435 97.76 73.22 97.76 73.22 98.08 73.435 98.08 73.435 98.085 ; - POLYGON 44.325 98.085 44.325 98.08 44.54 98.08 44.54 97.76 44.325 97.76 44.325 97.755 43.995 97.755 43.995 97.76 43.78 97.76 43.78 98.08 43.995 98.08 43.995 98.085 ; - POLYGON 2.03 68.16 2.03 68.15 4.75 68.15 4.75 67.85 2.03 67.85 2.03 67.84 1.65 67.84 1.65 68.16 ; - POLYGON 44.77 57.95 44.77 57.65 1.23 57.65 1.23 57.93 1.78 57.93 1.78 57.95 ; - POLYGON 39.71 55.23 39.71 54.93 1.23 54.93 1.23 55.21 1.78 55.21 1.78 55.23 ; - POLYGON 2.03 24.64 2.03 24.63 6.13 24.63 6.13 24.33 2.03 24.33 2.03 24.32 1.65 24.32 1.65 24.64 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 97.52 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 16.72 0.4 16.72 0.4 19.17 1.78 19.17 1.78 20.27 0.4 20.27 0.4 20.53 1.78 20.53 1.78 21.63 0.4 21.63 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.29 1.78 42.29 1.78 43.39 0.4 43.39 0.4 43.65 1.78 43.65 1.78 44.75 0.4 44.75 0.4 45.01 1.78 45.01 1.78 46.11 0.4 46.11 0.4 46.37 1.78 46.37 1.78 47.47 0.4 47.47 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 18.8 81.2 18.8 97.52 ; + POLYGON 83.885 108.965 83.885 108.96 84.1 108.96 84.1 108.64 83.885 108.64 83.885 108.635 83.555 108.635 83.555 108.64 83.34 108.64 83.34 108.96 83.555 108.96 83.555 108.965 ; + POLYGON 54.445 108.965 54.445 108.96 54.66 108.96 54.66 108.64 54.445 108.64 54.445 108.635 54.115 108.635 54.115 108.64 53.9 108.64 53.9 108.96 54.115 108.96 54.115 108.965 ; + POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; + POLYGON 5.67 74.27 5.67 73.97 1.99 73.97 1.99 73.29 1.78 73.29 1.78 73.99 1.69 73.99 1.69 74.27 ; + POLYGON 2.03 62.72 2.03 62.71 9.35 62.71 9.35 62.41 2.03 62.41 2.03 62.4 1.65 62.4 1.65 62.72 ; + POLYGON 2.005 58.645 2.005 58.63 2.91 58.63 2.91 58.33 2.005 58.33 2.005 58.315 1.675 58.315 1.675 58.645 ; + POLYGON 14.41 51.15 14.41 50.85 1.78 50.85 1.78 50.87 1.23 50.87 1.23 51.15 ; + POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 95.28 108.4 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 54.53 1.78 54.53 1.78 55.63 0.4 55.63 0.4 55.89 1.78 55.89 1.78 56.99 0.4 56.99 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 61.33 1.78 61.33 1.78 62.43 0.4 62.43 0.4 62.69 1.78 62.69 1.78 63.79 0.4 63.79 0.4 64.05 1.78 64.05 1.78 65.15 0.4 65.15 0.4 65.41 1.78 65.41 1.78 66.51 0.4 66.51 0.4 66.77 1.78 66.77 1.78 67.87 0.4 67.87 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 78.33 1.78 78.33 1.78 79.43 0.4 79.43 0.4 79.69 1.78 79.69 1.78 80.79 0.4 80.79 0.4 81.05 1.78 81.05 1.78 82.15 0.4 82.15 0.4 82.41 1.78 82.41 1.78 83.51 0.4 83.51 0.4 83.77 1.78 83.77 1.78 84.87 0.4 84.87 0.4 85.13 1.78 85.13 1.78 86.23 0.4 86.23 0.4 86.49 1.78 86.49 1.78 87.59 0.4 87.59 0.4 87.85 1.78 87.85 1.78 88.95 0.4 88.95 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 90.57 1.78 90.57 1.78 91.67 0.4 91.67 0.4 97.52 28 97.52 28 108.4 ; + LAYER met2 ; + RECT 83.58 108.615 83.86 108.985 ; + RECT 54.14 108.615 54.42 108.985 ; + RECT 79.45 106.94 79.71 107.26 ; + RECT 70.25 106.94 70.51 107.26 ; + RECT 60.59 106.94 60.85 107.26 ; + RECT 51.39 106.94 51.65 107.26 ; + RECT 40.35 106.94 40.61 107.26 ; + RECT 9.98 97.735 10.26 98.105 ; + RECT 12.29 96.06 12.55 96.38 ; + RECT 9.98 10.695 10.26 11.065 ; + RECT 84.97 1.54 85.23 1.86 ; + RECT 47.25 1.54 47.51 1.86 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + POLYGON 95.4 108.52 95.4 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 2.65 11.16 2.65 12.52 1.95 12.52 1.95 11.16 0.28 11.16 0.28 97.64 1.95 97.64 1.95 96.28 2.65 96.28 2.65 97.64 5.17 97.64 5.17 96.28 5.87 96.28 5.87 97.64 6.09 97.64 6.09 96.28 6.79 96.28 6.79 97.64 7.01 97.64 7.01 96.28 7.71 96.28 7.71 97.64 7.93 97.64 7.93 96.28 8.63 96.28 8.63 97.64 10.69 97.64 10.69 96.28 11.39 96.28 11.39 97.64 11.61 97.64 11.61 96.28 12.31 96.28 12.31 97.64 12.53 97.64 12.53 96.28 13.23 96.28 13.23 97.64 17.59 97.64 17.59 96.28 18.29 96.28 18.29 97.64 27.88 97.64 27.88 108.52 35.07 108.52 35.07 107.16 35.77 107.16 35.77 108.52 36.91 108.52 36.91 107.16 37.61 107.16 37.61 108.52 37.83 108.52 37.83 107.16 38.53 107.16 38.53 108.52 38.75 108.52 38.75 107.16 39.45 107.16 39.45 108.52 39.67 108.52 39.67 107.16 40.37 107.16 40.37 108.52 40.59 108.52 40.59 107.16 41.29 107.16 41.29 108.52 41.51 108.52 41.51 107.16 42.21 107.16 42.21 108.52 42.43 108.52 42.43 107.16 43.13 107.16 43.13 108.52 43.35 108.52 43.35 107.16 44.05 107.16 44.05 108.52 44.27 108.52 44.27 107.16 44.97 107.16 44.97 108.52 45.19 108.52 45.19 107.16 45.89 107.16 45.89 108.52 46.11 108.52 46.11 107.16 46.81 107.16 46.81 108.52 47.03 108.52 47.03 107.16 47.73 107.16 47.73 108.52 47.95 108.52 47.95 107.16 48.65 107.16 48.65 108.52 48.87 108.52 48.87 107.16 49.57 107.16 49.57 108.52 49.79 108.52 49.79 107.16 50.49 107.16 50.49 108.52 50.71 108.52 50.71 107.16 51.41 107.16 51.41 108.52 51.63 108.52 51.63 107.16 52.33 107.16 52.33 108.52 53.01 108.52 53.01 107.16 53.71 107.16 53.71 108.52 54.85 108.52 54.85 107.16 55.55 107.16 55.55 108.52 57.15 108.52 57.15 107.16 57.85 107.16 57.85 108.52 58.07 108.52 58.07 107.16 58.77 107.16 58.77 108.52 58.99 108.52 58.99 107.16 59.69 107.16 59.69 108.52 59.91 108.52 59.91 107.16 60.61 107.16 60.61 108.52 60.83 108.52 60.83 107.16 61.53 107.16 61.53 108.52 61.75 108.52 61.75 107.16 62.45 107.16 62.45 108.52 63.13 108.52 63.13 107.16 63.83 107.16 63.83 108.52 64.05 108.52 64.05 107.16 64.75 107.16 64.75 108.52 64.97 108.52 64.97 107.16 65.67 107.16 65.67 108.52 65.89 108.52 65.89 107.16 66.59 107.16 66.59 108.52 66.81 108.52 66.81 107.16 67.51 107.16 67.51 108.52 67.73 108.52 67.73 107.16 68.43 107.16 68.43 108.52 70.49 108.52 70.49 107.16 71.19 107.16 71.19 108.52 76.93 108.52 76.93 107.16 77.63 107.16 77.63 108.52 77.85 108.52 77.85 107.16 78.55 107.16 78.55 108.52 78.77 108.52 78.77 107.16 79.47 107.16 79.47 108.52 79.69 108.52 79.69 107.16 80.39 107.16 80.39 108.52 80.61 108.52 80.61 107.16 81.31 107.16 81.31 108.52 ; + LAYER met4 ; + POLYGON 95.28 108.4 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 28 97.52 28 108.4 38.86 108.4 38.86 107.8 40.26 107.8 40.26 108.4 43.61 108.4 43.61 107.04 44.71 107.04 44.71 108.4 45.45 108.4 45.45 107.04 46.55 107.04 46.55 108.4 53.58 108.4 53.58 107.8 54.98 107.8 54.98 108.4 61.09 108.4 61.09 107.04 62.19 107.04 62.19 108.4 62.93 108.4 62.93 107.04 64.03 107.04 64.03 108.4 68.3 108.4 68.3 107.8 69.7 107.8 69.7 108.4 83.02 108.4 83.02 107.8 84.42 107.8 84.42 108.4 ; LAYER met5 ; - POLYGON 83.04 96.32 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 20 80 20 96.32 ; + POLYGON 94.08 107.2 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 29.2 96.32 29.2 107.2 ; LAYER met1 ; - POLYGON 84.36 97.4 84.36 95.72 83.88 95.72 83.88 94.68 84.36 94.68 84.36 93 83.88 93 83.88 91.96 84.36 91.96 84.36 90.28 83.88 90.28 83.88 89.24 84.36 89.24 84.36 87.56 83.88 87.56 83.88 86.52 84.36 86.52 84.36 84.84 83.88 84.84 83.88 83.8 84.36 83.8 84.36 82.12 18.68 82.12 18.68 83.8 19.16 83.8 19.16 84.84 18.68 84.84 18.68 86.52 19.16 86.52 19.16 87.56 18.68 87.56 18.68 89.24 19.16 89.24 19.16 90.28 18.68 90.28 18.68 91.96 19.16 91.96 19.16 93 18.68 93 18.68 94.68 19.16 94.68 19.16 95.72 18.68 95.72 18.68 97.4 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; + POLYGON 95.4 108.28 95.4 106.6 94.92 106.6 94.92 105.56 95.4 105.56 95.4 103.88 94.92 103.88 94.92 102.84 95.4 102.84 95.4 101.16 94.92 101.16 94.92 100.12 95.4 100.12 95.4 98.44 27.88 98.44 27.88 100.12 28.36 100.12 28.36 101.16 27.88 101.16 27.88 102.84 28.36 102.84 28.36 103.88 27.88 103.88 27.88 105.56 28.36 105.56 28.36 106.6 27.88 106.6 27.88 108.28 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; LAYER li1 ; - POLYGON 84.47 97.75 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 18.57 81.43 18.57 97.75 ; + POLYGON 95.51 108.63 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 27.77 97.75 27.77 108.63 ; LAYER mcon ; + RECT 95.365 108.715 95.535 108.885 ; + RECT 94.905 108.715 95.075 108.885 ; + RECT 94.445 108.715 94.615 108.885 ; + RECT 93.985 108.715 94.155 108.885 ; + RECT 93.525 108.715 93.695 108.885 ; + RECT 93.065 108.715 93.235 108.885 ; + RECT 92.605 108.715 92.775 108.885 ; + RECT 92.145 108.715 92.315 108.885 ; + RECT 91.685 108.715 91.855 108.885 ; + RECT 91.225 108.715 91.395 108.885 ; + RECT 90.765 108.715 90.935 108.885 ; + RECT 90.305 108.715 90.475 108.885 ; + RECT 89.845 108.715 90.015 108.885 ; + RECT 89.385 108.715 89.555 108.885 ; + RECT 88.925 108.715 89.095 108.885 ; + RECT 88.465 108.715 88.635 108.885 ; + RECT 88.005 108.715 88.175 108.885 ; + RECT 87.545 108.715 87.715 108.885 ; + RECT 87.085 108.715 87.255 108.885 ; + RECT 86.625 108.715 86.795 108.885 ; + RECT 86.165 108.715 86.335 108.885 ; + RECT 85.705 108.715 85.875 108.885 ; + RECT 85.245 108.715 85.415 108.885 ; + RECT 84.785 108.715 84.955 108.885 ; + RECT 84.325 108.715 84.495 108.885 ; + RECT 83.865 108.715 84.035 108.885 ; + RECT 83.405 108.715 83.575 108.885 ; + RECT 82.945 108.715 83.115 108.885 ; + RECT 82.485 108.715 82.655 108.885 ; + RECT 82.025 108.715 82.195 108.885 ; + RECT 81.565 108.715 81.735 108.885 ; + RECT 81.105 108.715 81.275 108.885 ; + RECT 80.645 108.715 80.815 108.885 ; + RECT 80.185 108.715 80.355 108.885 ; + RECT 79.725 108.715 79.895 108.885 ; + RECT 79.265 108.715 79.435 108.885 ; + RECT 78.805 108.715 78.975 108.885 ; + RECT 78.345 108.715 78.515 108.885 ; + RECT 77.885 108.715 78.055 108.885 ; + RECT 77.425 108.715 77.595 108.885 ; + RECT 76.965 108.715 77.135 108.885 ; + RECT 76.505 108.715 76.675 108.885 ; + RECT 76.045 108.715 76.215 108.885 ; + RECT 75.585 108.715 75.755 108.885 ; + RECT 75.125 108.715 75.295 108.885 ; + RECT 74.665 108.715 74.835 108.885 ; + RECT 74.205 108.715 74.375 108.885 ; + RECT 73.745 108.715 73.915 108.885 ; + RECT 73.285 108.715 73.455 108.885 ; + RECT 72.825 108.715 72.995 108.885 ; + RECT 72.365 108.715 72.535 108.885 ; + RECT 71.905 108.715 72.075 108.885 ; + RECT 71.445 108.715 71.615 108.885 ; + RECT 70.985 108.715 71.155 108.885 ; + RECT 70.525 108.715 70.695 108.885 ; + RECT 70.065 108.715 70.235 108.885 ; + RECT 69.605 108.715 69.775 108.885 ; + RECT 69.145 108.715 69.315 108.885 ; + RECT 68.685 108.715 68.855 108.885 ; + RECT 68.225 108.715 68.395 108.885 ; + RECT 67.765 108.715 67.935 108.885 ; + RECT 67.305 108.715 67.475 108.885 ; + RECT 66.845 108.715 67.015 108.885 ; + RECT 66.385 108.715 66.555 108.885 ; + RECT 65.925 108.715 66.095 108.885 ; + RECT 65.465 108.715 65.635 108.885 ; + RECT 65.005 108.715 65.175 108.885 ; + RECT 64.545 108.715 64.715 108.885 ; + RECT 64.085 108.715 64.255 108.885 ; + RECT 63.625 108.715 63.795 108.885 ; + RECT 63.165 108.715 63.335 108.885 ; + RECT 62.705 108.715 62.875 108.885 ; + RECT 62.245 108.715 62.415 108.885 ; + RECT 61.785 108.715 61.955 108.885 ; + RECT 61.325 108.715 61.495 108.885 ; + RECT 60.865 108.715 61.035 108.885 ; + RECT 60.405 108.715 60.575 108.885 ; + RECT 59.945 108.715 60.115 108.885 ; + RECT 59.485 108.715 59.655 108.885 ; + RECT 59.025 108.715 59.195 108.885 ; + RECT 58.565 108.715 58.735 108.885 ; + RECT 58.105 108.715 58.275 108.885 ; + RECT 57.645 108.715 57.815 108.885 ; + RECT 57.185 108.715 57.355 108.885 ; + RECT 56.725 108.715 56.895 108.885 ; + RECT 56.265 108.715 56.435 108.885 ; + RECT 55.805 108.715 55.975 108.885 ; + RECT 55.345 108.715 55.515 108.885 ; + RECT 54.885 108.715 55.055 108.885 ; + RECT 54.425 108.715 54.595 108.885 ; + RECT 53.965 108.715 54.135 108.885 ; + RECT 53.505 108.715 53.675 108.885 ; + RECT 53.045 108.715 53.215 108.885 ; + RECT 52.585 108.715 52.755 108.885 ; + RECT 52.125 108.715 52.295 108.885 ; + RECT 51.665 108.715 51.835 108.885 ; + RECT 51.205 108.715 51.375 108.885 ; + RECT 50.745 108.715 50.915 108.885 ; + RECT 50.285 108.715 50.455 108.885 ; + RECT 49.825 108.715 49.995 108.885 ; + RECT 49.365 108.715 49.535 108.885 ; + RECT 48.905 108.715 49.075 108.885 ; + RECT 48.445 108.715 48.615 108.885 ; + RECT 47.985 108.715 48.155 108.885 ; + RECT 47.525 108.715 47.695 108.885 ; + RECT 47.065 108.715 47.235 108.885 ; + RECT 46.605 108.715 46.775 108.885 ; + RECT 46.145 108.715 46.315 108.885 ; + RECT 45.685 108.715 45.855 108.885 ; + RECT 45.225 108.715 45.395 108.885 ; + RECT 44.765 108.715 44.935 108.885 ; + RECT 44.305 108.715 44.475 108.885 ; + RECT 43.845 108.715 44.015 108.885 ; + RECT 43.385 108.715 43.555 108.885 ; + RECT 42.925 108.715 43.095 108.885 ; + RECT 42.465 108.715 42.635 108.885 ; + RECT 42.005 108.715 42.175 108.885 ; + RECT 41.545 108.715 41.715 108.885 ; + RECT 41.085 108.715 41.255 108.885 ; + RECT 40.625 108.715 40.795 108.885 ; + RECT 40.165 108.715 40.335 108.885 ; + RECT 39.705 108.715 39.875 108.885 ; + RECT 39.245 108.715 39.415 108.885 ; + RECT 38.785 108.715 38.955 108.885 ; + RECT 38.325 108.715 38.495 108.885 ; + RECT 37.865 108.715 38.035 108.885 ; + RECT 37.405 108.715 37.575 108.885 ; + RECT 36.945 108.715 37.115 108.885 ; + RECT 36.485 108.715 36.655 108.885 ; + RECT 36.025 108.715 36.195 108.885 ; + RECT 35.565 108.715 35.735 108.885 ; + RECT 35.105 108.715 35.275 108.885 ; + RECT 34.645 108.715 34.815 108.885 ; + RECT 34.185 108.715 34.355 108.885 ; + RECT 33.725 108.715 33.895 108.885 ; + RECT 33.265 108.715 33.435 108.885 ; + RECT 32.805 108.715 32.975 108.885 ; + RECT 32.345 108.715 32.515 108.885 ; + RECT 31.885 108.715 32.055 108.885 ; + RECT 31.425 108.715 31.595 108.885 ; + RECT 30.965 108.715 31.135 108.885 ; + RECT 30.505 108.715 30.675 108.885 ; + RECT 30.045 108.715 30.215 108.885 ; + RECT 29.585 108.715 29.755 108.885 ; + RECT 29.125 108.715 29.295 108.885 ; + RECT 28.665 108.715 28.835 108.885 ; + RECT 28.205 108.715 28.375 108.885 ; + RECT 27.745 108.715 27.915 108.885 ; + RECT 95.365 105.995 95.535 106.165 ; + RECT 94.905 105.995 95.075 106.165 ; + RECT 28.205 105.995 28.375 106.165 ; + RECT 27.745 105.995 27.915 106.165 ; + RECT 95.365 103.275 95.535 103.445 ; + RECT 94.905 103.275 95.075 103.445 ; + RECT 28.205 103.275 28.375 103.445 ; + RECT 27.745 103.275 27.915 103.445 ; + RECT 95.365 100.555 95.535 100.725 ; + RECT 94.905 100.555 95.075 100.725 ; + RECT 28.205 100.555 28.375 100.725 ; + RECT 27.745 100.555 27.915 100.725 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; RECT 84.325 97.835 84.495 98.005 ; RECT 83.865 97.835 84.035 98.005 ; RECT 83.405 97.835 83.575 98.005 ; @@ -1900,506 +2129,414 @@ MACRO sb_2__1_ RECT 19.465 97.835 19.635 98.005 ; RECT 19.005 97.835 19.175 98.005 ; RECT 18.545 97.835 18.715 98.005 ; - RECT 84.325 95.115 84.495 95.285 ; - RECT 83.865 95.115 84.035 95.285 ; - RECT 19.005 95.115 19.175 95.285 ; - RECT 18.545 95.115 18.715 95.285 ; - RECT 84.325 92.395 84.495 92.565 ; - RECT 83.865 92.395 84.035 92.565 ; - RECT 19.005 92.395 19.175 92.565 ; - RECT 18.545 92.395 18.715 92.565 ; - RECT 84.325 89.675 84.495 89.845 ; - RECT 83.865 89.675 84.035 89.845 ; - RECT 19.005 89.675 19.175 89.845 ; - RECT 18.545 89.675 18.715 89.845 ; - RECT 84.325 86.955 84.495 87.125 ; - RECT 83.865 86.955 84.035 87.125 ; - RECT 19.005 86.955 19.175 87.125 ; - RECT 18.545 86.955 18.715 87.125 ; - RECT 84.325 84.235 84.495 84.405 ; - RECT 83.865 84.235 84.035 84.405 ; - RECT 19.005 84.235 19.175 84.405 ; - RECT 18.545 84.235 18.715 84.405 ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; - RECT 19.005 13.515 19.175 13.685 ; - RECT 18.545 13.515 18.715 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; RECT 84.325 10.795 84.495 10.965 ; RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; RECT 19.005 10.795 19.175 10.965 ; RECT 18.545 10.795 18.715 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; - RECT 19.005 8.075 19.175 8.245 ; - RECT 18.545 8.075 18.715 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; - RECT 19.005 5.355 19.175 5.525 ; - RECT 18.545 5.355 18.715 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; - RECT 19.005 2.635 19.175 2.805 ; - RECT 18.545 2.635 18.715 2.805 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; + RECT 28.205 8.075 28.375 8.245 ; + RECT 27.745 8.075 27.915 8.245 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; + RECT 28.205 5.355 28.375 5.525 ; + RECT 27.745 5.355 27.915 5.525 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; + RECT 28.205 2.635 28.375 2.805 ; + RECT 27.745 2.635 27.915 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -2524,60 +2661,44 @@ MACRO sb_2__1_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; LAYER via ; - RECT 73.525 97.845 73.675 97.995 ; - RECT 44.085 97.845 44.235 97.995 ; - RECT 59.265 96.145 59.415 96.295 ; - RECT 40.865 96.145 41.015 96.295 ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 13.265 79.825 13.415 79.975 ; - RECT 5.445 17.945 5.595 18.095 ; - RECT 73.525 16.245 73.675 16.395 ; - RECT 44.085 16.245 44.235 16.395 ; - RECT 37.645 1.625 37.795 1.775 ; - RECT 24.765 1.625 24.915 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 83.645 108.725 83.795 108.875 ; + RECT 54.205 108.725 54.355 108.875 ; + RECT 77.205 107.025 77.355 107.175 ; + RECT 67.085 107.025 67.235 107.175 ; + RECT 44.545 107.025 44.695 107.175 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 10.045 97.845 10.195 97.995 ; + RECT 15.105 12.505 15.255 12.655 ; + RECT 83.645 10.805 83.795 10.955 ; + RECT 54.205 10.805 54.355 10.955 ; + RECT 10.045 10.805 10.195 10.955 ; + RECT 78.125 1.625 78.275 1.775 ; + RECT 66.165 1.625 66.315 1.775 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; LAYER via2 ; - RECT 73.5 97.82 73.7 98.02 ; - RECT 44.06 97.82 44.26 98.02 ; - RECT 1.28 73.34 1.48 73.54 ; - RECT 1.74 61.1 1.94 61.3 ; - RECT 1.74 46.82 1.94 47.02 ; - RECT 1.28 25.06 1.48 25.26 ; - RECT 19.68 5.34 19.88 5.54 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 108.7 83.82 108.9 ; + RECT 54.18 108.7 54.38 108.9 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.28 89.66 1.48 89.86 ; + RECT 1.74 84.22 1.94 84.42 ; + RECT 1.28 82.86 1.48 83.06 ; + RECT 1.28 77.42 1.48 77.62 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER via3 ; - RECT 73.5 97.82 73.7 98.02 ; - RECT 44.06 97.82 44.26 98.02 ; - RECT 1.74 30.5 1.94 30.7 ; - RECT 1.74 26.42 1.94 26.62 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 108.7 83.82 108.9 ; + RECT 54.18 108.7 54.38 108.9 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.74 74.7 1.94 74.9 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER OVERLAP ; - POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 18.4 81.6 18.4 97.92 84.64 97.92 84.64 0 ; + POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 27.6 97.92 27.6 108.8 95.68 108.8 95.68 0 ; END END sb_2__1_ diff --git a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef index f57ed33..be19040 100644 --- a/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef +++ b/FPGA22_HIER_SKY_PNR/modules/lef/sb_2__2__icv_in_design.lef @@ -356,22 +356,22 @@ END unithddbl MACRO sb_2__2_ CLASS BLOCK ; ORIGIN 0 0 ; - SIZE 84.64 BY 81.6 ; + SIZE 95.68 BY 97.92 ; SYMMETRY X Y ; PIN prog_clk[0] DIRECTION INPUT ; USE CLOCK ; PORT LAYER met2 ; - RECT 2.23 16.32 2.37 17.68 ; + RECT 30.75 0 30.89 1.36 ; END END prog_clk[0] PIN chany_bottom_in[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 41.33 0 41.47 1.36 ; + LAYER met4 ; + RECT 52.29 0 52.59 1.36 ; END END chany_bottom_in[0] PIN chany_bottom_in[1] @@ -379,15 +379,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 49.15 0 49.29 1.36 ; + RECT 35.81 0 35.95 1.36 ; END END chany_bottom_in[1] PIN chany_bottom_in[2] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 50.99 0 51.13 1.36 ; + LAYER met4 ; + RECT 50.45 0 50.75 1.36 ; END END chany_bottom_in[2] PIN chany_bottom_in[3] @@ -395,7 +395,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 42.25 0 42.39 1.36 ; + RECT 49.61 0 49.75 1.36 ; END END chany_bottom_in[3] PIN chany_bottom_in[4] @@ -403,7 +403,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.01 0 22.15 1.36 ; + RECT 37.65 0 37.79 1.36 ; END END chany_bottom_in[4] PIN chany_bottom_in[5] @@ -411,7 +411,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 38.57 0 38.71 1.36 ; + RECT 52.37 0 52.51 1.36 ; END END chany_bottom_in[5] PIN chany_bottom_in[6] @@ -419,7 +419,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 39.49 0 39.63 1.36 ; + RECT 67.09 0 67.23 1.36 ; END END chany_bottom_in[6] PIN chany_bottom_in[7] @@ -427,7 +427,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 62.95 0 63.09 1.36 ; + RECT 79.97 0 80.11 1.36 ; END END chany_bottom_in[7] PIN chany_bottom_in[8] @@ -435,7 +435,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 61.57 0 61.71 1.36 ; + RECT 84.57 0 84.71 1.36 ; END END chany_bottom_in[8] PIN chany_bottom_in[9] @@ -443,7 +443,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 64.79 0 64.93 1.36 ; + RECT 65.25 0 65.39 1.36 ; END END chany_bottom_in[9] PIN chany_bottom_in[10] @@ -451,7 +451,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 36.73 0 36.87 1.36 ; + RECT 33.51 0 33.65 1.36 ; END END chany_bottom_in[10] PIN chany_bottom_in[11] @@ -459,7 +459,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 57.43 0 57.57 1.36 ; + RECT 56.51 0 56.65 1.36 ; END END chany_bottom_in[11] PIN chany_bottom_in[12] @@ -467,7 +467,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 40.41 0 40.55 1.36 ; + RECT 51.45 0 51.59 1.36 ; END END chany_bottom_in[12] PIN chany_bottom_in[13] @@ -475,7 +475,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 31.21 0 31.35 1.36 ; + RECT 62.03 0 62.17 1.36 ; END END chany_bottom_in[13] PIN chany_bottom_in[14] @@ -483,7 +483,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 51.91 0 52.05 1.36 ; + RECT 68.01 0 68.15 1.36 ; END END chany_bottom_in[14] PIN chany_bottom_in[15] @@ -491,7 +491,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 59.73 0 59.87 1.36 ; + RECT 71.69 0 71.83 1.36 ; END END chany_bottom_in[15] PIN chany_bottom_in[16] @@ -499,7 +499,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 58.35 0 58.49 1.36 ; + RECT 57.43 0 57.57 1.36 ; END END chany_bottom_in[16] PIN chany_bottom_in[17] @@ -507,7 +507,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 60.65 0 60.79 1.36 ; + RECT 81.81 0 81.95 1.36 ; END END chany_bottom_in[17] PIN chany_bottom_in[18] @@ -515,7 +515,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 63.87 0 64.01 1.36 ; + RECT 82.73 0 82.87 1.36 ; END END chany_bottom_in[18] PIN chany_bottom_in[19] @@ -523,7 +523,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 56.51 0 56.65 1.36 ; + RECT 80.89 0 81.03 1.36 ; END END chany_bottom_in[19] PIN bottom_right_grid_pin_1_[0] @@ -531,7 +531,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 25.69 0 25.83 1.36 ; + RECT 42.25 0 42.39 1.36 ; END END bottom_right_grid_pin_1_[0] PIN bottom_left_grid_pin_42_[0] @@ -539,63 +539,63 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 3.61 16.32 3.75 17.68 ; + RECT 11.43 10.88 11.57 12.24 ; END END bottom_left_grid_pin_42_[0] PIN bottom_left_grid_pin_43_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 22.85 0 23.15 1.36 ; + LAYER met2 ; + RECT 9.13 10.88 9.27 12.24 ; END END bottom_left_grid_pin_43_[0] PIN bottom_left_grid_pin_44_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 8.01 19.78 8.31 ; + LAYER met2 ; + RECT 12.35 10.88 12.49 12.24 ; END END bottom_left_grid_pin_44_[0] PIN bottom_left_grid_pin_45_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 10.73 19.78 11.03 ; + LAYER met2 ; + RECT 14.19 10.88 14.33 12.24 ; END END bottom_left_grid_pin_45_[0] PIN bottom_left_grid_pin_46_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 6.65 19.78 6.95 ; + LAYER met2 ; + RECT 16.03 10.88 16.17 12.24 ; END END bottom_left_grid_pin_46_[0] PIN bottom_left_grid_pin_47_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 9.37 19.78 9.67 ; + LAYER met2 ; + RECT 17.87 10.88 18.01 12.24 ; END END bottom_left_grid_pin_47_[0] PIN bottom_left_grid_pin_48_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 5.29 19.78 5.59 ; + LAYER met4 ; + RECT 5.37 10.88 5.67 12.24 ; END END bottom_left_grid_pin_48_[0] PIN bottom_left_grid_pin_49_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 6.37 16.32 6.51 17.68 ; + LAYER met4 ; + RECT 11.81 10.88 12.11 12.24 ; END END bottom_left_grid_pin_49_[0] PIN chanx_left_in[0] @@ -603,7 +603,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 27.05 1.38 27.35 ; + RECT 0 44.73 1.38 45.03 ; END END chanx_left_in[0] PIN chanx_left_in[1] @@ -611,7 +611,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 67.85 1.38 68.15 ; + RECT 0 61.05 1.38 61.35 ; END END chanx_left_in[1] PIN chanx_left_in[2] @@ -619,7 +619,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 70.57 1.38 70.87 ; + RECT 0 39.97 1.38 40.27 ; END END chanx_left_in[2] PIN chanx_left_in[3] @@ -627,7 +627,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 69.21 1.38 69.51 ; + RECT 0 23.65 1.38 23.95 ; END END chanx_left_in[3] PIN chanx_left_in[4] @@ -635,7 +635,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 37.93 1.38 38.23 ; + RECT 0 29.09 1.38 29.39 ; END END chanx_left_in[4] PIN chanx_left_in[5] @@ -643,7 +643,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 22.97 1.38 23.27 ; + RECT 0 25.01 1.38 25.31 ; END END chanx_left_in[5] PIN chanx_left_in[6] @@ -651,7 +651,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 65.13 1.38 65.43 ; + RECT 0 41.33 1.38 41.63 ; END END chanx_left_in[6] PIN chanx_left_in[7] @@ -659,7 +659,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 25.69 1.38 25.99 ; + RECT 0 35.89 1.38 36.19 ; END END chanx_left_in[7] PIN chanx_left_in[8] @@ -667,7 +667,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 46.09 1.38 46.39 ; + RECT 0 33.17 1.38 33.47 ; END END chanx_left_in[8] PIN chanx_left_in[9] @@ -675,7 +675,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 60.37 1.38 60.67 ; + RECT 0 65.13 1.38 65.43 ; END END chanx_left_in[9] PIN chanx_left_in[10] @@ -683,7 +683,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 63.77 1.38 64.07 ; + RECT 0 47.45 1.38 47.75 ; END END chanx_left_in[10] PIN chanx_left_in[11] @@ -691,7 +691,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 36.57 1.38 36.87 ; + RECT 0 20.25 1.38 20.55 ; END END chanx_left_in[11] PIN chanx_left_in[12] @@ -699,7 +699,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 29.77 1.38 30.07 ; + RECT 0 17.53 1.38 17.83 ; END END chanx_left_in[12] PIN chanx_left_in[13] @@ -707,7 +707,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 20.25 1.38 20.55 ; + RECT 0 22.29 1.38 22.59 ; END END chanx_left_in[13] PIN chanx_left_in[14] @@ -715,7 +715,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 77.37 1.38 77.67 ; + RECT 0 18.89 1.38 19.19 ; END END chanx_left_in[14] PIN chanx_left_in[15] @@ -723,7 +723,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 76.01 1.38 76.31 ; + RECT 0 34.53 1.38 34.83 ; END END chanx_left_in[15] PIN chanx_left_in[16] @@ -731,7 +731,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 59.01 1.38 59.31 ; + RECT 0 58.33 1.38 58.63 ; END END chanx_left_in[16] PIN chanx_left_in[17] @@ -739,7 +739,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 52.21 1.38 52.51 ; + RECT 0 63.77 1.38 64.07 ; END END chanx_left_in[17] PIN chanx_left_in[18] @@ -747,7 +747,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 40.65 1.38 40.95 ; + RECT 0 56.97 1.38 57.27 ; END END chanx_left_in[18] PIN chanx_left_in[19] @@ -755,7 +755,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 24.33 1.38 24.63 ; + RECT 0 38.61 1.38 38.91 ; END END chanx_left_in[19] PIN left_top_grid_pin_1_[0] @@ -763,23 +763,23 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 62.41 1.38 62.71 ; + RECT 0 55.61 1.38 55.91 ; END END left_top_grid_pin_1_[0] PIN left_bottom_grid_pin_34_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 6.29 16.32 6.59 17.68 ; + LAYER met2 ; + RECT 15.11 10.88 15.25 12.24 ; END END left_bottom_grid_pin_34_[0] PIN left_bottom_grid_pin_35_[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met3 ; - RECT 18.4 12.09 19.78 12.39 ; + LAYER met2 ; + RECT 13.27 10.88 13.41 12.24 ; END END left_bottom_grid_pin_35_[0] PIN left_bottom_grid_pin_36_[0] @@ -787,7 +787,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 8.67 16.32 8.81 17.68 ; + RECT 4.99 10.88 5.13 12.24 ; END END left_bottom_grid_pin_36_[0] PIN left_bottom_grid_pin_37_[0] @@ -795,7 +795,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 5.45 16.32 5.59 17.68 ; + RECT 5.91 10.88 6.05 12.24 ; END END left_bottom_grid_pin_37_[0] PIN left_bottom_grid_pin_38_[0] @@ -803,7 +803,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 20.63 0 20.77 1.36 ; + RECT 7.75 10.88 7.89 12.24 ; END END left_bottom_grid_pin_38_[0] PIN left_bottom_grid_pin_39_[0] @@ -811,7 +811,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 9.59 16.32 9.73 17.68 ; + RECT 4.07 10.88 4.21 12.24 ; END END left_bottom_grid_pin_39_[0] PIN left_bottom_grid_pin_40_[0] @@ -819,7 +819,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 10.97 16.32 11.11 17.68 ; + RECT 3.15 10.88 3.29 12.24 ; END END left_bottom_grid_pin_40_[0] PIN left_bottom_grid_pin_41_[0] @@ -827,15 +827,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 7.75 16.32 7.89 17.68 ; + RECT 6.83 10.88 6.97 12.24 ; END END left_bottom_grid_pin_41_[0] PIN ccff_head[0] DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 2.23 80.24 2.37 81.6 ; + LAYER met3 ; + RECT 94.3 61.05 95.68 61.35 ; END END ccff_head[0] PIN chany_bottom_out[0] @@ -843,7 +843,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 32.13 0 32.27 1.36 ; + RECT 55.13 0 55.27 1.36 ; END END chany_bottom_out[0] PIN chany_bottom_out[1] @@ -859,7 +859,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 78.13 0 78.27 1.36 ; + RECT 77.21 0 77.35 1.36 ; END END chany_bottom_out[2] PIN chany_bottom_out[3] @@ -867,7 +867,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 37.65 0 37.79 1.36 ; + RECT 39.49 0 39.63 1.36 ; END END chany_bottom_out[3] PIN chany_bottom_out[4] @@ -875,7 +875,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 29.37 0 29.51 1.36 ; + RECT 41.33 0 41.47 1.36 ; END END chany_bottom_out[4] PIN chany_bottom_out[5] @@ -883,7 +883,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 22.93 0 23.07 1.36 ; + RECT 38.57 0 38.71 1.36 ; END END chany_bottom_out[5] PIN chany_bottom_out[6] @@ -891,7 +891,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 23.85 0 23.99 1.36 ; + RECT 58.35 0 58.49 1.36 ; END END chany_bottom_out[6] PIN chany_bottom_out[7] @@ -899,7 +899,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 46.39 0 46.53 1.36 ; + RECT 48.69 0 48.83 1.36 ; END END chany_bottom_out[7] PIN chany_bottom_out[8] @@ -907,7 +907,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 43.17 0 43.31 1.36 ; + RECT 36.73 0 36.87 1.36 ; END END chany_bottom_out[8] PIN chany_bottom_out[9] @@ -915,7 +915,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 50.07 0 50.21 1.36 ; + RECT 34.89 0 35.03 1.36 ; END END chany_bottom_out[9] PIN chany_bottom_out[10] @@ -923,7 +923,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 34.43 0 34.57 1.36 ; + RECT 53.29 0 53.43 1.36 ; END END chany_bottom_out[10] PIN chany_bottom_out[11] @@ -931,7 +931,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 28.45 0 28.59 1.36 ; + RECT 47.77 0 47.91 1.36 ; END END chany_bottom_out[11] PIN chany_bottom_out[12] @@ -939,7 +939,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 26.61 0 26.75 1.36 ; + RECT 45.93 0 46.07 1.36 ; END END chany_bottom_out[12] PIN chany_bottom_out[13] @@ -947,7 +947,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 24.77 0 24.91 1.36 ; + RECT 40.41 0 40.55 1.36 ; END END chany_bottom_out[13] PIN chany_bottom_out[14] @@ -955,7 +955,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 30.29 0 30.43 1.36 ; + RECT 78.13 0 78.27 1.36 ; END END chany_bottom_out[14] PIN chany_bottom_out[15] @@ -963,7 +963,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 47.31 0 47.45 1.36 ; + RECT 66.17 0 66.31 1.36 ; END END chany_bottom_out[15] PIN chany_bottom_out[16] @@ -971,7 +971,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 27.53 0 27.67 1.36 ; + RECT 44.55 0 44.69 1.36 ; END END chany_bottom_out[16] PIN chany_bottom_out[17] @@ -979,7 +979,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 33.05 0 33.19 1.36 ; + RECT 50.53 0 50.67 1.36 ; END END chany_bottom_out[17] PIN chany_bottom_out[18] @@ -987,7 +987,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 48.23 0 48.37 1.36 ; + RECT 46.85 0 46.99 1.36 ; END END chany_bottom_out[18] PIN chany_bottom_out[19] @@ -995,7 +995,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met2 ; - RECT 45.47 0 45.61 1.36 ; + RECT 43.63 0 43.77 1.36 ; END END chany_bottom_out[19] PIN chanx_left_out[0] @@ -1003,7 +1003,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 57.65 1.38 57.95 ; + RECT 0 71.25 1.38 71.55 ; END END chanx_left_out[0] PIN chanx_left_out[1] @@ -1011,7 +1011,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 66.49 1.38 66.79 ; + RECT 0 89.61 1.38 89.91 ; END END chanx_left_out[1] PIN chanx_left_out[2] @@ -1019,7 +1019,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 55.61 1.38 55.91 ; + RECT 0 68.53 1.38 68.83 ; END END chanx_left_out[2] PIN chanx_left_out[3] @@ -1027,7 +1027,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 47.45 1.38 47.75 ; + RECT 0 51.53 1.38 51.83 ; END END chanx_left_out[3] PIN chanx_left_out[4] @@ -1035,7 +1035,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 50.85 1.38 51.15 ; + RECT 0 75.33 1.38 75.63 ; END END chanx_left_out[4] PIN chanx_left_out[5] @@ -1043,7 +1043,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 28.41 1.38 28.71 ; + RECT 0 46.09 1.38 46.39 ; END END chanx_left_out[5] PIN chanx_left_out[6] @@ -1051,7 +1051,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 43.37 1.38 43.67 ; + RECT 0 54.25 1.38 54.55 ; END END chanx_left_out[6] PIN chanx_left_out[7] @@ -1059,7 +1059,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 31.13 1.38 31.43 ; + RECT 0 50.17 1.38 50.47 ; END END chanx_left_out[7] PIN chanx_left_out[8] @@ -1067,15 +1067,15 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 73.29 1.38 73.59 ; + RECT 0 73.97 1.38 74.27 ; END END chanx_left_out[8] PIN chanx_left_out[9] DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met4 ; - RECT 4.45 16.32 4.75 17.68 ; + LAYER met3 ; + RECT 0 37.25 1.38 37.55 ; END END chanx_left_out[9] PIN chanx_left_out[10] @@ -1083,7 +1083,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 74.65 1.38 74.95 ; + RECT 0 72.61 1.38 72.91 ; END END chanx_left_out[10] PIN chanx_left_out[11] @@ -1091,7 +1091,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 35.21 1.38 35.51 ; + RECT 0 30.45 1.38 30.75 ; END END chanx_left_out[11] PIN chanx_left_out[12] @@ -1099,7 +1099,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 71.93 1.38 72.23 ; + RECT 0 69.89 1.38 70.19 ; END END chanx_left_out[12] PIN chanx_left_out[13] @@ -1107,7 +1107,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 53.57 1.38 53.87 ; + RECT 0 48.81 1.38 49.11 ; END END chanx_left_out[13] PIN chanx_left_out[14] @@ -1115,7 +1115,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 42.01 1.38 42.31 ; + RECT 0 52.89 1.38 53.19 ; END END chanx_left_out[14] PIN chanx_left_out[15] @@ -1123,7 +1123,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 48.81 1.38 49.11 ; + RECT 0 62.41 1.38 62.71 ; END END chanx_left_out[15] PIN chanx_left_out[16] @@ -1131,7 +1131,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 33.85 1.38 34.15 ; + RECT 0 43.37 1.38 43.67 ; END END chanx_left_out[16] PIN chanx_left_out[17] @@ -1139,7 +1139,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 32.49 1.38 32.79 ; + RECT 0 26.37 1.38 26.67 ; END END chanx_left_out[17] PIN chanx_left_out[18] @@ -1147,7 +1147,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 44.73 1.38 45.03 ; + RECT 0 59.69 1.38 59.99 ; END END chanx_left_out[18] PIN chanx_left_out[19] @@ -1155,7 +1155,7 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 39.29 1.38 39.59 ; + RECT 0 27.73 1.38 28.03 ; END END chanx_left_out[19] PIN ccff_tail[0] @@ -1163,39 +1163,39 @@ MACRO sb_2__2_ USE SIGNAL ; PORT LAYER met3 ; - RECT 0 21.61 1.38 21.91 ; + RECT 0 31.81 1.38 32.11 ; END END ccff_tail[0] PIN SC_IN_TOP DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 4.53 16.32 4.67 17.68 ; + LAYER met3 ; + RECT 0 14.13 1.38 14.43 ; END END SC_IN_TOP PIN SC_IN_BOT DIRECTION INPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 43.17 80.24 43.31 81.6 ; + LAYER met3 ; + RECT 0 76.69 1.38 76.99 ; END END SC_IN_BOT PIN SC_OUT_TOP DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 28.91 80.24 29.05 81.6 ; + LAYER met3 ; + RECT 94.3 33.17 95.68 33.47 ; END END SC_OUT_TOP PIN SC_OUT_BOT DIRECTION OUTPUT ; USE SIGNAL ; PORT - LAYER met2 ; - RECT 42.25 80.24 42.39 81.6 ; + LAYER met3 ; + RECT 0 66.49 1.38 66.79 ; END END SC_OUT_BOT PIN VDD @@ -1203,46 +1203,52 @@ MACRO sb_2__2_ USE POWER ; PORT LAYER met1 ; - RECT 18.4 2.48 18.88 2.96 ; - RECT 84.16 2.48 84.64 2.96 ; - RECT 18.4 7.92 18.88 8.4 ; - RECT 84.16 7.92 84.64 8.4 ; - RECT 18.4 13.36 18.88 13.84 ; - RECT 84.16 13.36 84.64 13.84 ; + RECT 27.6 2.48 28.08 2.96 ; + RECT 95.2 2.48 95.68 2.96 ; + RECT 27.6 7.92 28.08 8.4 ; + RECT 95.2 7.92 95.68 8.4 ; + RECT 0 13.36 0.48 13.84 ; + RECT 95.2 13.36 95.68 13.84 ; RECT 0 18.8 0.48 19.28 ; - RECT 84.16 18.8 84.64 19.28 ; + RECT 95.2 18.8 95.68 19.28 ; RECT 0 24.24 0.48 24.72 ; - RECT 84.16 24.24 84.64 24.72 ; + RECT 95.2 24.24 95.68 24.72 ; RECT 0 29.68 0.48 30.16 ; - RECT 84.16 29.68 84.64 30.16 ; + RECT 95.2 29.68 95.68 30.16 ; RECT 0 35.12 0.48 35.6 ; - RECT 84.16 35.12 84.64 35.6 ; + RECT 95.2 35.12 95.68 35.6 ; RECT 0 40.56 0.48 41.04 ; - RECT 84.16 40.56 84.64 41.04 ; + RECT 95.2 40.56 95.68 41.04 ; RECT 0 46 0.48 46.48 ; - RECT 84.16 46 84.64 46.48 ; + RECT 95.2 46 95.68 46.48 ; RECT 0 51.44 0.48 51.92 ; - RECT 84.16 51.44 84.64 51.92 ; + RECT 95.2 51.44 95.68 51.92 ; RECT 0 56.88 0.48 57.36 ; - RECT 84.16 56.88 84.64 57.36 ; + RECT 95.2 56.88 95.68 57.36 ; RECT 0 62.32 0.48 62.8 ; - RECT 84.16 62.32 84.64 62.8 ; + RECT 95.2 62.32 95.68 62.8 ; RECT 0 67.76 0.48 68.24 ; - RECT 84.16 67.76 84.64 68.24 ; + RECT 95.2 67.76 95.68 68.24 ; RECT 0 73.2 0.48 73.68 ; - RECT 84.16 73.2 84.64 73.68 ; + RECT 95.2 73.2 95.68 73.68 ; RECT 0 78.64 0.48 79.12 ; - RECT 84.16 78.64 84.64 79.12 ; + RECT 95.2 78.64 95.68 79.12 ; + RECT 0 84.08 0.48 84.56 ; + RECT 95.2 84.08 95.68 84.56 ; + RECT 0 89.52 0.48 90 ; + RECT 95.2 89.52 95.68 90 ; + RECT 0 94.96 0.48 95.44 ; + RECT 95.2 94.96 95.68 95.44 ; LAYER met4 ; - RECT 29.14 0 29.74 0.6 ; - RECT 58.58 0 59.18 0.6 ; - RECT 29.14 81 29.74 81.6 ; - RECT 58.58 81 59.18 81.6 ; + RECT 39.26 0 39.86 0.6 ; + RECT 68.7 0 69.3 0.6 ; + RECT 39.26 97.32 39.86 97.92 ; + RECT 68.7 97.32 69.3 97.92 ; LAYER met5 ; - RECT 0 26.96 3.2 30.16 ; - RECT 81.44 26.96 84.64 30.16 ; - RECT 0 67.76 3.2 70.96 ; - RECT 81.44 67.76 84.64 70.96 ; + RECT 0 22.2 3.2 25.4 ; + RECT 92.48 22.2 95.68 25.4 ; + RECT 0 63 3.2 66.2 ; + RECT 92.48 63 95.68 66.2 ; END END VDD PIN VSS @@ -1250,615 +1256,734 @@ MACRO sb_2__2_ USE GROUND ; PORT LAYER met1 ; - RECT 18.4 0 84.64 0.24 ; - RECT 18.4 5.2 18.88 5.68 ; - RECT 84.16 5.2 84.64 5.68 ; - RECT 18.4 10.64 18.88 11.12 ; - RECT 84.16 10.64 84.64 11.12 ; - RECT 0 16.08 84.64 16.56 ; + RECT 27.6 0 95.68 0.24 ; + RECT 27.6 5.2 28.08 5.68 ; + RECT 95.2 5.2 95.68 5.68 ; + RECT 0 10.64 95.68 11.12 ; + RECT 0 16.08 0.48 16.56 ; + RECT 95.2 16.08 95.68 16.56 ; RECT 0 21.52 0.48 22 ; - RECT 84.16 21.52 84.64 22 ; + RECT 95.2 21.52 95.68 22 ; RECT 0 26.96 0.48 27.44 ; - RECT 84.16 26.96 84.64 27.44 ; + RECT 95.2 26.96 95.68 27.44 ; RECT 0 32.4 0.48 32.88 ; - RECT 84.16 32.4 84.64 32.88 ; + RECT 95.2 32.4 95.68 32.88 ; RECT 0 37.84 0.48 38.32 ; - RECT 84.16 37.84 84.64 38.32 ; + RECT 95.2 37.84 95.68 38.32 ; RECT 0 43.28 0.48 43.76 ; - RECT 84.16 43.28 84.64 43.76 ; + RECT 95.2 43.28 95.68 43.76 ; RECT 0 48.72 0.48 49.2 ; - RECT 84.16 48.72 84.64 49.2 ; + RECT 95.2 48.72 95.68 49.2 ; RECT 0 54.16 0.48 54.64 ; - RECT 84.16 54.16 84.64 54.64 ; + RECT 95.2 54.16 95.68 54.64 ; RECT 0 59.6 0.48 60.08 ; - RECT 84.16 59.6 84.64 60.08 ; + RECT 95.2 59.6 95.68 60.08 ; RECT 0 65.04 0.48 65.52 ; - RECT 84.16 65.04 84.64 65.52 ; + RECT 95.2 65.04 95.68 65.52 ; RECT 0 70.48 0.48 70.96 ; - RECT 84.16 70.48 84.64 70.96 ; + RECT 95.2 70.48 95.68 70.96 ; RECT 0 75.92 0.48 76.4 ; - RECT 84.16 75.92 84.64 76.4 ; - RECT 0 81.36 84.64 81.6 ; + RECT 95.2 75.92 95.68 76.4 ; + RECT 0 81.36 0.48 81.84 ; + RECT 95.2 81.36 95.68 81.84 ; + RECT 0 86.8 0.48 87.28 ; + RECT 95.2 86.8 95.68 87.28 ; + RECT 0 92.24 0.48 92.72 ; + RECT 95.2 92.24 95.68 92.72 ; + RECT 0 97.68 95.68 97.92 ; LAYER met4 ; - RECT 43.86 0 44.46 0.6 ; - RECT 73.3 0 73.9 0.6 ; - RECT 43.86 81 44.46 81.6 ; - RECT 73.3 81 73.9 81.6 ; + RECT 53.98 0 54.58 0.6 ; + RECT 83.42 0 84.02 0.6 ; + RECT 9.82 10.88 10.42 11.48 ; + RECT 9.82 97.32 10.42 97.92 ; + RECT 53.98 97.32 54.58 97.92 ; + RECT 83.42 97.32 84.02 97.92 ; LAYER met5 ; - RECT 0 47.36 3.2 50.56 ; - RECT 81.44 47.36 84.64 50.56 ; + RECT 0 42.6 3.2 45.8 ; + RECT 92.48 42.6 95.68 45.8 ; + RECT 0 83.4 3.2 86.6 ; + RECT 92.48 83.4 95.68 86.6 ; END END VSS OBS LAYER li1 ; - RECT 0 81.515 84.64 81.685 ; - RECT 84.18 78.795 84.64 78.965 ; + RECT 0 97.835 95.68 98.005 ; + RECT 95.22 95.115 95.68 95.285 ; + RECT 0 95.115 3.68 95.285 ; + RECT 95.22 92.395 95.68 92.565 ; + RECT 0 92.395 3.68 92.565 ; + RECT 95.22 89.675 95.68 89.845 ; + RECT 0 89.675 3.68 89.845 ; + RECT 95.22 86.955 95.68 87.125 ; + RECT 0 86.955 3.68 87.125 ; + RECT 92 84.235 95.68 84.405 ; + RECT 0 84.235 3.68 84.405 ; + RECT 92 81.515 95.68 81.685 ; + RECT 0 81.515 3.68 81.685 ; + RECT 95.22 78.795 95.68 78.965 ; RECT 0 78.795 3.68 78.965 ; - RECT 80.96 76.075 84.64 76.245 ; + RECT 95.22 76.075 95.68 76.245 ; RECT 0 76.075 3.68 76.245 ; - RECT 80.96 73.355 84.64 73.525 ; - RECT 0 73.355 3.68 73.525 ; - RECT 82.8 70.635 84.64 70.805 ; - RECT 0 70.635 3.68 70.805 ; - RECT 82.8 67.915 84.64 68.085 ; - RECT 0 67.915 3.68 68.085 ; - RECT 84.18 65.195 84.64 65.365 ; + RECT 95.22 73.355 95.68 73.525 ; + RECT 0 73.355 1.84 73.525 ; + RECT 95.22 70.635 95.68 70.805 ; + RECT 0 70.635 1.84 70.805 ; + RECT 92 67.915 95.68 68.085 ; + RECT 0 67.915 1.84 68.085 ; + RECT 92 65.195 95.68 65.365 ; RECT 0 65.195 3.68 65.365 ; - RECT 82.8 62.475 84.64 62.645 ; + RECT 95.22 62.475 95.68 62.645 ; RECT 0 62.475 3.68 62.645 ; - RECT 82.8 59.755 84.64 59.925 ; - RECT 0 59.755 1.84 59.925 ; - RECT 84.18 57.035 84.64 57.205 ; - RECT 0 57.035 1.84 57.205 ; - RECT 84.18 54.315 84.64 54.485 ; + RECT 95.22 59.755 95.68 59.925 ; + RECT 0 59.755 3.68 59.925 ; + RECT 94.76 57.035 95.68 57.205 ; + RECT 0 57.035 3.68 57.205 ; + RECT 94.76 54.315 95.68 54.485 ; RECT 0 54.315 3.68 54.485 ; - RECT 83.72 51.595 84.64 51.765 ; + RECT 94.76 51.595 95.68 51.765 ; RECT 0 51.595 3.68 51.765 ; - RECT 83.72 48.875 84.64 49.045 ; - RECT 0 48.875 1.84 49.045 ; - RECT 80.96 46.155 84.64 46.325 ; - RECT 0 46.155 3.68 46.325 ; - RECT 80.96 43.435 84.64 43.605 ; + RECT 94.76 48.875 95.68 49.045 ; + RECT 0 48.875 3.68 49.045 ; + RECT 95.22 46.155 95.68 46.325 ; + RECT 0 46.155 1.84 46.325 ; + RECT 95.22 43.435 95.68 43.605 ; RECT 0 43.435 3.68 43.605 ; - RECT 80.96 40.715 84.64 40.885 ; + RECT 95.22 40.715 95.68 40.885 ; RECT 0 40.715 3.68 40.885 ; - RECT 83.72 37.995 84.64 38.165 ; - RECT 0 37.995 3.68 38.165 ; - RECT 80.96 35.275 84.64 35.445 ; + RECT 94.76 37.995 95.68 38.165 ; + RECT 0 37.995 1.84 38.165 ; + RECT 92 35.275 95.68 35.445 ; RECT 0 35.275 1.84 35.445 ; - RECT 80.96 32.555 84.64 32.725 ; + RECT 92 32.555 95.68 32.725 ; RECT 0 32.555 3.68 32.725 ; - RECT 83.72 29.835 84.64 30.005 ; + RECT 95.22 29.835 95.68 30.005 ; RECT 0 29.835 3.68 30.005 ; - RECT 84.18 27.115 84.64 27.285 ; - RECT 0 27.115 3.68 27.285 ; - RECT 84.18 24.395 84.64 24.565 ; - RECT 0 24.395 1.84 24.565 ; - RECT 83.72 21.675 84.64 21.845 ; - RECT 0 21.675 1.84 21.845 ; - RECT 80.96 18.955 84.64 19.125 ; + RECT 94.76 27.115 95.68 27.285 ; + RECT 0 27.115 1.84 27.285 ; + RECT 94.76 24.395 95.68 24.565 ; + RECT 0 24.395 3.68 24.565 ; + RECT 94.76 21.675 95.68 21.845 ; + RECT 0 21.675 3.68 21.845 ; + RECT 95.22 18.955 95.68 19.125 ; RECT 0 18.955 3.68 19.125 ; - RECT 80.96 16.235 84.64 16.405 ; - RECT 0 16.235 22.08 16.405 ; - RECT 84.18 13.515 84.64 13.685 ; - RECT 18.4 13.515 22.08 13.685 ; - RECT 80.96 10.795 84.64 10.965 ; - RECT 18.4 10.795 22.08 10.965 ; - RECT 80.96 8.075 84.64 8.245 ; - RECT 18.4 8.075 20.24 8.245 ; - RECT 80.96 5.355 84.64 5.525 ; - RECT 18.4 5.355 22.08 5.525 ; - RECT 80.96 2.635 84.64 2.805 ; - RECT 18.4 2.635 22.08 2.805 ; - RECT 18.4 -0.085 84.64 0.085 ; + RECT 95.22 16.235 95.68 16.405 ; + RECT 0 16.235 3.68 16.405 ; + RECT 94.76 13.515 95.68 13.685 ; + RECT 0 13.515 3.68 13.685 ; + RECT 94.76 10.795 95.68 10.965 ; + RECT 0 10.795 31.28 10.965 ; + RECT 94.76 8.075 95.68 8.245 ; + RECT 27.6 8.075 31.28 8.245 ; + RECT 94.76 5.355 95.68 5.525 ; + RECT 27.6 5.355 31.28 5.525 ; + RECT 95.22 2.635 95.68 2.805 ; + RECT 27.6 2.635 31.28 2.805 ; + RECT 27.6 -0.085 95.68 0.085 ; LAYER met2 ; - RECT 73.46 81.415 73.74 81.785 ; - RECT 44.02 81.415 44.3 81.785 ; - RECT 10.45 17.86 10.71 18.18 ; - RECT 52.31 1.54 52.57 1.86 ; - RECT 36.21 1.54 36.47 1.86 ; - RECT 21.49 1.54 21.75 1.86 ; - RECT 73.46 -0.185 73.74 0.185 ; - RECT 44.02 -0.185 44.3 0.185 ; - POLYGON 84.36 81.32 84.36 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 65.21 0.28 65.21 1.64 64.51 1.64 64.51 0.28 64.29 0.28 64.29 1.64 63.59 1.64 63.59 0.28 63.37 0.28 63.37 1.64 62.67 1.64 62.67 0.28 61.99 0.28 61.99 1.64 61.29 1.64 61.29 0.28 61.07 0.28 61.07 1.64 60.37 1.64 60.37 0.28 60.15 0.28 60.15 1.64 59.45 1.64 59.45 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 52.33 0.28 52.33 1.64 51.63 1.64 51.63 0.28 51.41 0.28 51.41 1.64 50.71 1.64 50.71 0.28 50.49 0.28 50.49 1.64 49.79 1.64 49.79 0.28 49.57 0.28 49.57 1.64 48.87 1.64 48.87 0.28 48.65 0.28 48.65 1.64 47.95 1.64 47.95 0.28 47.73 0.28 47.73 1.64 47.03 1.64 47.03 0.28 46.81 0.28 46.81 1.64 46.11 1.64 46.11 0.28 45.89 0.28 45.89 1.64 45.19 1.64 45.19 0.28 43.59 0.28 43.59 1.64 42.89 1.64 42.89 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 34.85 0.28 34.85 1.64 34.15 1.64 34.15 0.28 33.47 0.28 33.47 1.64 32.77 1.64 32.77 0.28 32.55 0.28 32.55 1.64 31.85 1.64 31.85 0.28 31.63 0.28 31.63 1.64 30.93 1.64 30.93 0.28 30.71 0.28 30.71 1.64 30.01 1.64 30.01 0.28 29.79 0.28 29.79 1.64 29.09 1.64 29.09 0.28 28.87 0.28 28.87 1.64 28.17 1.64 28.17 0.28 27.95 0.28 27.95 1.64 27.25 1.64 27.25 0.28 27.03 0.28 27.03 1.64 26.33 1.64 26.33 0.28 26.11 0.28 26.11 1.64 25.41 1.64 25.41 0.28 25.19 0.28 25.19 1.64 24.49 1.64 24.49 0.28 24.27 0.28 24.27 1.64 23.57 1.64 23.57 0.28 23.35 0.28 23.35 1.64 22.65 1.64 22.65 0.28 22.43 0.28 22.43 1.64 21.73 1.64 21.73 0.28 21.05 0.28 21.05 1.64 20.35 1.64 20.35 0.28 18.68 0.28 18.68 16.6 11.39 16.6 11.39 17.96 10.69 17.96 10.69 16.6 10.01 16.6 10.01 17.96 9.31 17.96 9.31 16.6 9.09 16.6 9.09 17.96 8.39 17.96 8.39 16.6 8.17 16.6 8.17 17.96 7.47 17.96 7.47 16.6 6.79 16.6 6.79 17.96 6.09 17.96 6.09 16.6 5.87 16.6 5.87 17.96 5.17 17.96 5.17 16.6 4.95 16.6 4.95 17.96 4.25 17.96 4.25 16.6 4.03 16.6 4.03 17.96 3.33 17.96 3.33 16.6 2.65 16.6 2.65 17.96 1.95 17.96 1.95 16.6 0.28 16.6 0.28 81.32 1.95 81.32 1.95 79.96 2.65 79.96 2.65 81.32 28.63 81.32 28.63 79.96 29.33 79.96 29.33 81.32 41.97 81.32 41.97 79.96 42.67 79.96 42.67 81.32 42.89 81.32 42.89 79.96 43.59 79.96 43.59 81.32 ; + RECT 83.58 97.735 83.86 98.105 ; + RECT 54.14 97.735 54.42 98.105 ; + RECT 9.98 97.735 10.26 98.105 ; + RECT 9.98 10.695 10.26 11.065 ; + RECT 68.41 1.54 68.67 1.86 ; + RECT 55.53 1.54 55.79 1.86 ; + RECT 83.58 -0.185 83.86 0.185 ; + RECT 54.14 -0.185 54.42 0.185 ; + POLYGON 95.4 97.64 95.4 0.28 84.99 0.28 84.99 1.64 84.29 1.64 84.29 0.28 83.15 0.28 83.15 1.64 82.45 1.64 82.45 0.28 82.23 0.28 82.23 1.64 81.53 1.64 81.53 0.28 81.31 0.28 81.31 1.64 80.61 1.64 80.61 0.28 80.39 0.28 80.39 1.64 79.69 1.64 79.69 0.28 79.47 0.28 79.47 1.64 78.77 1.64 78.77 0.28 78.55 0.28 78.55 1.64 77.85 1.64 77.85 0.28 77.63 0.28 77.63 1.64 76.93 1.64 76.93 0.28 72.11 0.28 72.11 1.64 71.41 1.64 71.41 0.28 68.43 0.28 68.43 1.64 67.73 1.64 67.73 0.28 67.51 0.28 67.51 1.64 66.81 1.64 66.81 0.28 66.59 0.28 66.59 1.64 65.89 1.64 65.89 0.28 65.67 0.28 65.67 1.64 64.97 1.64 64.97 0.28 62.45 0.28 62.45 1.64 61.75 1.64 61.75 0.28 58.77 0.28 58.77 1.64 58.07 1.64 58.07 0.28 57.85 0.28 57.85 1.64 57.15 1.64 57.15 0.28 56.93 0.28 56.93 1.64 56.23 1.64 56.23 0.28 55.55 0.28 55.55 1.64 54.85 1.64 54.85 0.28 53.71 0.28 53.71 1.64 53.01 1.64 53.01 0.28 52.79 0.28 52.79 1.64 52.09 1.64 52.09 0.28 51.87 0.28 51.87 1.64 51.17 1.64 51.17 0.28 50.95 0.28 50.95 1.64 50.25 1.64 50.25 0.28 50.03 0.28 50.03 1.64 49.33 1.64 49.33 0.28 49.11 0.28 49.11 1.64 48.41 1.64 48.41 0.28 48.19 0.28 48.19 1.64 47.49 1.64 47.49 0.28 47.27 0.28 47.27 1.64 46.57 1.64 46.57 0.28 46.35 0.28 46.35 1.64 45.65 1.64 45.65 0.28 44.97 0.28 44.97 1.64 44.27 1.64 44.27 0.28 44.05 0.28 44.05 1.64 43.35 1.64 43.35 0.28 42.67 0.28 42.67 1.64 41.97 1.64 41.97 0.28 41.75 0.28 41.75 1.64 41.05 1.64 41.05 0.28 40.83 0.28 40.83 1.64 40.13 1.64 40.13 0.28 39.91 0.28 39.91 1.64 39.21 1.64 39.21 0.28 38.99 0.28 38.99 1.64 38.29 1.64 38.29 0.28 38.07 0.28 38.07 1.64 37.37 1.64 37.37 0.28 37.15 0.28 37.15 1.64 36.45 1.64 36.45 0.28 36.23 0.28 36.23 1.64 35.53 1.64 35.53 0.28 35.31 0.28 35.31 1.64 34.61 1.64 34.61 0.28 33.93 0.28 33.93 1.64 33.23 1.64 33.23 0.28 31.17 0.28 31.17 1.64 30.47 1.64 30.47 0.28 27.88 0.28 27.88 11.16 18.29 11.16 18.29 12.52 17.59 12.52 17.59 11.16 16.45 11.16 16.45 12.52 15.75 12.52 15.75 11.16 15.53 11.16 15.53 12.52 14.83 12.52 14.83 11.16 14.61 11.16 14.61 12.52 13.91 12.52 13.91 11.16 13.69 11.16 13.69 12.52 12.99 12.52 12.99 11.16 12.77 11.16 12.77 12.52 12.07 12.52 12.07 11.16 11.85 11.16 11.85 12.52 11.15 12.52 11.15 11.16 9.55 11.16 9.55 12.52 8.85 12.52 8.85 11.16 8.17 11.16 8.17 12.52 7.47 12.52 7.47 11.16 7.25 11.16 7.25 12.52 6.55 12.52 6.55 11.16 6.33 11.16 6.33 12.52 5.63 12.52 5.63 11.16 5.41 11.16 5.41 12.52 4.71 12.52 4.71 11.16 4.49 11.16 4.49 12.52 3.79 12.52 3.79 11.16 3.57 11.16 3.57 12.52 2.87 12.52 2.87 11.16 0.28 11.16 0.28 97.64 ; LAYER met4 ; - POLYGON 84.24 81.2 84.24 0.4 74.3 0.4 74.3 1 72.9 1 72.9 0.4 59.58 0.4 59.58 1 58.18 1 58.18 0.4 44.86 0.4 44.86 1 43.46 1 43.46 0.4 30.14 0.4 30.14 1 28.74 1 28.74 0.4 23.55 0.4 23.55 1.76 22.45 1.76 22.45 0.4 18.8 0.4 18.8 16.72 6.99 16.72 6.99 18.08 5.89 18.08 5.89 16.72 5.15 16.72 5.15 18.08 4.05 18.08 4.05 16.72 0.4 16.72 0.4 81.2 28.74 81.2 28.74 80.6 30.14 80.6 30.14 81.2 43.46 81.2 43.46 80.6 44.86 80.6 44.86 81.2 58.18 81.2 58.18 80.6 59.58 80.6 59.58 81.2 72.9 81.2 72.9 80.6 74.3 80.6 74.3 81.2 ; + POLYGON 95.28 97.52 95.28 0.4 84.42 0.4 84.42 1 83.02 1 83.02 0.4 69.7 0.4 69.7 1 68.3 1 68.3 0.4 54.98 0.4 54.98 1 53.58 1 53.58 0.4 52.99 0.4 52.99 1.76 51.89 1.76 51.89 0.4 51.15 0.4 51.15 1.76 50.05 1.76 50.05 0.4 40.26 0.4 40.26 1 38.86 1 38.86 0.4 28 0.4 28 11.28 12.51 11.28 12.51 12.64 11.41 12.64 11.41 11.28 10.82 11.28 10.82 11.88 9.42 11.88 9.42 11.28 6.07 11.28 6.07 12.64 4.97 12.64 4.97 11.28 0.4 11.28 0.4 97.52 9.42 97.52 9.42 96.92 10.82 96.92 10.82 97.52 38.86 97.52 38.86 96.92 40.26 96.92 40.26 97.52 53.58 97.52 53.58 96.92 54.98 96.92 54.98 97.52 68.3 97.52 68.3 96.92 69.7 96.92 69.7 97.52 83.02 97.52 83.02 96.92 84.42 96.92 84.42 97.52 ; LAYER met3 ; - POLYGON 73.765 81.765 73.765 81.76 73.98 81.76 73.98 81.44 73.765 81.44 73.765 81.435 73.435 81.435 73.435 81.44 73.22 81.44 73.22 81.76 73.435 81.76 73.435 81.765 ; - POLYGON 44.325 81.765 44.325 81.76 44.54 81.76 44.54 81.44 44.325 81.44 44.325 81.435 43.995 81.435 43.995 81.44 43.78 81.44 43.78 81.76 43.995 81.76 43.995 81.765 ; - POLYGON 2.03 55.24 2.03 55.23 60.87 55.23 60.87 54.93 2.03 54.93 2.03 54.92 1.65 54.92 1.65 55.24 ; - POLYGON 2.005 21.245 2.005 21.23 3.83 21.23 3.83 20.93 2.005 20.93 2.005 20.915 1.675 20.915 1.675 21.245 ; - POLYGON 73.765 0.165 73.765 0.16 73.98 0.16 73.98 -0.16 73.765 -0.16 73.765 -0.165 73.435 -0.165 73.435 -0.16 73.22 -0.16 73.22 0.16 73.435 0.16 73.435 0.165 ; - POLYGON 44.325 0.165 44.325 0.16 44.54 0.16 44.54 -0.16 44.325 -0.16 44.325 -0.165 43.995 -0.165 43.995 -0.16 43.78 -0.16 43.78 0.16 43.995 0.16 43.995 0.165 ; - POLYGON 84.24 81.2 84.24 0.4 18.8 0.4 18.8 4.89 20.18 4.89 20.18 5.99 18.8 5.99 18.8 6.25 20.18 6.25 20.18 7.35 18.8 7.35 18.8 7.61 20.18 7.61 20.18 8.71 18.8 8.71 18.8 8.97 20.18 8.97 20.18 10.07 18.8 10.07 18.8 10.33 20.18 10.33 20.18 11.43 18.8 11.43 18.8 11.69 20.18 11.69 20.18 12.79 18.8 12.79 18.8 16.72 0.4 16.72 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.21 1.78 21.21 1.78 22.31 0.4 22.31 0.4 22.57 1.78 22.57 1.78 23.67 0.4 23.67 0.4 23.93 1.78 23.93 1.78 25.03 0.4 25.03 0.4 25.29 1.78 25.29 1.78 26.39 0.4 26.39 0.4 26.65 1.78 26.65 1.78 27.75 0.4 27.75 0.4 28.01 1.78 28.01 1.78 29.11 0.4 29.11 0.4 29.37 1.78 29.37 1.78 30.47 0.4 30.47 0.4 30.73 1.78 30.73 1.78 31.83 0.4 31.83 0.4 32.09 1.78 32.09 1.78 33.19 0.4 33.19 0.4 33.45 1.78 33.45 1.78 34.55 0.4 34.55 0.4 34.81 1.78 34.81 1.78 35.91 0.4 35.91 0.4 36.17 1.78 36.17 1.78 37.27 0.4 37.27 0.4 37.53 1.78 37.53 1.78 38.63 0.4 38.63 0.4 38.89 1.78 38.89 1.78 39.99 0.4 39.99 0.4 40.25 1.78 40.25 1.78 41.35 0.4 41.35 0.4 41.61 1.78 41.61 1.78 42.71 0.4 42.71 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 50.45 1.78 50.45 1.78 51.55 0.4 51.55 0.4 51.81 1.78 51.81 1.78 52.91 0.4 52.91 0.4 53.17 1.78 53.17 1.78 54.27 0.4 54.27 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 57.25 1.78 57.25 1.78 58.35 0.4 58.35 0.4 58.61 1.78 58.61 1.78 59.71 0.4 59.71 0.4 59.97 1.78 59.97 1.78 61.07 0.4 61.07 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 67.45 1.78 67.45 1.78 68.55 0.4 68.55 0.4 68.81 1.78 68.81 1.78 69.91 0.4 69.91 0.4 70.17 1.78 70.17 1.78 71.27 0.4 71.27 0.4 71.53 1.78 71.53 1.78 72.63 0.4 72.63 0.4 72.89 1.78 72.89 1.78 73.99 0.4 73.99 0.4 74.25 1.78 74.25 1.78 75.35 0.4 75.35 0.4 75.61 1.78 75.61 1.78 76.71 0.4 76.71 0.4 76.97 1.78 76.97 1.78 78.07 0.4 78.07 0.4 81.2 ; + POLYGON 83.885 98.085 83.885 98.08 84.1 98.08 84.1 97.76 83.885 97.76 83.885 97.755 83.555 97.755 83.555 97.76 83.34 97.76 83.34 98.08 83.555 98.08 83.555 98.085 ; + POLYGON 54.445 98.085 54.445 98.08 54.66 98.08 54.66 97.76 54.445 97.76 54.445 97.755 54.115 97.755 54.115 97.76 53.9 97.76 53.9 98.08 54.115 98.08 54.115 98.085 ; + POLYGON 10.285 98.085 10.285 98.08 10.5 98.08 10.5 97.76 10.285 97.76 10.285 97.755 9.955 97.755 9.955 97.76 9.74 97.76 9.74 98.08 9.955 98.08 9.955 98.085 ; + POLYGON 2.03 15.12 2.03 15.11 33.73 15.11 33.73 14.81 2.03 14.81 2.03 14.8 1.65 14.8 1.65 15.12 ; + POLYGON 10.285 11.045 10.285 11.04 10.5 11.04 10.5 10.72 10.285 10.72 10.285 10.715 9.955 10.715 9.955 10.72 9.74 10.72 9.74 11.04 9.955 11.04 9.955 11.045 ; + POLYGON 83.885 0.165 83.885 0.16 84.1 0.16 84.1 -0.16 83.885 -0.16 83.885 -0.165 83.555 -0.165 83.555 -0.16 83.34 -0.16 83.34 0.16 83.555 0.16 83.555 0.165 ; + POLYGON 54.445 0.165 54.445 0.16 54.66 0.16 54.66 -0.16 54.445 -0.16 54.445 -0.165 54.115 -0.165 54.115 -0.16 53.9 -0.16 53.9 0.16 54.115 0.16 54.115 0.165 ; + POLYGON 95.28 97.52 95.28 61.75 93.9 61.75 93.9 60.65 95.28 60.65 95.28 33.87 93.9 33.87 93.9 32.77 95.28 32.77 95.28 0.4 28 0.4 28 11.28 0.4 11.28 0.4 13.73 1.78 13.73 1.78 14.83 0.4 14.83 0.4 17.13 1.78 17.13 1.78 18.23 0.4 18.23 0.4 18.49 1.78 18.49 1.78 19.59 0.4 19.59 0.4 19.85 1.78 19.85 1.78 20.95 0.4 20.95 0.4 21.89 1.78 21.89 1.78 22.99 0.4 22.99 0.4 23.25 1.78 23.25 1.78 24.35 0.4 24.35 0.4 24.61 1.78 24.61 1.78 25.71 0.4 25.71 0.4 25.97 1.78 25.97 1.78 27.07 0.4 27.07 0.4 27.33 1.78 27.33 1.78 28.43 0.4 28.43 0.4 28.69 1.78 28.69 1.78 29.79 0.4 29.79 0.4 30.05 1.78 30.05 1.78 31.15 0.4 31.15 0.4 31.41 1.78 31.41 1.78 32.51 0.4 32.51 0.4 32.77 1.78 32.77 1.78 33.87 0.4 33.87 0.4 34.13 1.78 34.13 1.78 35.23 0.4 35.23 0.4 35.49 1.78 35.49 1.78 36.59 0.4 36.59 0.4 36.85 1.78 36.85 1.78 37.95 0.4 37.95 0.4 38.21 1.78 38.21 1.78 39.31 0.4 39.31 0.4 39.57 1.78 39.57 1.78 40.67 0.4 40.67 0.4 40.93 1.78 40.93 1.78 42.03 0.4 42.03 0.4 42.97 1.78 42.97 1.78 44.07 0.4 44.07 0.4 44.33 1.78 44.33 1.78 45.43 0.4 45.43 0.4 45.69 1.78 45.69 1.78 46.79 0.4 46.79 0.4 47.05 1.78 47.05 1.78 48.15 0.4 48.15 0.4 48.41 1.78 48.41 1.78 49.51 0.4 49.51 0.4 49.77 1.78 49.77 1.78 50.87 0.4 50.87 0.4 51.13 1.78 51.13 1.78 52.23 0.4 52.23 0.4 52.49 1.78 52.49 1.78 53.59 0.4 53.59 0.4 53.85 1.78 53.85 1.78 54.95 0.4 54.95 0.4 55.21 1.78 55.21 1.78 56.31 0.4 56.31 0.4 56.57 1.78 56.57 1.78 57.67 0.4 57.67 0.4 57.93 1.78 57.93 1.78 59.03 0.4 59.03 0.4 59.29 1.78 59.29 1.78 60.39 0.4 60.39 0.4 60.65 1.78 60.65 1.78 61.75 0.4 61.75 0.4 62.01 1.78 62.01 1.78 63.11 0.4 63.11 0.4 63.37 1.78 63.37 1.78 64.47 0.4 64.47 0.4 64.73 1.78 64.73 1.78 65.83 0.4 65.83 0.4 66.09 1.78 66.09 1.78 67.19 0.4 67.19 0.4 68.13 1.78 68.13 1.78 69.23 0.4 69.23 0.4 69.49 1.78 69.49 1.78 70.59 0.4 70.59 0.4 70.85 1.78 70.85 1.78 71.95 0.4 71.95 0.4 72.21 1.78 72.21 1.78 73.31 0.4 73.31 0.4 73.57 1.78 73.57 1.78 74.67 0.4 74.67 0.4 74.93 1.78 74.93 1.78 76.03 0.4 76.03 0.4 76.29 1.78 76.29 1.78 77.39 0.4 77.39 0.4 89.21 1.78 89.21 1.78 90.31 0.4 90.31 0.4 97.52 ; LAYER met5 ; - POLYGON 83.04 80 83.04 72.56 79.84 72.56 79.84 66.16 83.04 66.16 83.04 52.16 79.84 52.16 79.84 45.76 83.04 45.76 83.04 31.76 79.84 31.76 79.84 25.36 83.04 25.36 83.04 1.6 20 1.6 20 17.92 1.6 17.92 1.6 25.36 4.8 25.36 4.8 31.76 1.6 31.76 1.6 45.76 4.8 45.76 4.8 52.16 1.6 52.16 1.6 66.16 4.8 66.16 4.8 72.56 1.6 72.56 1.6 80 ; + POLYGON 94.08 96.32 94.08 88.2 90.88 88.2 90.88 81.8 94.08 81.8 94.08 67.8 90.88 67.8 90.88 61.4 94.08 61.4 94.08 47.4 90.88 47.4 90.88 41 94.08 41 94.08 27 90.88 27 90.88 20.6 94.08 20.6 94.08 1.6 29.2 1.6 29.2 12.48 1.6 12.48 1.6 20.6 4.8 20.6 4.8 27 1.6 27 1.6 41 4.8 41 4.8 47.4 1.6 47.4 1.6 61.4 4.8 61.4 4.8 67.8 1.6 67.8 1.6 81.8 4.8 81.8 4.8 88.2 1.6 88.2 1.6 96.32 ; LAYER met1 ; - POLYGON 84.36 81.08 84.36 79.4 83.88 79.4 83.88 78.36 84.36 78.36 84.36 76.68 83.88 76.68 83.88 75.64 84.36 75.64 84.36 73.96 83.88 73.96 83.88 72.92 84.36 72.92 84.36 71.24 83.88 71.24 83.88 70.2 84.36 70.2 84.36 68.52 83.88 68.52 83.88 67.48 84.36 67.48 84.36 65.8 83.88 65.8 83.88 64.76 84.36 64.76 84.36 63.08 83.88 63.08 83.88 62.04 84.36 62.04 84.36 60.36 83.88 60.36 83.88 59.32 84.36 59.32 84.36 57.64 83.88 57.64 83.88 56.6 84.36 56.6 84.36 54.92 83.88 54.92 83.88 53.88 84.36 53.88 84.36 52.2 83.88 52.2 83.88 51.16 84.36 51.16 84.36 49.48 83.88 49.48 83.88 48.44 84.36 48.44 84.36 46.76 83.88 46.76 83.88 45.72 84.36 45.72 84.36 44.04 83.88 44.04 83.88 43 84.36 43 84.36 41.32 83.88 41.32 83.88 40.28 84.36 40.28 84.36 38.6 83.88 38.6 83.88 37.56 84.36 37.56 84.36 35.88 83.88 35.88 83.88 34.84 84.36 34.84 84.36 33.16 83.88 33.16 83.88 32.12 84.36 32.12 84.36 30.44 83.88 30.44 83.88 29.4 84.36 29.4 84.36 27.72 83.88 27.72 83.88 26.68 84.36 26.68 84.36 25 83.88 25 83.88 23.96 84.36 23.96 84.36 22.28 83.88 22.28 83.88 21.24 84.36 21.24 84.36 19.56 83.88 19.56 83.88 18.52 84.36 18.52 84.36 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 ; - POLYGON 84.36 15.8 84.36 14.12 83.88 14.12 83.88 13.08 84.36 13.08 84.36 11.4 83.88 11.4 83.88 10.36 84.36 10.36 84.36 8.68 83.88 8.68 83.88 7.64 84.36 7.64 84.36 5.96 83.88 5.96 83.88 4.92 84.36 4.92 84.36 3.24 83.88 3.24 83.88 2.2 84.36 2.2 84.36 0.52 18.68 0.52 18.68 2.2 19.16 2.2 19.16 3.24 18.68 3.24 18.68 4.92 19.16 4.92 19.16 5.96 18.68 5.96 18.68 7.64 19.16 7.64 19.16 8.68 18.68 8.68 18.68 10.36 19.16 10.36 19.16 11.4 18.68 11.4 18.68 13.08 19.16 13.08 19.16 14.12 18.68 14.12 18.68 15.8 ; + POLYGON 95.4 97.4 95.4 95.72 94.92 95.72 94.92 94.68 95.4 94.68 95.4 93 94.92 93 94.92 91.96 95.4 91.96 95.4 90.28 94.92 90.28 94.92 89.24 95.4 89.24 95.4 87.56 94.92 87.56 94.92 86.52 95.4 86.52 95.4 84.84 94.92 84.84 94.92 83.8 95.4 83.8 95.4 82.12 94.92 82.12 94.92 81.08 95.4 81.08 95.4 79.4 94.92 79.4 94.92 78.36 95.4 78.36 95.4 76.68 94.92 76.68 94.92 75.64 95.4 75.64 95.4 73.96 94.92 73.96 94.92 72.92 95.4 72.92 95.4 71.24 94.92 71.24 94.92 70.2 95.4 70.2 95.4 68.52 94.92 68.52 94.92 67.48 95.4 67.48 95.4 65.8 94.92 65.8 94.92 64.76 95.4 64.76 95.4 63.08 94.92 63.08 94.92 62.04 95.4 62.04 95.4 60.36 94.92 60.36 94.92 59.32 95.4 59.32 95.4 57.64 94.92 57.64 94.92 56.6 95.4 56.6 95.4 54.92 94.92 54.92 94.92 53.88 95.4 53.88 95.4 52.2 94.92 52.2 94.92 51.16 95.4 51.16 95.4 49.48 94.92 49.48 94.92 48.44 95.4 48.44 95.4 46.76 94.92 46.76 94.92 45.72 95.4 45.72 95.4 44.04 94.92 44.04 94.92 43 95.4 43 95.4 41.32 94.92 41.32 94.92 40.28 95.4 40.28 95.4 38.6 94.92 38.6 94.92 37.56 95.4 37.56 95.4 35.88 94.92 35.88 94.92 34.84 95.4 34.84 95.4 33.16 94.92 33.16 94.92 32.12 95.4 32.12 95.4 30.44 94.92 30.44 94.92 29.4 95.4 29.4 95.4 27.72 94.92 27.72 94.92 26.68 95.4 26.68 95.4 25 94.92 25 94.92 23.96 95.4 23.96 95.4 22.28 94.92 22.28 94.92 21.24 95.4 21.24 95.4 19.56 94.92 19.56 94.92 18.52 95.4 18.52 95.4 16.84 94.92 16.84 94.92 15.8 95.4 15.8 95.4 14.12 94.92 14.12 94.92 13.08 95.4 13.08 95.4 11.4 0.28 11.4 0.28 13.08 0.76 13.08 0.76 14.12 0.28 14.12 0.28 15.8 0.76 15.8 0.76 16.84 0.28 16.84 0.28 18.52 0.76 18.52 0.76 19.56 0.28 19.56 0.28 21.24 0.76 21.24 0.76 22.28 0.28 22.28 0.28 23.96 0.76 23.96 0.76 25 0.28 25 0.28 26.68 0.76 26.68 0.76 27.72 0.28 27.72 0.28 29.4 0.76 29.4 0.76 30.44 0.28 30.44 0.28 32.12 0.76 32.12 0.76 33.16 0.28 33.16 0.28 34.84 0.76 34.84 0.76 35.88 0.28 35.88 0.28 37.56 0.76 37.56 0.76 38.6 0.28 38.6 0.28 40.28 0.76 40.28 0.76 41.32 0.28 41.32 0.28 43 0.76 43 0.76 44.04 0.28 44.04 0.28 45.72 0.76 45.72 0.76 46.76 0.28 46.76 0.28 48.44 0.76 48.44 0.76 49.48 0.28 49.48 0.28 51.16 0.76 51.16 0.76 52.2 0.28 52.2 0.28 53.88 0.76 53.88 0.76 54.92 0.28 54.92 0.28 56.6 0.76 56.6 0.76 57.64 0.28 57.64 0.28 59.32 0.76 59.32 0.76 60.36 0.28 60.36 0.28 62.04 0.76 62.04 0.76 63.08 0.28 63.08 0.28 64.76 0.76 64.76 0.76 65.8 0.28 65.8 0.28 67.48 0.76 67.48 0.76 68.52 0.28 68.52 0.28 70.2 0.76 70.2 0.76 71.24 0.28 71.24 0.28 72.92 0.76 72.92 0.76 73.96 0.28 73.96 0.28 75.64 0.76 75.64 0.76 76.68 0.28 76.68 0.28 78.36 0.76 78.36 0.76 79.4 0.28 79.4 0.28 81.08 0.76 81.08 0.76 82.12 0.28 82.12 0.28 83.8 0.76 83.8 0.76 84.84 0.28 84.84 0.28 86.52 0.76 86.52 0.76 87.56 0.28 87.56 0.28 89.24 0.76 89.24 0.76 90.28 0.28 90.28 0.28 91.96 0.76 91.96 0.76 93 0.28 93 0.28 94.68 0.76 94.68 0.76 95.72 0.28 95.72 0.28 97.4 ; + POLYGON 95.4 10.36 95.4 8.68 94.92 8.68 94.92 7.64 95.4 7.64 95.4 5.96 94.92 5.96 94.92 4.92 95.4 4.92 95.4 3.24 94.92 3.24 94.92 2.2 95.4 2.2 95.4 0.52 27.88 0.52 27.88 2.2 28.36 2.2 28.36 3.24 27.88 3.24 27.88 4.92 28.36 4.92 28.36 5.96 27.88 5.96 27.88 7.64 28.36 7.64 28.36 8.68 27.88 8.68 27.88 10.36 ; LAYER li1 ; - POLYGON 84.47 81.43 84.47 0.17 18.57 0.17 18.57 16.49 0.17 16.49 0.17 81.43 ; + POLYGON 95.51 97.75 95.51 0.17 27.77 0.17 27.77 11.05 0.17 11.05 0.17 97.75 ; LAYER mcon ; - RECT 84.325 81.515 84.495 81.685 ; - RECT 83.865 81.515 84.035 81.685 ; - RECT 83.405 81.515 83.575 81.685 ; - RECT 82.945 81.515 83.115 81.685 ; - RECT 82.485 81.515 82.655 81.685 ; - RECT 82.025 81.515 82.195 81.685 ; - RECT 81.565 81.515 81.735 81.685 ; - RECT 81.105 81.515 81.275 81.685 ; - RECT 80.645 81.515 80.815 81.685 ; - RECT 80.185 81.515 80.355 81.685 ; - RECT 79.725 81.515 79.895 81.685 ; - RECT 79.265 81.515 79.435 81.685 ; - RECT 78.805 81.515 78.975 81.685 ; - RECT 78.345 81.515 78.515 81.685 ; - RECT 77.885 81.515 78.055 81.685 ; - RECT 77.425 81.515 77.595 81.685 ; - RECT 76.965 81.515 77.135 81.685 ; - RECT 76.505 81.515 76.675 81.685 ; - RECT 76.045 81.515 76.215 81.685 ; - RECT 75.585 81.515 75.755 81.685 ; - RECT 75.125 81.515 75.295 81.685 ; - RECT 74.665 81.515 74.835 81.685 ; - RECT 74.205 81.515 74.375 81.685 ; - RECT 73.745 81.515 73.915 81.685 ; - RECT 73.285 81.515 73.455 81.685 ; - RECT 72.825 81.515 72.995 81.685 ; - RECT 72.365 81.515 72.535 81.685 ; - RECT 71.905 81.515 72.075 81.685 ; - RECT 71.445 81.515 71.615 81.685 ; - RECT 70.985 81.515 71.155 81.685 ; - RECT 70.525 81.515 70.695 81.685 ; - RECT 70.065 81.515 70.235 81.685 ; - RECT 69.605 81.515 69.775 81.685 ; - RECT 69.145 81.515 69.315 81.685 ; - RECT 68.685 81.515 68.855 81.685 ; - RECT 68.225 81.515 68.395 81.685 ; - RECT 67.765 81.515 67.935 81.685 ; - RECT 67.305 81.515 67.475 81.685 ; - RECT 66.845 81.515 67.015 81.685 ; - RECT 66.385 81.515 66.555 81.685 ; - RECT 65.925 81.515 66.095 81.685 ; - RECT 65.465 81.515 65.635 81.685 ; - RECT 65.005 81.515 65.175 81.685 ; - RECT 64.545 81.515 64.715 81.685 ; - RECT 64.085 81.515 64.255 81.685 ; - RECT 63.625 81.515 63.795 81.685 ; - RECT 63.165 81.515 63.335 81.685 ; - RECT 62.705 81.515 62.875 81.685 ; - RECT 62.245 81.515 62.415 81.685 ; - RECT 61.785 81.515 61.955 81.685 ; - RECT 61.325 81.515 61.495 81.685 ; - RECT 60.865 81.515 61.035 81.685 ; - RECT 60.405 81.515 60.575 81.685 ; - RECT 59.945 81.515 60.115 81.685 ; - RECT 59.485 81.515 59.655 81.685 ; - RECT 59.025 81.515 59.195 81.685 ; - RECT 58.565 81.515 58.735 81.685 ; - RECT 58.105 81.515 58.275 81.685 ; - RECT 57.645 81.515 57.815 81.685 ; - RECT 57.185 81.515 57.355 81.685 ; - RECT 56.725 81.515 56.895 81.685 ; - RECT 56.265 81.515 56.435 81.685 ; - RECT 55.805 81.515 55.975 81.685 ; - RECT 55.345 81.515 55.515 81.685 ; - RECT 54.885 81.515 55.055 81.685 ; - RECT 54.425 81.515 54.595 81.685 ; - RECT 53.965 81.515 54.135 81.685 ; - RECT 53.505 81.515 53.675 81.685 ; - RECT 53.045 81.515 53.215 81.685 ; - RECT 52.585 81.515 52.755 81.685 ; - RECT 52.125 81.515 52.295 81.685 ; - RECT 51.665 81.515 51.835 81.685 ; - RECT 51.205 81.515 51.375 81.685 ; - RECT 50.745 81.515 50.915 81.685 ; - RECT 50.285 81.515 50.455 81.685 ; - RECT 49.825 81.515 49.995 81.685 ; - RECT 49.365 81.515 49.535 81.685 ; - RECT 48.905 81.515 49.075 81.685 ; - RECT 48.445 81.515 48.615 81.685 ; - RECT 47.985 81.515 48.155 81.685 ; - RECT 47.525 81.515 47.695 81.685 ; - RECT 47.065 81.515 47.235 81.685 ; - RECT 46.605 81.515 46.775 81.685 ; - RECT 46.145 81.515 46.315 81.685 ; - RECT 45.685 81.515 45.855 81.685 ; - RECT 45.225 81.515 45.395 81.685 ; - RECT 44.765 81.515 44.935 81.685 ; - RECT 44.305 81.515 44.475 81.685 ; - RECT 43.845 81.515 44.015 81.685 ; - RECT 43.385 81.515 43.555 81.685 ; - RECT 42.925 81.515 43.095 81.685 ; - RECT 42.465 81.515 42.635 81.685 ; - RECT 42.005 81.515 42.175 81.685 ; - RECT 41.545 81.515 41.715 81.685 ; - RECT 41.085 81.515 41.255 81.685 ; - RECT 40.625 81.515 40.795 81.685 ; - RECT 40.165 81.515 40.335 81.685 ; - RECT 39.705 81.515 39.875 81.685 ; - RECT 39.245 81.515 39.415 81.685 ; - RECT 38.785 81.515 38.955 81.685 ; - RECT 38.325 81.515 38.495 81.685 ; - RECT 37.865 81.515 38.035 81.685 ; - RECT 37.405 81.515 37.575 81.685 ; - RECT 36.945 81.515 37.115 81.685 ; - RECT 36.485 81.515 36.655 81.685 ; - RECT 36.025 81.515 36.195 81.685 ; - RECT 35.565 81.515 35.735 81.685 ; - RECT 35.105 81.515 35.275 81.685 ; - RECT 34.645 81.515 34.815 81.685 ; - RECT 34.185 81.515 34.355 81.685 ; - RECT 33.725 81.515 33.895 81.685 ; - RECT 33.265 81.515 33.435 81.685 ; - RECT 32.805 81.515 32.975 81.685 ; - RECT 32.345 81.515 32.515 81.685 ; - RECT 31.885 81.515 32.055 81.685 ; - RECT 31.425 81.515 31.595 81.685 ; - RECT 30.965 81.515 31.135 81.685 ; - RECT 30.505 81.515 30.675 81.685 ; - RECT 30.045 81.515 30.215 81.685 ; - RECT 29.585 81.515 29.755 81.685 ; - RECT 29.125 81.515 29.295 81.685 ; - RECT 28.665 81.515 28.835 81.685 ; - RECT 28.205 81.515 28.375 81.685 ; - RECT 27.745 81.515 27.915 81.685 ; - RECT 27.285 81.515 27.455 81.685 ; - RECT 26.825 81.515 26.995 81.685 ; - RECT 26.365 81.515 26.535 81.685 ; - RECT 25.905 81.515 26.075 81.685 ; - RECT 25.445 81.515 25.615 81.685 ; - RECT 24.985 81.515 25.155 81.685 ; - RECT 24.525 81.515 24.695 81.685 ; - RECT 24.065 81.515 24.235 81.685 ; - RECT 23.605 81.515 23.775 81.685 ; - RECT 23.145 81.515 23.315 81.685 ; - RECT 22.685 81.515 22.855 81.685 ; - RECT 22.225 81.515 22.395 81.685 ; - RECT 21.765 81.515 21.935 81.685 ; - RECT 21.305 81.515 21.475 81.685 ; - RECT 20.845 81.515 21.015 81.685 ; - RECT 20.385 81.515 20.555 81.685 ; - RECT 19.925 81.515 20.095 81.685 ; - RECT 19.465 81.515 19.635 81.685 ; - RECT 19.005 81.515 19.175 81.685 ; - RECT 18.545 81.515 18.715 81.685 ; - RECT 18.085 81.515 18.255 81.685 ; - RECT 17.625 81.515 17.795 81.685 ; - RECT 17.165 81.515 17.335 81.685 ; - RECT 16.705 81.515 16.875 81.685 ; - RECT 16.245 81.515 16.415 81.685 ; - RECT 15.785 81.515 15.955 81.685 ; - RECT 15.325 81.515 15.495 81.685 ; - RECT 14.865 81.515 15.035 81.685 ; - RECT 14.405 81.515 14.575 81.685 ; - RECT 13.945 81.515 14.115 81.685 ; - RECT 13.485 81.515 13.655 81.685 ; - RECT 13.025 81.515 13.195 81.685 ; - RECT 12.565 81.515 12.735 81.685 ; - RECT 12.105 81.515 12.275 81.685 ; - RECT 11.645 81.515 11.815 81.685 ; - RECT 11.185 81.515 11.355 81.685 ; - RECT 10.725 81.515 10.895 81.685 ; - RECT 10.265 81.515 10.435 81.685 ; - RECT 9.805 81.515 9.975 81.685 ; - RECT 9.345 81.515 9.515 81.685 ; - RECT 8.885 81.515 9.055 81.685 ; - RECT 8.425 81.515 8.595 81.685 ; - RECT 7.965 81.515 8.135 81.685 ; - RECT 7.505 81.515 7.675 81.685 ; - RECT 7.045 81.515 7.215 81.685 ; - RECT 6.585 81.515 6.755 81.685 ; - RECT 6.125 81.515 6.295 81.685 ; - RECT 5.665 81.515 5.835 81.685 ; - RECT 5.205 81.515 5.375 81.685 ; - RECT 4.745 81.515 4.915 81.685 ; - RECT 4.285 81.515 4.455 81.685 ; - RECT 3.825 81.515 3.995 81.685 ; - RECT 3.365 81.515 3.535 81.685 ; - RECT 2.905 81.515 3.075 81.685 ; - RECT 2.445 81.515 2.615 81.685 ; - RECT 1.985 81.515 2.155 81.685 ; - RECT 1.525 81.515 1.695 81.685 ; - RECT 1.065 81.515 1.235 81.685 ; + RECT 95.365 97.835 95.535 98.005 ; + RECT 94.905 97.835 95.075 98.005 ; + RECT 94.445 97.835 94.615 98.005 ; + RECT 93.985 97.835 94.155 98.005 ; + RECT 93.525 97.835 93.695 98.005 ; + RECT 93.065 97.835 93.235 98.005 ; + RECT 92.605 97.835 92.775 98.005 ; + RECT 92.145 97.835 92.315 98.005 ; + RECT 91.685 97.835 91.855 98.005 ; + RECT 91.225 97.835 91.395 98.005 ; + RECT 90.765 97.835 90.935 98.005 ; + RECT 90.305 97.835 90.475 98.005 ; + RECT 89.845 97.835 90.015 98.005 ; + RECT 89.385 97.835 89.555 98.005 ; + RECT 88.925 97.835 89.095 98.005 ; + RECT 88.465 97.835 88.635 98.005 ; + RECT 88.005 97.835 88.175 98.005 ; + RECT 87.545 97.835 87.715 98.005 ; + RECT 87.085 97.835 87.255 98.005 ; + RECT 86.625 97.835 86.795 98.005 ; + RECT 86.165 97.835 86.335 98.005 ; + RECT 85.705 97.835 85.875 98.005 ; + RECT 85.245 97.835 85.415 98.005 ; + RECT 84.785 97.835 84.955 98.005 ; + RECT 84.325 97.835 84.495 98.005 ; + RECT 83.865 97.835 84.035 98.005 ; + RECT 83.405 97.835 83.575 98.005 ; + RECT 82.945 97.835 83.115 98.005 ; + RECT 82.485 97.835 82.655 98.005 ; + RECT 82.025 97.835 82.195 98.005 ; + RECT 81.565 97.835 81.735 98.005 ; + RECT 81.105 97.835 81.275 98.005 ; + RECT 80.645 97.835 80.815 98.005 ; + RECT 80.185 97.835 80.355 98.005 ; + RECT 79.725 97.835 79.895 98.005 ; + RECT 79.265 97.835 79.435 98.005 ; + RECT 78.805 97.835 78.975 98.005 ; + RECT 78.345 97.835 78.515 98.005 ; + RECT 77.885 97.835 78.055 98.005 ; + RECT 77.425 97.835 77.595 98.005 ; + RECT 76.965 97.835 77.135 98.005 ; + RECT 76.505 97.835 76.675 98.005 ; + RECT 76.045 97.835 76.215 98.005 ; + RECT 75.585 97.835 75.755 98.005 ; + RECT 75.125 97.835 75.295 98.005 ; + RECT 74.665 97.835 74.835 98.005 ; + RECT 74.205 97.835 74.375 98.005 ; + RECT 73.745 97.835 73.915 98.005 ; + RECT 73.285 97.835 73.455 98.005 ; + RECT 72.825 97.835 72.995 98.005 ; + RECT 72.365 97.835 72.535 98.005 ; + RECT 71.905 97.835 72.075 98.005 ; + RECT 71.445 97.835 71.615 98.005 ; + RECT 70.985 97.835 71.155 98.005 ; + RECT 70.525 97.835 70.695 98.005 ; + RECT 70.065 97.835 70.235 98.005 ; + RECT 69.605 97.835 69.775 98.005 ; + RECT 69.145 97.835 69.315 98.005 ; + RECT 68.685 97.835 68.855 98.005 ; + RECT 68.225 97.835 68.395 98.005 ; + RECT 67.765 97.835 67.935 98.005 ; + RECT 67.305 97.835 67.475 98.005 ; + RECT 66.845 97.835 67.015 98.005 ; + RECT 66.385 97.835 66.555 98.005 ; + RECT 65.925 97.835 66.095 98.005 ; + RECT 65.465 97.835 65.635 98.005 ; + RECT 65.005 97.835 65.175 98.005 ; + RECT 64.545 97.835 64.715 98.005 ; + RECT 64.085 97.835 64.255 98.005 ; + RECT 63.625 97.835 63.795 98.005 ; + RECT 63.165 97.835 63.335 98.005 ; + RECT 62.705 97.835 62.875 98.005 ; + RECT 62.245 97.835 62.415 98.005 ; + RECT 61.785 97.835 61.955 98.005 ; + RECT 61.325 97.835 61.495 98.005 ; + RECT 60.865 97.835 61.035 98.005 ; + RECT 60.405 97.835 60.575 98.005 ; + RECT 59.945 97.835 60.115 98.005 ; + RECT 59.485 97.835 59.655 98.005 ; + RECT 59.025 97.835 59.195 98.005 ; + RECT 58.565 97.835 58.735 98.005 ; + RECT 58.105 97.835 58.275 98.005 ; + RECT 57.645 97.835 57.815 98.005 ; + RECT 57.185 97.835 57.355 98.005 ; + RECT 56.725 97.835 56.895 98.005 ; + RECT 56.265 97.835 56.435 98.005 ; + RECT 55.805 97.835 55.975 98.005 ; + RECT 55.345 97.835 55.515 98.005 ; + RECT 54.885 97.835 55.055 98.005 ; + RECT 54.425 97.835 54.595 98.005 ; + RECT 53.965 97.835 54.135 98.005 ; + RECT 53.505 97.835 53.675 98.005 ; + RECT 53.045 97.835 53.215 98.005 ; + RECT 52.585 97.835 52.755 98.005 ; + RECT 52.125 97.835 52.295 98.005 ; + RECT 51.665 97.835 51.835 98.005 ; + RECT 51.205 97.835 51.375 98.005 ; + RECT 50.745 97.835 50.915 98.005 ; + RECT 50.285 97.835 50.455 98.005 ; + RECT 49.825 97.835 49.995 98.005 ; + RECT 49.365 97.835 49.535 98.005 ; + RECT 48.905 97.835 49.075 98.005 ; + RECT 48.445 97.835 48.615 98.005 ; + RECT 47.985 97.835 48.155 98.005 ; + RECT 47.525 97.835 47.695 98.005 ; + RECT 47.065 97.835 47.235 98.005 ; + RECT 46.605 97.835 46.775 98.005 ; + RECT 46.145 97.835 46.315 98.005 ; + RECT 45.685 97.835 45.855 98.005 ; + RECT 45.225 97.835 45.395 98.005 ; + RECT 44.765 97.835 44.935 98.005 ; + RECT 44.305 97.835 44.475 98.005 ; + RECT 43.845 97.835 44.015 98.005 ; + RECT 43.385 97.835 43.555 98.005 ; + RECT 42.925 97.835 43.095 98.005 ; + RECT 42.465 97.835 42.635 98.005 ; + RECT 42.005 97.835 42.175 98.005 ; + RECT 41.545 97.835 41.715 98.005 ; + RECT 41.085 97.835 41.255 98.005 ; + RECT 40.625 97.835 40.795 98.005 ; + RECT 40.165 97.835 40.335 98.005 ; + RECT 39.705 97.835 39.875 98.005 ; + RECT 39.245 97.835 39.415 98.005 ; + RECT 38.785 97.835 38.955 98.005 ; + RECT 38.325 97.835 38.495 98.005 ; + RECT 37.865 97.835 38.035 98.005 ; + RECT 37.405 97.835 37.575 98.005 ; + RECT 36.945 97.835 37.115 98.005 ; + RECT 36.485 97.835 36.655 98.005 ; + RECT 36.025 97.835 36.195 98.005 ; + RECT 35.565 97.835 35.735 98.005 ; + RECT 35.105 97.835 35.275 98.005 ; + RECT 34.645 97.835 34.815 98.005 ; + RECT 34.185 97.835 34.355 98.005 ; + RECT 33.725 97.835 33.895 98.005 ; + RECT 33.265 97.835 33.435 98.005 ; + RECT 32.805 97.835 32.975 98.005 ; + RECT 32.345 97.835 32.515 98.005 ; + RECT 31.885 97.835 32.055 98.005 ; + RECT 31.425 97.835 31.595 98.005 ; + RECT 30.965 97.835 31.135 98.005 ; + RECT 30.505 97.835 30.675 98.005 ; + RECT 30.045 97.835 30.215 98.005 ; + RECT 29.585 97.835 29.755 98.005 ; + RECT 29.125 97.835 29.295 98.005 ; + RECT 28.665 97.835 28.835 98.005 ; + RECT 28.205 97.835 28.375 98.005 ; + RECT 27.745 97.835 27.915 98.005 ; + RECT 27.285 97.835 27.455 98.005 ; + RECT 26.825 97.835 26.995 98.005 ; + RECT 26.365 97.835 26.535 98.005 ; + RECT 25.905 97.835 26.075 98.005 ; + RECT 25.445 97.835 25.615 98.005 ; + RECT 24.985 97.835 25.155 98.005 ; + RECT 24.525 97.835 24.695 98.005 ; + RECT 24.065 97.835 24.235 98.005 ; + RECT 23.605 97.835 23.775 98.005 ; + RECT 23.145 97.835 23.315 98.005 ; + RECT 22.685 97.835 22.855 98.005 ; + RECT 22.225 97.835 22.395 98.005 ; + RECT 21.765 97.835 21.935 98.005 ; + RECT 21.305 97.835 21.475 98.005 ; + RECT 20.845 97.835 21.015 98.005 ; + RECT 20.385 97.835 20.555 98.005 ; + RECT 19.925 97.835 20.095 98.005 ; + RECT 19.465 97.835 19.635 98.005 ; + RECT 19.005 97.835 19.175 98.005 ; + RECT 18.545 97.835 18.715 98.005 ; + RECT 18.085 97.835 18.255 98.005 ; + RECT 17.625 97.835 17.795 98.005 ; + RECT 17.165 97.835 17.335 98.005 ; + RECT 16.705 97.835 16.875 98.005 ; + RECT 16.245 97.835 16.415 98.005 ; + RECT 15.785 97.835 15.955 98.005 ; + RECT 15.325 97.835 15.495 98.005 ; + RECT 14.865 97.835 15.035 98.005 ; + RECT 14.405 97.835 14.575 98.005 ; + RECT 13.945 97.835 14.115 98.005 ; + RECT 13.485 97.835 13.655 98.005 ; + RECT 13.025 97.835 13.195 98.005 ; + RECT 12.565 97.835 12.735 98.005 ; + RECT 12.105 97.835 12.275 98.005 ; + RECT 11.645 97.835 11.815 98.005 ; + RECT 11.185 97.835 11.355 98.005 ; + RECT 10.725 97.835 10.895 98.005 ; + RECT 10.265 97.835 10.435 98.005 ; + RECT 9.805 97.835 9.975 98.005 ; + RECT 9.345 97.835 9.515 98.005 ; + RECT 8.885 97.835 9.055 98.005 ; + RECT 8.425 97.835 8.595 98.005 ; + RECT 7.965 97.835 8.135 98.005 ; + RECT 7.505 97.835 7.675 98.005 ; + RECT 7.045 97.835 7.215 98.005 ; + RECT 6.585 97.835 6.755 98.005 ; + RECT 6.125 97.835 6.295 98.005 ; + RECT 5.665 97.835 5.835 98.005 ; + RECT 5.205 97.835 5.375 98.005 ; + RECT 4.745 97.835 4.915 98.005 ; + RECT 4.285 97.835 4.455 98.005 ; + RECT 3.825 97.835 3.995 98.005 ; + RECT 3.365 97.835 3.535 98.005 ; + RECT 2.905 97.835 3.075 98.005 ; + RECT 2.445 97.835 2.615 98.005 ; + RECT 1.985 97.835 2.155 98.005 ; + RECT 1.525 97.835 1.695 98.005 ; + RECT 1.065 97.835 1.235 98.005 ; + RECT 0.605 97.835 0.775 98.005 ; + RECT 0.145 97.835 0.315 98.005 ; + RECT 95.365 95.115 95.535 95.285 ; + RECT 94.905 95.115 95.075 95.285 ; + RECT 0.605 95.115 0.775 95.285 ; + RECT 0.145 95.115 0.315 95.285 ; + RECT 95.365 92.395 95.535 92.565 ; + RECT 94.905 92.395 95.075 92.565 ; + RECT 0.605 92.395 0.775 92.565 ; + RECT 0.145 92.395 0.315 92.565 ; + RECT 95.365 89.675 95.535 89.845 ; + RECT 94.905 89.675 95.075 89.845 ; + RECT 0.605 89.675 0.775 89.845 ; + RECT 0.145 89.675 0.315 89.845 ; + RECT 95.365 86.955 95.535 87.125 ; + RECT 94.905 86.955 95.075 87.125 ; + RECT 0.605 86.955 0.775 87.125 ; + RECT 0.145 86.955 0.315 87.125 ; + RECT 95.365 84.235 95.535 84.405 ; + RECT 94.905 84.235 95.075 84.405 ; + RECT 0.605 84.235 0.775 84.405 ; + RECT 0.145 84.235 0.315 84.405 ; + RECT 95.365 81.515 95.535 81.685 ; + RECT 94.905 81.515 95.075 81.685 ; RECT 0.605 81.515 0.775 81.685 ; RECT 0.145 81.515 0.315 81.685 ; - RECT 84.325 78.795 84.495 78.965 ; - RECT 83.865 78.795 84.035 78.965 ; + RECT 95.365 78.795 95.535 78.965 ; + RECT 94.905 78.795 95.075 78.965 ; RECT 0.605 78.795 0.775 78.965 ; RECT 0.145 78.795 0.315 78.965 ; - RECT 84.325 76.075 84.495 76.245 ; - RECT 83.865 76.075 84.035 76.245 ; + RECT 95.365 76.075 95.535 76.245 ; + RECT 94.905 76.075 95.075 76.245 ; RECT 0.605 76.075 0.775 76.245 ; RECT 0.145 76.075 0.315 76.245 ; - RECT 84.325 73.355 84.495 73.525 ; - RECT 83.865 73.355 84.035 73.525 ; + RECT 95.365 73.355 95.535 73.525 ; + RECT 94.905 73.355 95.075 73.525 ; RECT 0.605 73.355 0.775 73.525 ; RECT 0.145 73.355 0.315 73.525 ; - RECT 84.325 70.635 84.495 70.805 ; - RECT 83.865 70.635 84.035 70.805 ; + RECT 95.365 70.635 95.535 70.805 ; + RECT 94.905 70.635 95.075 70.805 ; RECT 0.605 70.635 0.775 70.805 ; RECT 0.145 70.635 0.315 70.805 ; - RECT 84.325 67.915 84.495 68.085 ; - RECT 83.865 67.915 84.035 68.085 ; + RECT 95.365 67.915 95.535 68.085 ; + RECT 94.905 67.915 95.075 68.085 ; RECT 0.605 67.915 0.775 68.085 ; RECT 0.145 67.915 0.315 68.085 ; - RECT 84.325 65.195 84.495 65.365 ; - RECT 83.865 65.195 84.035 65.365 ; + RECT 95.365 65.195 95.535 65.365 ; + RECT 94.905 65.195 95.075 65.365 ; RECT 0.605 65.195 0.775 65.365 ; RECT 0.145 65.195 0.315 65.365 ; - RECT 84.325 62.475 84.495 62.645 ; - RECT 83.865 62.475 84.035 62.645 ; + RECT 95.365 62.475 95.535 62.645 ; + RECT 94.905 62.475 95.075 62.645 ; RECT 0.605 62.475 0.775 62.645 ; RECT 0.145 62.475 0.315 62.645 ; - RECT 84.325 59.755 84.495 59.925 ; - RECT 83.865 59.755 84.035 59.925 ; + RECT 95.365 59.755 95.535 59.925 ; + RECT 94.905 59.755 95.075 59.925 ; RECT 0.605 59.755 0.775 59.925 ; RECT 0.145 59.755 0.315 59.925 ; - RECT 84.325 57.035 84.495 57.205 ; - RECT 83.865 57.035 84.035 57.205 ; + RECT 95.365 57.035 95.535 57.205 ; + RECT 94.905 57.035 95.075 57.205 ; RECT 0.605 57.035 0.775 57.205 ; RECT 0.145 57.035 0.315 57.205 ; - RECT 84.325 54.315 84.495 54.485 ; - RECT 83.865 54.315 84.035 54.485 ; + RECT 95.365 54.315 95.535 54.485 ; + RECT 94.905 54.315 95.075 54.485 ; RECT 0.605 54.315 0.775 54.485 ; RECT 0.145 54.315 0.315 54.485 ; - RECT 84.325 51.595 84.495 51.765 ; - RECT 83.865 51.595 84.035 51.765 ; + RECT 95.365 51.595 95.535 51.765 ; + RECT 94.905 51.595 95.075 51.765 ; RECT 0.605 51.595 0.775 51.765 ; RECT 0.145 51.595 0.315 51.765 ; - RECT 84.325 48.875 84.495 49.045 ; - RECT 83.865 48.875 84.035 49.045 ; + RECT 95.365 48.875 95.535 49.045 ; + RECT 94.905 48.875 95.075 49.045 ; RECT 0.605 48.875 0.775 49.045 ; RECT 0.145 48.875 0.315 49.045 ; - RECT 84.325 46.155 84.495 46.325 ; - RECT 83.865 46.155 84.035 46.325 ; + RECT 95.365 46.155 95.535 46.325 ; + RECT 94.905 46.155 95.075 46.325 ; RECT 0.605 46.155 0.775 46.325 ; RECT 0.145 46.155 0.315 46.325 ; - RECT 84.325 43.435 84.495 43.605 ; - RECT 83.865 43.435 84.035 43.605 ; + RECT 95.365 43.435 95.535 43.605 ; + RECT 94.905 43.435 95.075 43.605 ; RECT 0.605 43.435 0.775 43.605 ; RECT 0.145 43.435 0.315 43.605 ; - RECT 84.325 40.715 84.495 40.885 ; - RECT 83.865 40.715 84.035 40.885 ; + RECT 95.365 40.715 95.535 40.885 ; + RECT 94.905 40.715 95.075 40.885 ; RECT 0.605 40.715 0.775 40.885 ; RECT 0.145 40.715 0.315 40.885 ; - RECT 84.325 37.995 84.495 38.165 ; - RECT 83.865 37.995 84.035 38.165 ; + RECT 95.365 37.995 95.535 38.165 ; + RECT 94.905 37.995 95.075 38.165 ; RECT 0.605 37.995 0.775 38.165 ; RECT 0.145 37.995 0.315 38.165 ; - RECT 84.325 35.275 84.495 35.445 ; - RECT 83.865 35.275 84.035 35.445 ; + RECT 95.365 35.275 95.535 35.445 ; + RECT 94.905 35.275 95.075 35.445 ; RECT 0.605 35.275 0.775 35.445 ; RECT 0.145 35.275 0.315 35.445 ; - RECT 84.325 32.555 84.495 32.725 ; - RECT 83.865 32.555 84.035 32.725 ; + RECT 95.365 32.555 95.535 32.725 ; + RECT 94.905 32.555 95.075 32.725 ; RECT 0.605 32.555 0.775 32.725 ; RECT 0.145 32.555 0.315 32.725 ; - RECT 84.325 29.835 84.495 30.005 ; - RECT 83.865 29.835 84.035 30.005 ; + RECT 95.365 29.835 95.535 30.005 ; + RECT 94.905 29.835 95.075 30.005 ; RECT 0.605 29.835 0.775 30.005 ; RECT 0.145 29.835 0.315 30.005 ; - RECT 84.325 27.115 84.495 27.285 ; - RECT 83.865 27.115 84.035 27.285 ; + RECT 95.365 27.115 95.535 27.285 ; + RECT 94.905 27.115 95.075 27.285 ; RECT 0.605 27.115 0.775 27.285 ; RECT 0.145 27.115 0.315 27.285 ; - RECT 84.325 24.395 84.495 24.565 ; - RECT 83.865 24.395 84.035 24.565 ; + RECT 95.365 24.395 95.535 24.565 ; + RECT 94.905 24.395 95.075 24.565 ; RECT 0.605 24.395 0.775 24.565 ; RECT 0.145 24.395 0.315 24.565 ; - RECT 84.325 21.675 84.495 21.845 ; - RECT 83.865 21.675 84.035 21.845 ; + RECT 95.365 21.675 95.535 21.845 ; + RECT 94.905 21.675 95.075 21.845 ; RECT 0.605 21.675 0.775 21.845 ; RECT 0.145 21.675 0.315 21.845 ; - RECT 84.325 18.955 84.495 19.125 ; - RECT 83.865 18.955 84.035 19.125 ; + RECT 95.365 18.955 95.535 19.125 ; + RECT 94.905 18.955 95.075 19.125 ; RECT 0.605 18.955 0.775 19.125 ; RECT 0.145 18.955 0.315 19.125 ; - RECT 84.325 16.235 84.495 16.405 ; - RECT 83.865 16.235 84.035 16.405 ; - RECT 83.405 16.235 83.575 16.405 ; - RECT 82.945 16.235 83.115 16.405 ; - RECT 82.485 16.235 82.655 16.405 ; - RECT 82.025 16.235 82.195 16.405 ; - RECT 81.565 16.235 81.735 16.405 ; - RECT 81.105 16.235 81.275 16.405 ; - RECT 80.645 16.235 80.815 16.405 ; - RECT 80.185 16.235 80.355 16.405 ; - RECT 79.725 16.235 79.895 16.405 ; - RECT 79.265 16.235 79.435 16.405 ; - RECT 78.805 16.235 78.975 16.405 ; - RECT 78.345 16.235 78.515 16.405 ; - RECT 77.885 16.235 78.055 16.405 ; - RECT 77.425 16.235 77.595 16.405 ; - RECT 76.965 16.235 77.135 16.405 ; - RECT 76.505 16.235 76.675 16.405 ; - RECT 76.045 16.235 76.215 16.405 ; - RECT 75.585 16.235 75.755 16.405 ; - RECT 75.125 16.235 75.295 16.405 ; - RECT 74.665 16.235 74.835 16.405 ; - RECT 74.205 16.235 74.375 16.405 ; - RECT 73.745 16.235 73.915 16.405 ; - RECT 73.285 16.235 73.455 16.405 ; - RECT 72.825 16.235 72.995 16.405 ; - RECT 72.365 16.235 72.535 16.405 ; - RECT 71.905 16.235 72.075 16.405 ; - RECT 71.445 16.235 71.615 16.405 ; - RECT 70.985 16.235 71.155 16.405 ; - RECT 70.525 16.235 70.695 16.405 ; - RECT 70.065 16.235 70.235 16.405 ; - RECT 69.605 16.235 69.775 16.405 ; - RECT 69.145 16.235 69.315 16.405 ; - RECT 68.685 16.235 68.855 16.405 ; - RECT 68.225 16.235 68.395 16.405 ; - RECT 67.765 16.235 67.935 16.405 ; - RECT 67.305 16.235 67.475 16.405 ; - RECT 66.845 16.235 67.015 16.405 ; - RECT 66.385 16.235 66.555 16.405 ; - RECT 65.925 16.235 66.095 16.405 ; - RECT 65.465 16.235 65.635 16.405 ; - RECT 65.005 16.235 65.175 16.405 ; - RECT 64.545 16.235 64.715 16.405 ; - RECT 64.085 16.235 64.255 16.405 ; - RECT 63.625 16.235 63.795 16.405 ; - RECT 63.165 16.235 63.335 16.405 ; - RECT 62.705 16.235 62.875 16.405 ; - RECT 62.245 16.235 62.415 16.405 ; - RECT 61.785 16.235 61.955 16.405 ; - RECT 61.325 16.235 61.495 16.405 ; - RECT 60.865 16.235 61.035 16.405 ; - RECT 60.405 16.235 60.575 16.405 ; - RECT 59.945 16.235 60.115 16.405 ; - RECT 59.485 16.235 59.655 16.405 ; - RECT 59.025 16.235 59.195 16.405 ; - RECT 58.565 16.235 58.735 16.405 ; - RECT 58.105 16.235 58.275 16.405 ; - RECT 57.645 16.235 57.815 16.405 ; - RECT 57.185 16.235 57.355 16.405 ; - RECT 56.725 16.235 56.895 16.405 ; - RECT 56.265 16.235 56.435 16.405 ; - RECT 55.805 16.235 55.975 16.405 ; - RECT 55.345 16.235 55.515 16.405 ; - RECT 54.885 16.235 55.055 16.405 ; - RECT 54.425 16.235 54.595 16.405 ; - RECT 53.965 16.235 54.135 16.405 ; - RECT 53.505 16.235 53.675 16.405 ; - RECT 53.045 16.235 53.215 16.405 ; - RECT 52.585 16.235 52.755 16.405 ; - RECT 52.125 16.235 52.295 16.405 ; - RECT 51.665 16.235 51.835 16.405 ; - RECT 51.205 16.235 51.375 16.405 ; - RECT 50.745 16.235 50.915 16.405 ; - RECT 50.285 16.235 50.455 16.405 ; - RECT 49.825 16.235 49.995 16.405 ; - RECT 49.365 16.235 49.535 16.405 ; - RECT 48.905 16.235 49.075 16.405 ; - RECT 48.445 16.235 48.615 16.405 ; - RECT 47.985 16.235 48.155 16.405 ; - RECT 47.525 16.235 47.695 16.405 ; - RECT 47.065 16.235 47.235 16.405 ; - RECT 46.605 16.235 46.775 16.405 ; - RECT 46.145 16.235 46.315 16.405 ; - RECT 45.685 16.235 45.855 16.405 ; - RECT 45.225 16.235 45.395 16.405 ; - RECT 44.765 16.235 44.935 16.405 ; - RECT 44.305 16.235 44.475 16.405 ; - RECT 43.845 16.235 44.015 16.405 ; - RECT 43.385 16.235 43.555 16.405 ; - RECT 42.925 16.235 43.095 16.405 ; - RECT 42.465 16.235 42.635 16.405 ; - RECT 42.005 16.235 42.175 16.405 ; - RECT 41.545 16.235 41.715 16.405 ; - RECT 41.085 16.235 41.255 16.405 ; - RECT 40.625 16.235 40.795 16.405 ; - RECT 40.165 16.235 40.335 16.405 ; - RECT 39.705 16.235 39.875 16.405 ; - RECT 39.245 16.235 39.415 16.405 ; - RECT 38.785 16.235 38.955 16.405 ; - RECT 38.325 16.235 38.495 16.405 ; - RECT 37.865 16.235 38.035 16.405 ; - RECT 37.405 16.235 37.575 16.405 ; - RECT 36.945 16.235 37.115 16.405 ; - RECT 36.485 16.235 36.655 16.405 ; - RECT 36.025 16.235 36.195 16.405 ; - RECT 35.565 16.235 35.735 16.405 ; - RECT 35.105 16.235 35.275 16.405 ; - RECT 34.645 16.235 34.815 16.405 ; - RECT 34.185 16.235 34.355 16.405 ; - RECT 33.725 16.235 33.895 16.405 ; - RECT 33.265 16.235 33.435 16.405 ; - RECT 32.805 16.235 32.975 16.405 ; - RECT 32.345 16.235 32.515 16.405 ; - RECT 31.885 16.235 32.055 16.405 ; - RECT 31.425 16.235 31.595 16.405 ; - RECT 30.965 16.235 31.135 16.405 ; - RECT 30.505 16.235 30.675 16.405 ; - RECT 30.045 16.235 30.215 16.405 ; - RECT 29.585 16.235 29.755 16.405 ; - RECT 29.125 16.235 29.295 16.405 ; - RECT 28.665 16.235 28.835 16.405 ; - RECT 28.205 16.235 28.375 16.405 ; - RECT 27.745 16.235 27.915 16.405 ; - RECT 27.285 16.235 27.455 16.405 ; - RECT 26.825 16.235 26.995 16.405 ; - RECT 26.365 16.235 26.535 16.405 ; - RECT 25.905 16.235 26.075 16.405 ; - RECT 25.445 16.235 25.615 16.405 ; - RECT 24.985 16.235 25.155 16.405 ; - RECT 24.525 16.235 24.695 16.405 ; - RECT 24.065 16.235 24.235 16.405 ; - RECT 23.605 16.235 23.775 16.405 ; - RECT 23.145 16.235 23.315 16.405 ; - RECT 22.685 16.235 22.855 16.405 ; - RECT 22.225 16.235 22.395 16.405 ; - RECT 21.765 16.235 21.935 16.405 ; - RECT 21.305 16.235 21.475 16.405 ; - RECT 20.845 16.235 21.015 16.405 ; - RECT 20.385 16.235 20.555 16.405 ; - RECT 19.925 16.235 20.095 16.405 ; - RECT 19.465 16.235 19.635 16.405 ; - RECT 19.005 16.235 19.175 16.405 ; - RECT 18.545 16.235 18.715 16.405 ; - RECT 18.085 16.235 18.255 16.405 ; - RECT 17.625 16.235 17.795 16.405 ; - RECT 17.165 16.235 17.335 16.405 ; - RECT 16.705 16.235 16.875 16.405 ; - RECT 16.245 16.235 16.415 16.405 ; - RECT 15.785 16.235 15.955 16.405 ; - RECT 15.325 16.235 15.495 16.405 ; - RECT 14.865 16.235 15.035 16.405 ; - RECT 14.405 16.235 14.575 16.405 ; - RECT 13.945 16.235 14.115 16.405 ; - RECT 13.485 16.235 13.655 16.405 ; - RECT 13.025 16.235 13.195 16.405 ; - RECT 12.565 16.235 12.735 16.405 ; - RECT 12.105 16.235 12.275 16.405 ; - RECT 11.645 16.235 11.815 16.405 ; - RECT 11.185 16.235 11.355 16.405 ; - RECT 10.725 16.235 10.895 16.405 ; - RECT 10.265 16.235 10.435 16.405 ; - RECT 9.805 16.235 9.975 16.405 ; - RECT 9.345 16.235 9.515 16.405 ; - RECT 8.885 16.235 9.055 16.405 ; - RECT 8.425 16.235 8.595 16.405 ; - RECT 7.965 16.235 8.135 16.405 ; - RECT 7.505 16.235 7.675 16.405 ; - RECT 7.045 16.235 7.215 16.405 ; - RECT 6.585 16.235 6.755 16.405 ; - RECT 6.125 16.235 6.295 16.405 ; - RECT 5.665 16.235 5.835 16.405 ; - RECT 5.205 16.235 5.375 16.405 ; - RECT 4.745 16.235 4.915 16.405 ; - RECT 4.285 16.235 4.455 16.405 ; - RECT 3.825 16.235 3.995 16.405 ; - RECT 3.365 16.235 3.535 16.405 ; - RECT 2.905 16.235 3.075 16.405 ; - RECT 2.445 16.235 2.615 16.405 ; - RECT 1.985 16.235 2.155 16.405 ; - RECT 1.525 16.235 1.695 16.405 ; - RECT 1.065 16.235 1.235 16.405 ; + RECT 95.365 16.235 95.535 16.405 ; + RECT 94.905 16.235 95.075 16.405 ; RECT 0.605 16.235 0.775 16.405 ; RECT 0.145 16.235 0.315 16.405 ; - RECT 84.325 13.515 84.495 13.685 ; - RECT 83.865 13.515 84.035 13.685 ; - RECT 19.005 13.515 19.175 13.685 ; - RECT 18.545 13.515 18.715 13.685 ; + RECT 95.365 13.515 95.535 13.685 ; + RECT 94.905 13.515 95.075 13.685 ; + RECT 0.605 13.515 0.775 13.685 ; + RECT 0.145 13.515 0.315 13.685 ; + RECT 95.365 10.795 95.535 10.965 ; + RECT 94.905 10.795 95.075 10.965 ; + RECT 94.445 10.795 94.615 10.965 ; + RECT 93.985 10.795 94.155 10.965 ; + RECT 93.525 10.795 93.695 10.965 ; + RECT 93.065 10.795 93.235 10.965 ; + RECT 92.605 10.795 92.775 10.965 ; + RECT 92.145 10.795 92.315 10.965 ; + RECT 91.685 10.795 91.855 10.965 ; + RECT 91.225 10.795 91.395 10.965 ; + RECT 90.765 10.795 90.935 10.965 ; + RECT 90.305 10.795 90.475 10.965 ; + RECT 89.845 10.795 90.015 10.965 ; + RECT 89.385 10.795 89.555 10.965 ; + RECT 88.925 10.795 89.095 10.965 ; + RECT 88.465 10.795 88.635 10.965 ; + RECT 88.005 10.795 88.175 10.965 ; + RECT 87.545 10.795 87.715 10.965 ; + RECT 87.085 10.795 87.255 10.965 ; + RECT 86.625 10.795 86.795 10.965 ; + RECT 86.165 10.795 86.335 10.965 ; + RECT 85.705 10.795 85.875 10.965 ; + RECT 85.245 10.795 85.415 10.965 ; + RECT 84.785 10.795 84.955 10.965 ; RECT 84.325 10.795 84.495 10.965 ; RECT 83.865 10.795 84.035 10.965 ; + RECT 83.405 10.795 83.575 10.965 ; + RECT 82.945 10.795 83.115 10.965 ; + RECT 82.485 10.795 82.655 10.965 ; + RECT 82.025 10.795 82.195 10.965 ; + RECT 81.565 10.795 81.735 10.965 ; + RECT 81.105 10.795 81.275 10.965 ; + RECT 80.645 10.795 80.815 10.965 ; + RECT 80.185 10.795 80.355 10.965 ; + RECT 79.725 10.795 79.895 10.965 ; + RECT 79.265 10.795 79.435 10.965 ; + RECT 78.805 10.795 78.975 10.965 ; + RECT 78.345 10.795 78.515 10.965 ; + RECT 77.885 10.795 78.055 10.965 ; + RECT 77.425 10.795 77.595 10.965 ; + RECT 76.965 10.795 77.135 10.965 ; + RECT 76.505 10.795 76.675 10.965 ; + RECT 76.045 10.795 76.215 10.965 ; + RECT 75.585 10.795 75.755 10.965 ; + RECT 75.125 10.795 75.295 10.965 ; + RECT 74.665 10.795 74.835 10.965 ; + RECT 74.205 10.795 74.375 10.965 ; + RECT 73.745 10.795 73.915 10.965 ; + RECT 73.285 10.795 73.455 10.965 ; + RECT 72.825 10.795 72.995 10.965 ; + RECT 72.365 10.795 72.535 10.965 ; + RECT 71.905 10.795 72.075 10.965 ; + RECT 71.445 10.795 71.615 10.965 ; + RECT 70.985 10.795 71.155 10.965 ; + RECT 70.525 10.795 70.695 10.965 ; + RECT 70.065 10.795 70.235 10.965 ; + RECT 69.605 10.795 69.775 10.965 ; + RECT 69.145 10.795 69.315 10.965 ; + RECT 68.685 10.795 68.855 10.965 ; + RECT 68.225 10.795 68.395 10.965 ; + RECT 67.765 10.795 67.935 10.965 ; + RECT 67.305 10.795 67.475 10.965 ; + RECT 66.845 10.795 67.015 10.965 ; + RECT 66.385 10.795 66.555 10.965 ; + RECT 65.925 10.795 66.095 10.965 ; + RECT 65.465 10.795 65.635 10.965 ; + RECT 65.005 10.795 65.175 10.965 ; + RECT 64.545 10.795 64.715 10.965 ; + RECT 64.085 10.795 64.255 10.965 ; + RECT 63.625 10.795 63.795 10.965 ; + RECT 63.165 10.795 63.335 10.965 ; + RECT 62.705 10.795 62.875 10.965 ; + RECT 62.245 10.795 62.415 10.965 ; + RECT 61.785 10.795 61.955 10.965 ; + RECT 61.325 10.795 61.495 10.965 ; + RECT 60.865 10.795 61.035 10.965 ; + RECT 60.405 10.795 60.575 10.965 ; + RECT 59.945 10.795 60.115 10.965 ; + RECT 59.485 10.795 59.655 10.965 ; + RECT 59.025 10.795 59.195 10.965 ; + RECT 58.565 10.795 58.735 10.965 ; + RECT 58.105 10.795 58.275 10.965 ; + RECT 57.645 10.795 57.815 10.965 ; + RECT 57.185 10.795 57.355 10.965 ; + RECT 56.725 10.795 56.895 10.965 ; + RECT 56.265 10.795 56.435 10.965 ; + RECT 55.805 10.795 55.975 10.965 ; + RECT 55.345 10.795 55.515 10.965 ; + RECT 54.885 10.795 55.055 10.965 ; + RECT 54.425 10.795 54.595 10.965 ; + RECT 53.965 10.795 54.135 10.965 ; + RECT 53.505 10.795 53.675 10.965 ; + RECT 53.045 10.795 53.215 10.965 ; + RECT 52.585 10.795 52.755 10.965 ; + RECT 52.125 10.795 52.295 10.965 ; + RECT 51.665 10.795 51.835 10.965 ; + RECT 51.205 10.795 51.375 10.965 ; + RECT 50.745 10.795 50.915 10.965 ; + RECT 50.285 10.795 50.455 10.965 ; + RECT 49.825 10.795 49.995 10.965 ; + RECT 49.365 10.795 49.535 10.965 ; + RECT 48.905 10.795 49.075 10.965 ; + RECT 48.445 10.795 48.615 10.965 ; + RECT 47.985 10.795 48.155 10.965 ; + RECT 47.525 10.795 47.695 10.965 ; + RECT 47.065 10.795 47.235 10.965 ; + RECT 46.605 10.795 46.775 10.965 ; + RECT 46.145 10.795 46.315 10.965 ; + RECT 45.685 10.795 45.855 10.965 ; + RECT 45.225 10.795 45.395 10.965 ; + RECT 44.765 10.795 44.935 10.965 ; + RECT 44.305 10.795 44.475 10.965 ; + RECT 43.845 10.795 44.015 10.965 ; + RECT 43.385 10.795 43.555 10.965 ; + RECT 42.925 10.795 43.095 10.965 ; + RECT 42.465 10.795 42.635 10.965 ; + RECT 42.005 10.795 42.175 10.965 ; + RECT 41.545 10.795 41.715 10.965 ; + RECT 41.085 10.795 41.255 10.965 ; + RECT 40.625 10.795 40.795 10.965 ; + RECT 40.165 10.795 40.335 10.965 ; + RECT 39.705 10.795 39.875 10.965 ; + RECT 39.245 10.795 39.415 10.965 ; + RECT 38.785 10.795 38.955 10.965 ; + RECT 38.325 10.795 38.495 10.965 ; + RECT 37.865 10.795 38.035 10.965 ; + RECT 37.405 10.795 37.575 10.965 ; + RECT 36.945 10.795 37.115 10.965 ; + RECT 36.485 10.795 36.655 10.965 ; + RECT 36.025 10.795 36.195 10.965 ; + RECT 35.565 10.795 35.735 10.965 ; + RECT 35.105 10.795 35.275 10.965 ; + RECT 34.645 10.795 34.815 10.965 ; + RECT 34.185 10.795 34.355 10.965 ; + RECT 33.725 10.795 33.895 10.965 ; + RECT 33.265 10.795 33.435 10.965 ; + RECT 32.805 10.795 32.975 10.965 ; + RECT 32.345 10.795 32.515 10.965 ; + RECT 31.885 10.795 32.055 10.965 ; + RECT 31.425 10.795 31.595 10.965 ; + RECT 30.965 10.795 31.135 10.965 ; + RECT 30.505 10.795 30.675 10.965 ; + RECT 30.045 10.795 30.215 10.965 ; + RECT 29.585 10.795 29.755 10.965 ; + RECT 29.125 10.795 29.295 10.965 ; + RECT 28.665 10.795 28.835 10.965 ; + RECT 28.205 10.795 28.375 10.965 ; + RECT 27.745 10.795 27.915 10.965 ; + RECT 27.285 10.795 27.455 10.965 ; + RECT 26.825 10.795 26.995 10.965 ; + RECT 26.365 10.795 26.535 10.965 ; + RECT 25.905 10.795 26.075 10.965 ; + RECT 25.445 10.795 25.615 10.965 ; + RECT 24.985 10.795 25.155 10.965 ; + RECT 24.525 10.795 24.695 10.965 ; + RECT 24.065 10.795 24.235 10.965 ; + RECT 23.605 10.795 23.775 10.965 ; + RECT 23.145 10.795 23.315 10.965 ; + RECT 22.685 10.795 22.855 10.965 ; + RECT 22.225 10.795 22.395 10.965 ; + RECT 21.765 10.795 21.935 10.965 ; + RECT 21.305 10.795 21.475 10.965 ; + RECT 20.845 10.795 21.015 10.965 ; + RECT 20.385 10.795 20.555 10.965 ; + RECT 19.925 10.795 20.095 10.965 ; + RECT 19.465 10.795 19.635 10.965 ; RECT 19.005 10.795 19.175 10.965 ; RECT 18.545 10.795 18.715 10.965 ; - RECT 84.325 8.075 84.495 8.245 ; - RECT 83.865 8.075 84.035 8.245 ; - RECT 19.005 8.075 19.175 8.245 ; - RECT 18.545 8.075 18.715 8.245 ; - RECT 84.325 5.355 84.495 5.525 ; - RECT 83.865 5.355 84.035 5.525 ; - RECT 19.005 5.355 19.175 5.525 ; - RECT 18.545 5.355 18.715 5.525 ; - RECT 84.325 2.635 84.495 2.805 ; - RECT 83.865 2.635 84.035 2.805 ; - RECT 19.005 2.635 19.175 2.805 ; - RECT 18.545 2.635 18.715 2.805 ; + RECT 18.085 10.795 18.255 10.965 ; + RECT 17.625 10.795 17.795 10.965 ; + RECT 17.165 10.795 17.335 10.965 ; + RECT 16.705 10.795 16.875 10.965 ; + RECT 16.245 10.795 16.415 10.965 ; + RECT 15.785 10.795 15.955 10.965 ; + RECT 15.325 10.795 15.495 10.965 ; + RECT 14.865 10.795 15.035 10.965 ; + RECT 14.405 10.795 14.575 10.965 ; + RECT 13.945 10.795 14.115 10.965 ; + RECT 13.485 10.795 13.655 10.965 ; + RECT 13.025 10.795 13.195 10.965 ; + RECT 12.565 10.795 12.735 10.965 ; + RECT 12.105 10.795 12.275 10.965 ; + RECT 11.645 10.795 11.815 10.965 ; + RECT 11.185 10.795 11.355 10.965 ; + RECT 10.725 10.795 10.895 10.965 ; + RECT 10.265 10.795 10.435 10.965 ; + RECT 9.805 10.795 9.975 10.965 ; + RECT 9.345 10.795 9.515 10.965 ; + RECT 8.885 10.795 9.055 10.965 ; + RECT 8.425 10.795 8.595 10.965 ; + RECT 7.965 10.795 8.135 10.965 ; + RECT 7.505 10.795 7.675 10.965 ; + RECT 7.045 10.795 7.215 10.965 ; + RECT 6.585 10.795 6.755 10.965 ; + RECT 6.125 10.795 6.295 10.965 ; + RECT 5.665 10.795 5.835 10.965 ; + RECT 5.205 10.795 5.375 10.965 ; + RECT 4.745 10.795 4.915 10.965 ; + RECT 4.285 10.795 4.455 10.965 ; + RECT 3.825 10.795 3.995 10.965 ; + RECT 3.365 10.795 3.535 10.965 ; + RECT 2.905 10.795 3.075 10.965 ; + RECT 2.445 10.795 2.615 10.965 ; + RECT 1.985 10.795 2.155 10.965 ; + RECT 1.525 10.795 1.695 10.965 ; + RECT 1.065 10.795 1.235 10.965 ; + RECT 0.605 10.795 0.775 10.965 ; + RECT 0.145 10.795 0.315 10.965 ; + RECT 95.365 8.075 95.535 8.245 ; + RECT 94.905 8.075 95.075 8.245 ; + RECT 28.205 8.075 28.375 8.245 ; + RECT 27.745 8.075 27.915 8.245 ; + RECT 95.365 5.355 95.535 5.525 ; + RECT 94.905 5.355 95.075 5.525 ; + RECT 28.205 5.355 28.375 5.525 ; + RECT 27.745 5.355 27.915 5.525 ; + RECT 95.365 2.635 95.535 2.805 ; + RECT 94.905 2.635 95.075 2.805 ; + RECT 28.205 2.635 28.375 2.805 ; + RECT 27.745 2.635 27.915 2.805 ; + RECT 95.365 -0.085 95.535 0.085 ; + RECT 94.905 -0.085 95.075 0.085 ; + RECT 94.445 -0.085 94.615 0.085 ; + RECT 93.985 -0.085 94.155 0.085 ; + RECT 93.525 -0.085 93.695 0.085 ; + RECT 93.065 -0.085 93.235 0.085 ; + RECT 92.605 -0.085 92.775 0.085 ; + RECT 92.145 -0.085 92.315 0.085 ; + RECT 91.685 -0.085 91.855 0.085 ; + RECT 91.225 -0.085 91.395 0.085 ; + RECT 90.765 -0.085 90.935 0.085 ; + RECT 90.305 -0.085 90.475 0.085 ; + RECT 89.845 -0.085 90.015 0.085 ; + RECT 89.385 -0.085 89.555 0.085 ; + RECT 88.925 -0.085 89.095 0.085 ; + RECT 88.465 -0.085 88.635 0.085 ; + RECT 88.005 -0.085 88.175 0.085 ; + RECT 87.545 -0.085 87.715 0.085 ; + RECT 87.085 -0.085 87.255 0.085 ; + RECT 86.625 -0.085 86.795 0.085 ; + RECT 86.165 -0.085 86.335 0.085 ; + RECT 85.705 -0.085 85.875 0.085 ; + RECT 85.245 -0.085 85.415 0.085 ; + RECT 84.785 -0.085 84.955 0.085 ; RECT 84.325 -0.085 84.495 0.085 ; RECT 83.865 -0.085 84.035 0.085 ; RECT 83.405 -0.085 83.575 0.085 ; @@ -1983,55 +2108,45 @@ MACRO sb_2__2_ RECT 28.665 -0.085 28.835 0.085 ; RECT 28.205 -0.085 28.375 0.085 ; RECT 27.745 -0.085 27.915 0.085 ; - RECT 27.285 -0.085 27.455 0.085 ; - RECT 26.825 -0.085 26.995 0.085 ; - RECT 26.365 -0.085 26.535 0.085 ; - RECT 25.905 -0.085 26.075 0.085 ; - RECT 25.445 -0.085 25.615 0.085 ; - RECT 24.985 -0.085 25.155 0.085 ; - RECT 24.525 -0.085 24.695 0.085 ; - RECT 24.065 -0.085 24.235 0.085 ; - RECT 23.605 -0.085 23.775 0.085 ; - RECT 23.145 -0.085 23.315 0.085 ; - RECT 22.685 -0.085 22.855 0.085 ; - RECT 22.225 -0.085 22.395 0.085 ; - RECT 21.765 -0.085 21.935 0.085 ; - RECT 21.305 -0.085 21.475 0.085 ; - RECT 20.845 -0.085 21.015 0.085 ; - RECT 20.385 -0.085 20.555 0.085 ; - RECT 19.925 -0.085 20.095 0.085 ; - RECT 19.465 -0.085 19.635 0.085 ; - RECT 19.005 -0.085 19.175 0.085 ; - RECT 18.545 -0.085 18.715 0.085 ; LAYER via ; - RECT 73.525 81.525 73.675 81.675 ; - RECT 44.085 81.525 44.235 81.675 ; - RECT 42.245 79.825 42.395 79.975 ; - RECT 6.365 17.945 6.515 18.095 ; - RECT 73.525 16.245 73.675 16.395 ; - RECT 44.085 16.245 44.235 16.395 ; - RECT 61.565 1.625 61.715 1.775 ; - RECT 29.365 1.625 29.515 1.775 ; - RECT 73.525 -0.075 73.675 0.075 ; - RECT 44.085 -0.075 44.235 0.075 ; + RECT 83.645 97.845 83.795 97.995 ; + RECT 54.205 97.845 54.355 97.995 ; + RECT 10.045 97.845 10.195 97.995 ; + RECT 9.125 12.505 9.275 12.655 ; + RECT 83.645 10.805 83.795 10.955 ; + RECT 54.205 10.805 54.355 10.955 ; + RECT 10.045 10.805 10.195 10.955 ; + RECT 77.205 1.625 77.355 1.775 ; + RECT 50.525 1.625 50.675 1.775 ; + RECT 83.645 -0.075 83.795 0.075 ; + RECT 54.205 -0.075 54.355 0.075 ; LAYER via2 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 1.28 53.62 1.48 53.82 ; - RECT 1.28 52.26 1.48 52.46 ; - RECT 1.74 48.86 1.94 49.06 ; - RECT 1.28 32.54 1.48 32.74 ; - RECT 1.28 23.02 1.48 23.22 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.28 89.66 1.48 89.86 ; + RECT 1.74 76.74 1.94 76.94 ; + RECT 1.28 75.38 1.48 75.58 ; + RECT 1.74 59.74 1.94 59.94 ; + RECT 1.28 31.86 1.48 32.06 ; + RECT 1.28 30.5 1.48 30.7 ; + RECT 1.28 26.42 1.48 26.62 ; + RECT 1.28 22.34 1.48 22.54 ; + RECT 1.28 17.58 1.48 17.78 ; + RECT 1.28 14.18 1.48 14.38 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER via3 ; - RECT 73.5 81.5 73.7 81.7 ; - RECT 44.06 81.5 44.26 81.7 ; - RECT 1.74 60.42 1.94 60.62 ; - RECT 73.5 -0.1 73.7 0.1 ; - RECT 44.06 -0.1 44.26 0.1 ; + RECT 83.62 97.82 83.82 98.02 ; + RECT 54.18 97.82 54.38 98.02 ; + RECT 10.02 97.82 10.22 98.02 ; + RECT 1.74 57.02 1.94 57.22 ; + RECT 10.02 10.78 10.22 10.98 ; + RECT 83.62 -0.1 83.82 0.1 ; + RECT 54.18 -0.1 54.38 0.1 ; LAYER OVERLAP ; - POLYGON 18.4 0 18.4 16.32 0 16.32 0 81.6 84.64 81.6 84.64 0 ; + POLYGON 27.6 0 27.6 10.88 0 10.88 0 97.92 95.68 97.92 95.68 0 ; END END sb_2__2_ diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef index 429f16f..dd9f950 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:920e17dc24c8c4b732f6bbd636e73e5a2d052c3447b8861c38ccbca598c89f6b -size 726450 +oid sha256:4459f54f80efe83b578590c9748f03265d0ac8d4ed1c7788b3f5572b5b07e375 +size 779620 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef index 6c68408..e520000 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:d692d1e9a27e44a71862c2d1a53b3c01e7db59105a52d0d09be8bd6ca20340c6 -size 1108940 +oid sha256:9cacb82c62dabd60d49e997c2ac82c72c8b6b995fedfda6fc6fbf9fc778e7a79 +size 1156324 diff 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a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__1__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:4d6ccedd49803560b0b7d173ce31dcb33375433b91b7f790684fa34a9be32224 -size 2431409 +oid sha256:c07846a2035d4080078be12c5353ac3f15a6a9543c4391f714d7d299a09ae990 +size 2556291 diff --git a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef index 7e25175..dd7388f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef +++ b/FPGA22_HIER_SKY_PNR/modules/spef/sb_1__2__icv_in_design.nominal_25.spef @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:3a8a55f4f50455ab38135f8ad461314037eb671bd826a81f09180f6b693fb967 -size 1548871 +oid sha256:02dd3c2c6848959f6f7888fa7f779a1b1027702dded883222c7cc7d68be9a0fb +size 1598293 diff --git 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a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.fm.v @@ -4,8 +4,14 @@ // // // -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_5 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14,17 +20,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -32,21 +36,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -56,26 +61,26 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -86,25 +91,31 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_5 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_4 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -118,8 +129,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -127,21 +138,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -151,17 +160,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -169,9 +177,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -182,7 +191,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -190,18 +199,24 @@ logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_4 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_3 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -215,8 +230,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -224,22 +239,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -249,17 +261,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -267,9 +278,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -280,7 +292,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -288,18 +300,24 @@ logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_3 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__direct_interc_2 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -313,8 +331,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -322,22 +340,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -347,17 +362,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -365,9 +379,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -378,7 +393,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -386,24 +401,24 @@ logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc_2 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , + .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc_1 ( in , out ) ; +module cbx_1__0__direct_interc_1 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -417,8 +432,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -429,13 +444,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -451,12 +467,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -464,9 +481,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -477,7 +495,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -486,16 +504,16 @@ logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_1 direct_interc_0_ ( +cbx_1__0__direct_interc_1 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc ( in , out ) ; +module cbx_1__0__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -503,14 +521,14 @@ assign out[0] = in[0] ; endmodule -module direct_interc_0 ( in , out ) ; +module cbx_1__0__direct_interc_0 ( in , out ) ; input [0:0] in ; output [0:0] out ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -524,8 +542,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -536,13 +554,13 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -558,12 +576,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -571,9 +590,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -584,7 +604,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -593,17 +613,17 @@ logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc_0 direct_interc_0_ ( +cbx_1__0__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( { SYNOPSYS_UNCONNECTED_3 } ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_4 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -618,13 +638,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -639,13 +659,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -660,13 +680,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -681,13 +701,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -702,13 +722,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -723,17 +743,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module cbx_1__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -751,7 +771,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1 const1_0_ ( +cbx_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -787,12 +807,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module cbx_1__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -810,7 +830,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +cbx_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -846,12 +866,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module cbx_1__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -869,7 +889,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( +cbx_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -905,12 +925,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module cbx_1__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -928,7 +948,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( +cbx_1__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -964,71 +984,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module cbx_1__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1045,7 +1006,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_0 const1_0_ ( +cbx_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1078,6 +1039,65 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__0__const1_0 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__0__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -1093,7 +1113,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1132,13 +1152,15 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1159,370 +1181,396 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_5 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v index 361d4ae..7bd822e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.lvs.v @@ -4,8 +4,8 @@ // // // -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20,17 +20,15 @@ supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -38,7 +36,6 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; input VDD ; input VSS ; @@ -47,21 +44,21 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -73,19 +70,19 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -93,9 +90,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_me endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -111,25 +109,22 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -149,8 +144,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -158,7 +153,6 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; input VDD ; input VSS ; @@ -167,21 +161,19 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -193,19 +185,19 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -214,9 +206,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -232,7 +225,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -240,19 +233,15 @@ logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -272,8 +261,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -281,7 +270,6 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; input VDD ; input VSS ; @@ -290,21 +278,19 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -316,19 +302,19 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -337,9 +323,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -355,7 +342,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -363,19 +350,15 @@ logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -395,8 +378,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -404,7 +387,6 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; input VDD ; input VSS ; @@ -413,21 +395,19 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -439,19 +419,19 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -460,9 +440,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -478,7 +459,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -486,19 +467,15 @@ logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -518,8 +495,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -535,16 +512,16 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; @@ -564,13 +541,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -579,9 +557,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -597,7 +576,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -606,13 +585,13 @@ logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc ( in , out ) ; +module cbx_1__0__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -620,8 +599,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -641,8 +620,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -658,16 +637,16 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; @@ -687,13 +666,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -702,9 +682,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -720,7 +701,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -729,14 +710,14 @@ logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -760,13 +741,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -790,13 +771,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -820,13 +801,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -850,13 +831,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -880,13 +861,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -910,12 +891,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -977,8 +959,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1040,8 +1022,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1103,8 +1085,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1166,71 +1148,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1288,6 +1207,69 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -1303,7 +1285,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1344,13 +1326,15 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1373,8 +1357,9 @@ supply0 VSS ; // assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -1382,8 +1367,8 @@ mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( + .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , @@ -1391,8 +1376,8 @@ mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , @@ -1400,8 +1385,8 @@ mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , @@ -1409,8 +1394,8 @@ mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , @@ -1418,8 +1403,8 @@ mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_5 ( + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , @@ -1427,364 +1412,399 @@ mux_tree_tapbuf_size10 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1421 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1429 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1477 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , .X ( top_width_0_height_0__pin_5_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , .X ( ropt_net_252 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , .X ( top_width_0_height_0__pin_11_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , .X ( top_width_0_height_0__pin_5_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , .X ( ropt_net_250 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , .X ( ropt_net_256 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , - .X ( ropt_net_238 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -1795,701 +1815,919 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v index db949a5..51c1902 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__0__icv_in_design.pt.v @@ -4,8 +4,8 @@ // // // -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -14,17 +14,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb15_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__70 ( .A ( mem_out[0] ) , - .X ( net_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_114 ( .A ( net_net_114 ) , - .X ( net_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_152 ( .A ( net_net_113 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__70 ( .A ( mem_out[0] ) , + .X ( net_net_109 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_150 ( .A ( net_net_109 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -32,21 +30,22 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__68 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__69 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_144 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_82 ( .A ( FPGA_IN ) , + .X ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_144 ( .A ( BUF_net_82 ) , + .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -56,26 +55,26 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -86,25 +85,22 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -118,8 +114,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__67 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_4 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -127,21 +123,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__65 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__66 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_143 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_4 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -151,17 +145,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_4 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_4 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -169,9 +162,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_4 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__4 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__4 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -182,7 +176,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -190,18 +184,15 @@ logical_tile_io_mode_physical__iopad_4 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -215,8 +206,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__64 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_3 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -224,22 +215,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_17__63 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__62 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__63 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_152 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_3 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -249,17 +237,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_3 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_3 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -267,9 +254,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_3 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__3 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__3 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -280,7 +268,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -288,18 +276,15 @@ logical_tile_io_mode_physical__iopad_3 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -313,8 +298,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__61 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cbx_1__0__EMBEDDED_IO_2 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -322,22 +307,19 @@ output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; output p_abuf0 ; -output p_abuf1 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_14__60 ( .A ( FPGA_DIR ) , - .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_155 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_151 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_2 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , p_abuf0 , p_abuf1 ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -347,17 +329,16 @@ input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_2 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_2 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -365,9 +346,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_2 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__2 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__2 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -378,7 +360,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -386,18 +368,15 @@ logical_tile_io_mode_physical__iopad_2 logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( + .p_abuf0 ( p_abuf0 ) ) ; +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , - .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -411,8 +390,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__58 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_1 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -423,13 +402,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__57 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_154 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__56 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 FTB_11__57 ( .A ( FPGA_DIR ) , + .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_143 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_1 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -445,12 +425,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_1 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_1 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -458,9 +439,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_1 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__1 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__1 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -471,7 +453,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -480,13 +462,13 @@ logical_tile_io_mode_physical__iopad_1 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module direct_interc ( in , out ) ; +module cbx_1__0__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -494,8 +476,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -509,8 +491,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__55 ( .A ( mem_out[0] ) , endmodule -module EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__0__EMBEDDED_IO_0 ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -521,13 +503,13 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__53 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__54 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_142 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad_0 ( prog_clk , +module cbx_1__0__logical_tile_io_mode_physical__iopad_0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -543,12 +525,13 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO_0 EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__0__EMBEDDED_IO_0 EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__0__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .mem_out ( EMBEDDED_IO_0_en ) , @@ -556,9 +539,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_0 EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_ endmodule -module logical_tile_io_mode_io__0 ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__0__logical_tile_io_mode_io__0 ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -569,7 +553,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( +cbx_1__0__logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -578,14 +562,14 @@ logical_tile_io_mode_physical__iopad_0 logical_tile_io_mode_physical__iopad_0 ( .iopad_inpad ( io_inpad ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_1_ ( +cbx_1__0__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -600,13 +584,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -621,13 +605,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -642,13 +626,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -663,13 +647,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -684,13 +668,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__0__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -705,12 +689,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -762,7 +746,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -814,7 +798,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -866,7 +850,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -918,59 +902,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__0__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1018,6 +950,58 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule +module cbx_1__0__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +endmodule + + module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , chanx_left_out , chanx_right_out , bottom_grid_pin_0_ , bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ , @@ -1033,7 +1017,7 @@ module cbx_1__0_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , top_width_0_height_0__pin_7_lower , top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower , top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1072,13 +1056,15 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +wire ropt_net_204 ; +wire ropt_net_209 ; wire ropt_net_188 ; -wire ropt_net_186 ; -wire ropt_net_190 ; -wire ropt_net_184 ; -wire ropt_net_185 ; -wire ropt_net_183 ; +wire ropt_net_197 ; +wire ropt_net_189 ; +wire ropt_net_200 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1099,370 +1085,396 @@ wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__0__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_184 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_1 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_2 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_182 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_3 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_4 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_176 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_5 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_177 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_183 ) ) ; +cbx_1__0__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__0__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__0__mux_tree_tapbuf_size10_mem mem_top_ipin_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( +cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_202 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_211 } ) , .io_outpad ( top_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_12_ } ) , + .io_inpad ( { aps_rename_5_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_1 } ) , - .p_abuf0 ( ropt_net_188 ) ) ; -logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( + .p_abuf0 ( ropt_net_204 ) ) ; +cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_206 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[1] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) , .io_outpad ( top_width_0_height_0__pin_2_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_13_ } ) , + .io_inpad ( { aps_rename_6_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_2 } ) , - .p_abuf0 ( ropt_net_186 ) ) ; -logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( + .p_abuf0 ( ropt_net_209 ) ) ; +cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[2] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_214 } ) , .io_outpad ( top_width_0_height_0__pin_4_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_14_ } ) , + .io_inpad ( { aps_rename_8_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_3 } ) , - .p_abuf0 ( ropt_net_190 ) ) ; -logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( + .p_abuf0 ( ropt_net_188 ) ) ; +cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[3] ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_210 } ) , .io_outpad ( top_width_0_height_0__pin_6_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_15_ } ) , + .io_inpad ( { aps_rename_9_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_4 } ) , - .p_abuf0 ( ropt_net_184 ) ) ; -logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( + .p_abuf0 ( ropt_net_197 ) ) ; +cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[4] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[4] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_201 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_213 } ) , .io_outpad ( top_width_0_height_0__pin_8_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_16_ } ) , + .io_inpad ( { aps_rename_10_ } ) , .ccff_tail ( { SYNOPSYS_UNCONNECTED_5 } ) , - .p_abuf0 ( ropt_net_185 ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( .prog_clk ( prog_clk ) , + .p_abuf0 ( ropt_net_189 ) ) ; +cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__5 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[5] ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[5] ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_194 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_212 } ) , .io_outpad ( top_width_0_height_0__pin_10_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_17_ } ) , - .ccff_tail ( { ropt_net_221 } ) , - .p_abuf0 ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_230 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_176 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , - .HI ( optlc_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_183 ) , - .X ( ropt_net_236 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_184 ) , - .X ( ropt_net_231 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_185 ) , - .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_186 ) , - .X ( ropt_net_245 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_187 ) , + .io_inpad ( { aps_rename_11_ } ) , + .ccff_tail ( { ropt_net_227 } ) , + .p_abuf0 ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , .X ( ropt_net_234 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_188 ) , - .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_190 ) , - .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( BUF_net_111 ) , - .X ( ropt_net_239 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( BUF_net_110 ) , - .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_231 ) , - .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_194 ) , - .X ( ropt_net_247 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_232 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( BUF_net_109 ) , - .X ( ropt_net_246 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_233 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( ropt_net_197 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_254 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_234 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_235 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( ropt_net_199 ) , - .X ( ropt_net_251 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_201 ) , - .X ( ropt_net_252 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_202 ) , - .X ( ropt_net_242 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_236 ) , - .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_237 ) , - .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_238 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_255 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_205 ) , - .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_43__42 ( .A ( aps_rename_14_ ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_44__43 ( .A ( aps_rename_15_ ) , - .X ( ropt_net_237 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_206 ) , - .X ( ropt_net_253 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( chanx_right_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_208 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_212 ) , - .X ( ropt_net_248 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_213 ) , - .X ( ropt_net_244 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_214 ) , - .X ( ropt_net_243 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_239 ) , - .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_92 ( .A ( chanx_left_in[14] ) , - .X ( BUF_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_93 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_240 ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_232 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_241 ) , - .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_216 ) , - .X ( ropt_net_241 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_242 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_217 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_101 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_233 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_102 ( .A ( chanx_right_in[9] ) , - .X ( BUF_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_103 ( .A ( chanx_right_in[10] ) , - .X ( BUF_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_846 ( .A ( ropt_net_243 ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_847 ( .A ( ropt_net_244 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_849 ( .A ( ropt_net_245 ) , - .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_246 ) , - .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_218 ) , - .X ( ropt_net_240 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_109 ( .A ( aps_rename_12_ ) , - .X ( BUF_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_110 ( .A ( aps_rename_13_ ) , - .X ( BUF_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_111 ( .A ( aps_rename_16_ ) , - .X ( BUF_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_219 ) , +sky130_fd_sc_hd__conb_1 optlc_178 ( .LO ( SYNOPSYS_UNCONNECTED_8 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip445 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_243 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_220 ) , - .X ( ropt_net_235 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_221 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_222 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_223 ) , - .X ( ropt_net_249 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_224 ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_225 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_226 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_188 ) , + .X ( top_width_0_height_0__pin_5_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_247 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_248 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_856 ( .A ( ropt_net_249 ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_250 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_866 ( .A ( ropt_net_251 ) , - .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_875 ( .A ( ropt_net_252 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_877 ( .A ( ropt_net_253 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_254 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_255 ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_256 ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_138 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_139 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_140 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_142 ( .A ( chanx_right_in[19] ) , - .X ( ropt_net_257 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_890 ( .A ( ropt_net_257 ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_146 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_250 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_147 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_256 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_148 ( .A ( BUF_net_102 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_189 ) , + .X ( top_width_0_height_0__pin_9_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_190 ) , + .X ( ropt_net_252 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_335780 ( .A ( ctsbuf_net_3187 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_191 ) , + .X ( ropt_net_258 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_878 ( .A ( ropt_net_244 ) , .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_149 ( .A ( BUF_net_103 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_192 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( BUF_net_108 ) , + .X ( ropt_net_257 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_194 ) , + .X ( ropt_net_259 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_239 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_881 ( .A ( ropt_net_245 ) , + .X ( top_width_0_height_0__pin_11_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_882 ( .A ( ropt_net_246 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_195 ) , + .X ( ropt_net_262 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , .X ( ropt_net_238 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_158 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_159 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_161 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_162 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_163 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_164 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_165 ( .A ( BUF_net_92 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_167 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_173 ( .A ( aps_rename_17_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( BUF_net_106 ) , + .X ( top_width_0_height_0__pin_5_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_197 ) , + .X ( top_width_0_height_0__pin_7_upper[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_198 ) , + .X ( top_width_0_height_0__pin_3_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_814 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_200 ) , + .X ( ropt_net_245 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_237 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_884 ( .A ( ropt_net_247 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_248 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_203 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_887 ( .A ( ropt_net_249 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_204 ) , + .X ( top_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_205 ) , + .X ( ropt_net_254 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_206 ) , + .X ( ropt_net_250 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_46__45 ( .A ( aps_rename_11_ ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_47__46 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_888 ( .A ( ropt_net_250 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_270 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_889 ( .A ( ropt_net_251 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_208 ) , + .X ( top_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_252 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_892 ( .A ( ropt_net_253 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_209 ) , + .X ( ropt_net_256 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_92 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_896 ( .A ( ropt_net_254 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_210 ) , + .X ( ropt_net_265 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_898 ( .A ( ropt_net_255 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_900 ( .A ( ropt_net_256 ) , + .X ( top_width_0_height_0__pin_3_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_211 ) , + .X ( ropt_net_271 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_100 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_235 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_902 ( .A ( ropt_net_257 ) , + .X ( top_width_0_height_0__pin_9_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_903 ( .A ( ropt_net_258 ) , + .X ( top_width_0_height_0__pin_11_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_212 ) , + .X ( ropt_net_268 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_904 ( .A ( ropt_net_259 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( aps_rename_6_ ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_106 ( .A ( aps_rename_8_ ) , + .X ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_915 ( .A ( ropt_net_260 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_108 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_213 ) , + .X ( ropt_net_267 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_214 ) , + .X ( ropt_net_272 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_269 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_218 ) , + .X ( ropt_net_255 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_243 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_261 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_266 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_224 ) , + .X ( ropt_net_249 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_225 ) , + .X ( ropt_net_244 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_227 ) , + .X ( ropt_net_264 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_228 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_229 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_230 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_231 ) , + .X ( ropt_net_263 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_134 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_232 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_135 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_260 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_233 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_137 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_236 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_145 ( .A ( aps_rename_3_ ) , + .X ( ropt_net_253 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_855 ( .A ( ropt_net_232 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_233 ) , + .X ( ropt_net_248 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_148 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_149 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_154 ( .A ( chanx_left_in[0] ) , .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_155 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_234 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_917 ( .A ( ropt_net_261 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_858 ( .A ( ropt_net_235 ) , + .X ( ropt_net_251 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_921 ( .A ( ropt_net_262 ) , + .X ( top_width_0_height_0__pin_7_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_160 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_922 ( .A ( ropt_net_263 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_861 ( .A ( ropt_net_236 ) , + .X ( ropt_net_247 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_862 ( .A ( ropt_net_237 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_863 ( .A ( ropt_net_238 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_923 ( .A ( ropt_net_264 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_864 ( .A ( ropt_net_239 ) , + .X ( ropt_net_246 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_924 ( .A ( ropt_net_265 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_168 ( .A ( aps_rename_5_ ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_926 ( .A ( ropt_net_266 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_928 ( .A ( ropt_net_267 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_171 ( .A ( aps_rename_9_ ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_929 ( .A ( ropt_net_268 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_932 ( .A ( ropt_net_269 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_933 ( .A ( ropt_net_270 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_934 ( .A ( ropt_net_271 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_937 ( .A ( ropt_net_272 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[2] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v index d9024d5..136d078 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.fm.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20,13 +20,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41,13 +41,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -62,13 +62,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -83,13 +83,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -104,13 +104,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,13 +125,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -146,13 +146,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -167,17 +167,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module cbx_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -193,7 +193,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1 const1_0_ ( +cbx_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -223,12 +223,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module cbx_1__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -244,7 +244,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14 const1_0_ ( +cbx_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -274,165 +274,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module cbx_1__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -447,7 +294,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10 const1_0_ ( +cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -468,18 +315,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_9 ( const1 ) ; +module cbx_1__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -495,7 +342,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_9 const1_0_ ( +cbx_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -525,12 +372,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_8 ( const1 ) ; +module cbx_1__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -546,7 +393,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_8 const1_0_ ( +cbx_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -576,180 +423,333 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; +module cbx_1__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cbx_1__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -767,7 +767,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7 const1_0_ ( +cbx_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -803,12 +803,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module cbx_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -826,7 +826,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( +cbx_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -862,12 +862,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module cbx_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -885,7 +885,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +cbx_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -921,12 +921,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module cbx_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -944,7 +944,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +cbx_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -980,12 +980,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module cbx_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1003,7 +1003,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( +cbx_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1039,12 +1039,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module cbx_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +cbx_1__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1062,7 +1117,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( +cbx_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1098,12 +1153,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module cbx_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1121,10 +1176,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( +cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1154,65 +1207,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_0 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -1223,8 +1219,8 @@ module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1248,12 +1244,11 @@ output [0:0] bottom_grid_pin_13_ ; output [0:0] bottom_grid_pin_14_ ; output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1306,313 +1301,383 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; + .X ( ropt_net_153 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; + .X ( ropt_net_156 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) ) ; + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) ) ; + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) ) ; + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v index a3a7c08..4491fe9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.lvs.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29,13 +29,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -59,13 +59,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -89,13 +89,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -119,13 +119,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -149,13 +149,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -179,13 +179,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -209,13 +209,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -239,12 +239,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -297,7 +298,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -350,166 +352,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -551,14 +395,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -611,7 +456,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -664,8 +510,170 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -689,13 +697,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -719,13 +727,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -749,13 +757,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -779,13 +787,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -809,13 +817,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -839,13 +847,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -869,13 +877,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -899,13 +907,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -967,8 +975,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1030,8 +1038,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1093,7 +1101,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1155,8 +1164,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1218,8 +1227,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1281,8 +1349,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1304,9 +1372,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1341,69 +1406,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1414,8 +1419,8 @@ module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1439,14 +1444,13 @@ output [0:0] bottom_grid_pin_13_ ; output [0:0] bottom_grid_pin_14_ ; output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1501,16 +1505,16 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , @@ -1518,8 +1522,8 @@ mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , @@ -1527,8 +1531,8 @@ mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , @@ -1536,8 +1540,8 @@ mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , @@ -1545,8 +1549,8 @@ mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , @@ -1554,8 +1558,8 @@ mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , @@ -1563,8 +1567,8 @@ mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , @@ -1572,721 +1576,1099 @@ mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1493 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1499 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v index 0428a39..c728f3e 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__1__icv_in_design.pt.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20,13 +20,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41,13 +41,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -62,13 +62,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -83,13 +83,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -104,13 +104,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,13 +125,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -146,13 +146,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -167,12 +167,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -216,7 +216,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -260,139 +260,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -426,13 +294,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -476,7 +344,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -520,8 +388,140 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -536,13 +536,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 FTB_8__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -557,13 +557,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -578,13 +578,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -599,13 +599,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -620,13 +620,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -641,13 +641,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -662,13 +662,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -683,12 +683,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -740,7 +740,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -792,7 +792,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -844,7 +844,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -896,7 +896,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -948,7 +948,55 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1000,7 +1048,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1018,8 +1066,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1049,58 +1095,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; endmodule @@ -1111,8 +1107,8 @@ module cbx_1__1_ ( prog_clk , chanx_left_in , chanx_right_in , ccff_head , bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ , bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ , bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ , - ccff_tail , CLB_SC_IN , CLB_SC_OUT , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , SC_OUT_BOT , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_left_in ; input [0:19] chanx_right_in ; @@ -1136,12 +1132,11 @@ output [0:0] bottom_grid_pin_13_ ; output [0:0] bottom_grid_pin_14_ ; output [0:0] bottom_grid_pin_15_ ; output [0:0] ccff_tail ; -input CLB_SC_IN ; -output CLB_SC_OUT ; input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1194,313 +1189,383 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( +cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_113 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_3 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_4 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_7 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_11 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_12 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_15 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_108 ) ) ; +cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__1__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , + .out ( { ropt_net_114 } ) , + .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[13] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_107 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_106 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ; +cbx_1__1__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , +cbx_1__1__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( chanx_right_out[1] ) ) ; + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; + .X ( ropt_net_153 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( chanx_right_out[3] ) ) ; + .X ( ropt_net_156 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( ropt_net_105 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_left_in[9] ) , - .X ( aps_rename_6_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_684 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_right_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_142 ) , .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( ropt_net_143 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_107 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_108 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_109 ) ) ; + .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( ropt_net_106 ) , - .X ( chanx_left_out[16] ) ) ; + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip376 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , - .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_107 ) , - .X ( chanx_right_out[8] ) ) ; + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( chanx_left_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_108 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_109 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , - .X ( aps_rename_4_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_65 ( .A ( chanx_left_in[19] ) , - .X ( BUF_net_65 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_68 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chanx_right_in[12] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chanx_right_in[16] ) , - .X ( BUF_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_77 ( .A ( aps_rename_6_ ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chanx_left_in[12] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chanx_left_in[12] ) , .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( BUF_net_65 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( BUF_net_69 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_84 ( .A ( BUF_net_71 ) , - .X ( ropt_net_106 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( CLB_SC_IN ) , - .X ( CLB_SC_OUT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_left_in[11] ) , +sky130_fd_sc_hd__buf_6 cts_buf_326702 ( .A ( ctsbuf_net_1109 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_112 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_113 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_114 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_93 ( .A ( aps_rename_4_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_right_in[19] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_144 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[19] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_right_in[8] ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_145 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_147 ) , + .X ( bottom_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[11] ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( ropt_net_123 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( chanx_right_in[5] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_742 ( .A ( ropt_net_125 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_84 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_148 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( ropt_net_149 ) , + .X ( bottom_grid_pin_1_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_126 ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_152 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_128 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_129 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_130 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_131 ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_132 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_133 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_134 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_137 ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_138 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_154 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_156 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v index cbe5341..123fa91 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,14 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22,15 +28,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -41,14 +47,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -64,21 +70,23 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -89,7 +97,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -97,17 +105,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_0_ ( +cbx_1__2__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cbx_1__2__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -127,8 +135,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -148,8 +156,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -169,8 +177,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -190,8 +198,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -211,8 +219,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -227,13 +235,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -253,8 +261,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -274,12 +282,12 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module const1 ( const1 ) ; +module cbx_1__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -295,7 +303,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1 const1_0_ ( +cbx_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -325,12 +333,267 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15 ( const1 ) ; +module cbx_1__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cbx_1__2__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -345,7 +608,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_15 const1_0_ ( +cbx_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -366,18 +629,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_14 ( const1 ) ; +module cbx_1__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -393,7 +656,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14 const1_0_ ( +cbx_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -423,255 +686,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -686,13 +702,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -712,8 +728,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -733,8 +749,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -754,8 +770,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -775,8 +791,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -796,8 +812,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -817,8 +833,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -833,13 +849,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -854,17 +870,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_8 ( const1 ) ; +module cbx_1__2__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -882,7 +898,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8 const1_0_ ( +cbx_1__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -918,12 +934,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_7 ( const1 ) ; +module cbx_1__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -941,7 +957,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7 const1_0_ ( +cbx_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -977,12 +993,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module cbx_1__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1000,7 +1016,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( +cbx_1__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1036,12 +1052,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module cbx_1__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1059,7 +1075,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +cbx_1__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1095,12 +1111,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module cbx_1__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1118,7 +1134,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +cbx_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1154,12 +1170,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module cbx_1__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1177,7 +1193,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( +cbx_1__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1213,12 +1229,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module cbx_1__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1236,7 +1252,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( +cbx_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1272,12 +1288,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module cbx_1__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1293,12 +1309,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( +cbx_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1324,19 +1337,18 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module const1_0 ( const1 ) ; +module cbx_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1354,7 +1366,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( +cbx_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1437,7 +1449,7 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1492,321 +1504,381 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v index 45f1f14..88acf4a 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28,15 +28,15 @@ supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , VDD , VSS ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -52,16 +52,16 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; @@ -81,13 +81,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -95,9 +96,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_me endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -113,7 +115,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -121,17 +123,14 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_0_ ( +cbx_1__2__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -160,8 +159,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -190,8 +189,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -220,8 +219,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -250,8 +249,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -280,8 +279,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -305,13 +304,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -340,8 +339,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -370,7 +369,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -423,7 +423,278 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -465,14 +736,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -525,265 +797,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -807,13 +822,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -842,8 +857,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -872,8 +887,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -902,8 +917,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -932,8 +947,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -962,8 +977,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -992,8 +1007,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1017,13 +1032,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1047,13 +1062,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1115,8 +1130,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1178,8 +1193,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1241,7 +1256,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1303,8 +1319,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1366,8 +1382,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1429,8 +1445,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1492,8 +1508,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1511,13 +1527,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1548,15 +1560,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1667,7 +1679,7 @@ output SC_OUT_BOT ; input VDD ; input VSS ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1724,7 +1736,7 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -1732,8 +1744,8 @@ mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( top_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , @@ -1741,8 +1753,8 @@ mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , @@ -1750,8 +1762,8 @@ mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , @@ -1759,8 +1771,8 @@ mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , @@ -1768,8 +1780,8 @@ mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , @@ -1777,8 +1789,8 @@ mux_tree_tapbuf_size10 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , @@ -1786,8 +1798,8 @@ mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , @@ -1795,8 +1807,8 @@ mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , @@ -1804,636 +1816,1028 @@ mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1509 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1510 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1511 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1512 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1513 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1514 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1460 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1515 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1516 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1517 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1518 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1519 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , .X ( chanx_left_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , - .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v index bb10d5b..3676d3d 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cbx_1__2__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cbx_1__2__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22,15 +22,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__61 ( .A ( mem_out[0] ) , - .X ( net_aps_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_91 ( .A ( net_aps_61 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__61 ( .A ( mem_out[0] ) , + .X ( net_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( net_net_84 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 ) ; +module cbx_1__2__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -41,14 +41,14 @@ output p_abuf0 ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__59 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; sky130_fd_sc_hd__dlymetal6s6s_1 FTB_19__60 ( .A ( FPGA_DIR ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( p_abuf0 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_105 ( .A ( FPGA_IN ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cbx_1__2__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 ) ; @@ -64,21 +64,23 @@ output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cbx_1__2__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cbx_1__2__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cbx_1__2__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -89,7 +91,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cbx_1__2__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -97,17 +99,14 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -direct_interc direct_interc_0_ ( +cbx_1__2__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( { p_abuf0 } ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -127,8 +126,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__58 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -148,8 +147,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__57 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -169,8 +168,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__56 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -190,8 +189,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__55 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -211,8 +210,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__54 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -227,13 +226,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -253,8 +252,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__52 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -274,7 +273,7 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__51 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -318,7 +317,227 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cbx_1__2__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -352,13 +571,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -402,220 +621,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -630,13 +637,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -656,8 +663,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__49 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -677,8 +684,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__48 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -698,8 +705,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__47 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -719,8 +726,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__46 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -740,8 +747,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__45 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -761,8 +768,8 @@ sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__44 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -777,13 +784,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cbx_1__2__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -798,12 +805,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -855,7 +862,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -907,7 +914,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -959,7 +966,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1011,7 +1018,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1063,7 +1070,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1115,7 +1122,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1167,7 +1174,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1183,10 +1190,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1212,14 +1216,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cbx_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1318,7 +1321,7 @@ input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; -wire p_abuf0 ; +wire ropt_net_123 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; wire [0:3] mux_tree_tapbuf_size10_1_sram ; @@ -1373,321 +1376,381 @@ wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( +cbx_1__2__mux_tree_tapbuf_size10_0 mux_bottom_ipin_0 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( + .out ( top_grid_pin_0_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_0 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_3 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_4 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[5] , chanx_right_in[5] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_7 mux_top_ipin_7 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[8] , chanx_right_in[8] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10 mux_top_ipin_8 ( + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_8 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[9] , chanx_right_in[9] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_11 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[12] , chanx_right_in[12] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_12 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[13] , chanx_right_in[13] , chanx_left_in[17] , chanx_right_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_15 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[4] , chanx_right_in[4] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[16] , chanx_right_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_bottom_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_7 mem_top_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_8 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( .prog_clk ( prog_clk ) , +cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( +cbx_1__2__mux_tree_tapbuf_size8_0 mux_top_ipin_1 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_4 mux_top_ipin_2 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_5 mux_top_ipin_5 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_120 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_6 mux_top_ipin_6 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8 mux_top_ipin_9 ( + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8 mux_top_ipin_9 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[6] , chanx_right_in[6] , chanx_left_in[14] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_1 mux_top_ipin_10 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[7] , chanx_right_in[7] , chanx_left_in[15] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_119 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_2 mux_top_ipin_13 ( .in ( { chanx_left_in[0] , chanx_right_in[0] , chanx_left_in[2] , chanx_right_in[2] , chanx_left_in[10] , chanx_right_in[10] , chanx_left_in[18] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_117 ) ) ; -mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_122 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_3 mux_top_ipin_14 ( .in ( { chanx_left_in[1] , chanx_right_in[1] , chanx_left_in[3] , chanx_right_in[3] , chanx_left_in[11] , chanx_right_in[11] , chanx_left_in[19] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_118 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_121 ) ) ; +cbx_1__2__mux_tree_tapbuf_size8_mem_0 mem_top_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_4 mem_top_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_5 mem_top_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_6 mem_top_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem mem_top_ipin_9 ( .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_1 mem_top_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_2 mem_top_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cbx_1__2__mux_tree_tapbuf_size8_mem_3 mem_top_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_119 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( bottom_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( bottom_width_0_height_0__pin_1_upper ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_117 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[1] ) , - .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_9__8 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_119 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chanx_left_in[19] ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_131 } ) , + .p_abuf0 ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_144 ) , .X ( chanx_left_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , - .X ( chanx_left_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_right_in[8] ) , +sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_119 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_left_in[3] ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_123 ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chanx_left_in[6] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_left_in[7] ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_753 ( .A ( ropt_net_145 ) , + .X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_121 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chanx_left_in[11] ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_124 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chanx_right_in[11] ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_left_in[4] ) , + .X ( chanx_right_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( ropt_net_147 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_128 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_left_in[13] ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_148 ) , + .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__26 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chanx_right_in[7] ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chanx_right_in[9] ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_right_in[10] ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_33__32 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chanx_right_in[14] ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_37__36 ( .A ( chanx_right_in[16] ) , - .X ( chanx_left_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_36__35 ( .A ( chanx_right_in[15] ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chanx_right_in[17] ) , + .X ( aps_rename_2_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_41__40 ( .A ( p_abuf0 ) , - .X ( bottom_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( chanx_right_in[5] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_right_in[7] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_right_in[15] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_right_in[19] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( aps_rename_2_ ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( aps_rename_3_ ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_88 ( .A ( chanx_left_in[9] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_left_in[9] ) , .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_96 ( .A ( chanx_left_in[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_42__41 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_720 ( .A ( chanx_left_in[8] ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_71 ( .A ( chanx_left_in[10] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chanx_left_in[12] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_150 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_134 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chanx_right_in[16] ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_97 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( chanx_right_in[3] ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chanx_right_in[10] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_142 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_151 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_152 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[2] ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_138 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_82 ( .A ( chanx_right_in[19] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_140 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_141 ) , + .X ( chanx_left_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_142 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_143 ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_99 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_100 ( .A ( aps_rename_2_ ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chanx_left_in[1] ) , + .X ( chanx_right_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chanx_left_in[2] ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[3] ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_72 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_111 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_112 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_139 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v index 05bd39d..08c7846 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22,13 +22,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -42,17 +44,17 @@ wire aps_rename_2_ ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 , p_abuf1 ) ; @@ -69,22 +71,24 @@ output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -95,7 +99,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -103,17 +107,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -133,12 +137,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module const1 ( const1 ) ; +module cby_0__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -156,10 +160,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1 const1_0_ ( +cby_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -189,6 +191,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -197,7 +201,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; + right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -212,246 +216,243 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; // -mux_tree_tapbuf_size10 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v index 01a2ce4..6ee7a67 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28,13 +28,15 @@ supply0 VSS ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -52,20 +54,20 @@ supply0 VSS ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 ) ; @@ -86,13 +88,14 @@ wire [0:0] EMBEDDED_IO_0_en ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , @@ -100,9 +103,10 @@ EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_me endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -118,7 +122,7 @@ output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -126,17 +130,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -165,7 +169,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -187,9 +192,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -224,6 +226,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule @@ -232,7 +237,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower , VDD , VSS ) ; + right_width_0_height_0__pin_1_lower , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -249,238 +254,267 @@ output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1521 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1522 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1523 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1524 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1466 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1525 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1467 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1526 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1468 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1527 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1469 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1528 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1470 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1529 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1471 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1530 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1472 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1531 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1473 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1532 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1474 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1533 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1475 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1534 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1476 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1535 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , .X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , .X ( right_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -495,110 +529,84 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y27200 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y54400 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( @@ -607,15 +615,13 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -625,11 +631,23 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -641,30 +659,36 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( @@ -679,29 +703,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -709,39 +735,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -757,29 +781,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -793,75 +823,79 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -883,9 +917,7 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -893,16 +925,12 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( @@ -917,26 +945,30 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( @@ -959,24 +991,22 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( @@ -991,29 +1021,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1031,31 +1067,27 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1071,25 +1103,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1111,32 +1151,24 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( @@ -1151,28 +1183,32 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( @@ -1189,32 +1225,26 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( @@ -1223,39 +1253,41 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1263,137 +1295,141 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1409,35 +1445,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v index 8457822..1000fb9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_0__1__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_0__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -22,13 +22,15 @@ output [0:0] mem_outb ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__44 ( .A ( mem_out[0] ) , + .X ( net_net_89 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_129 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR , p_abuf0 , p_abuf1 ) ; +module cby_0__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , p_abuf1 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; @@ -42,17 +44,17 @@ wire aps_rename_2_ ; assign SOC_OUT = FPGA_OUT ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__42 ( .A ( SOC_IN ) , .X ( p_abuf1 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__43 ( .A ( FPGA_DIR ) , .X ( aps_rename_2_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( aps_rename_2_ ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_45 ( .A ( p_abuf1 ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_87 ( .A ( aps_rename_2_ ) , .X ( SOC_DIR ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_130 ( .A ( p_abuf1 ) , .X ( p_abuf0 ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_0__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , ccff_tail , p_abuf0 , p_abuf1 ) ; @@ -69,22 +71,24 @@ output p_abuf1 ; wire [0:0] EMBEDDED_IO_0_en ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_0__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( +cby_0__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , p_abuf0 ) ; +module cby_0__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -95,7 +99,7 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , @@ -103,17 +107,17 @@ logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) ) ; -direct_interc direct_interc_0_ ( +cby_0__1__direct_interc direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , .out ( { p_abuf1 } ) ) ; -direct_interc direct_interc_1_ ( +cby_0__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_0__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -133,7 +137,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__41 ( .A ( mem_out[3] ) , endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_0__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -151,8 +155,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -182,6 +184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -190,7 +194,7 @@ module cby_0__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper , - right_width_0_height_0__pin_1_lower ) ; + right_width_0_height_0__pin_1_lower , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -205,246 +209,243 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] right_width_0_height_0__pin_0_ ; output [0:0] right_width_0_height_0__pin_1_upper ; output [0:0] right_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; -wire ropt_net_162 ; +wire ropt_net_166 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; // -mux_tree_tapbuf_size10 mux_right_ipin_0 ( +cby_0__1__mux_tree_tapbuf_size10 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_0_ ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , + .out ( { ropt_net_160 } ) , + .p0 ( optlc_net_155 ) ) ; +cby_0__1__mux_tree_tapbuf_size10_mem mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_161 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_159 } ) , .io_outpad ( right_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( { aps_rename_4_ } ) , - .ccff_tail ( { ropt_net_163 } ) , - .p_abuf0 ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( - .A ( chany_bottom_in[13] ) , .X ( ropt_net_230 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chany_bottom_in[4] ) , - .X ( ropt_net_229 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_160 ) , - .X ( ropt_net_227 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_161 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_740 ( .A ( ropt_net_162 ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_163 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chany_bottom_in[7] ) , - .X ( ropt_net_228 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( ropt_net_165 ) , - .X ( ropt_net_222 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( - .A ( chany_bottom_in[11] ) , .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_749 ( .A ( ropt_net_171 ) , - .X ( ropt_net_218 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_173 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_174 ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_175 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_176 ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_177 ) , - .X ( ropt_net_217 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_200 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_178 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_179 ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_180 ) , - .X ( ropt_net_220 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_181 ) , - .X ( ropt_net_221 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_182 ) , - .X ( ropt_net_216 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_183 ) , - .X ( ropt_net_219 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_184 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_763 ( .A ( ropt_net_185 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_186 ) , - .X ( ropt_net_226 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_187 ) , - .X ( ropt_net_223 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_188 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_37__36 ( .A ( chany_top_in[16] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_189 ) , - .X ( ropt_net_225 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_768 ( .A ( ropt_net_190 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_191 ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_192 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_193 ) , - .X ( ropt_net_224 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_194 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_195 ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( ropt_net_201 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( ropt_net_203 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_780 ( .A ( ropt_net_204 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_205 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_206 ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chany_bottom_in[10] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_783 ( .A ( ropt_net_207 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( ropt_net_208 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_210 ) , - .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( ropt_net_211 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( .A ( chany_bottom_in[17] ) , - .X ( BUF_net_64 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( ropt_net_212 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_213 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_214 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_215 ) , - .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_216 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[8] ) , - .X ( BUF_net_72 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( ropt_net_217 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_218 ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_219 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_76 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_220 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_221 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_222 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_223 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( .A ( ropt_net_224 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_225 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_226 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_227 ) , - .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_228 ) , + .io_inpad ( { aps_rename_13_ } ) , + .ccff_tail ( { ropt_net_195 } ) , + .p_abuf0 ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_229 ) , +sky130_fd_sc_hd__buf_2 prog_clk_0__bip423 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1156 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321744 ( .A ( ctsbuf_net_1156 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_201 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_158 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_159 ) , + .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_160 ) , + .X ( left_grid_pin_0_[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_203 ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_91 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_230 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_104 ( .A ( chany_top_in[0] ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_117 ( .A ( aps_rename_4_ ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( chany_top_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_161 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_204 ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_124 ( .A ( chany_bottom_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_125 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_126 ( .A ( chany_bottom_in[2] ) , - .X ( ropt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_127 ( .A ( chany_bottom_in[3] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_129 ( .A ( chany_bottom_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_130 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chany_bottom_in[12] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_135 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_137 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_138 ( .A ( BUF_net_64 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_139 ( .A ( chany_bottom_in[18] ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_143 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_146 ( .A ( BUF_net_72 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_149 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_151 ( .A ( chany_top_in[15] ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_152 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_230 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_165 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_166 ) , + .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_781 ( .A ( chany_top_in[15] ) , + .X ( ropt_net_231 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_782 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_169 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_784 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_785 ( + .A ( chany_bottom_in[10] ) , .X ( ropt_net_229 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_786 ( .A ( ropt_net_172 ) , + .X ( right_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_787 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_818 ( .A ( ropt_net_206 ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_788 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_177 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chany_bottom_in[3] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_180 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_208 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_181 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_182 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_821 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( chany_bottom_in[0] ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_185 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( chany_bottom_in[1] ) , + .X ( BUF_net_49 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_800 ( + .A ( chany_bottom_in[18] ) , .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_801 ( .A ( ropt_net_187 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_53 ( .A ( chany_bottom_in[6] ) , + .X ( BUF_net_53 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chany_bottom_in[7] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chany_bottom_in[8] ) , + .X ( BUF_net_55 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( + .A ( chany_bottom_in[16] ) , .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( chany_bottom_in[11] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_59 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_top_in[19] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_190 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_191 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_192 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_69 ( .A ( chany_top_in[3] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_72 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_76 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_193 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_78 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_79 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_80 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_830 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_831 ( .A ( ropt_net_218 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_194 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_84 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_219 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_195 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_196 ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_197 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_220 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_836 ( .A ( ropt_net_221 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_96 ( .A ( BUF_net_53 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_837 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_224 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_225 ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_101 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_851 ( .A ( ropt_net_226 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_227 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_853 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_229 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_230 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_857 ( .A ( ropt_net_231 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_122 ( .A ( BUF_net_49 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( .A ( BUF_net_55 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_138 ( .A ( chany_bottom_in[15] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_139 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_141 ( .A ( chany_bottom_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_145 ( .A ( chany_top_in[7] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_153 ( .A ( aps_rename_13_ ) , + .X ( ropt_net_172 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v index d08666b..46b8690 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.fm.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20,13 +20,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41,13 +41,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -62,13 +62,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -83,13 +83,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -104,13 +104,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,13 +125,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -146,13 +146,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -167,17 +167,323 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module cby_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +cby_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -192,7 +498,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1 const1_0_ ( +cby_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -219,12 +525,12 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module cby_1__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -240,7 +546,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14 const1_0_ ( +cby_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -270,488 +576,182 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module cby_1__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -769,7 +769,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7 const1_0_ ( +cby_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -805,12 +805,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module cby_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -828,7 +828,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( +cby_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -864,12 +864,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module cby_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -887,7 +887,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +cby_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -923,12 +923,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module cby_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -946,7 +946,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +cby_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -982,12 +982,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module cby_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1005,7 +1005,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( +cby_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1041,12 +1041,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module cby_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1064,7 +1064,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( +cby_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1100,12 +1100,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module cby_1__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1123,7 +1123,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( +cby_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1159,12 +1159,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module cby_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1182,7 +1182,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( +cby_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1224,7 +1224,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1248,6 +1251,10 @@ output [0:0] left_grid_pin_29_ ; output [0:0] left_grid_pin_30_ ; output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1298,323 +1305,350 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v index 6a0c590..40e4c34 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.lvs.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -29,13 +29,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -59,13 +59,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -89,13 +89,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -119,13 +119,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -149,13 +149,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -179,13 +179,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -209,13 +209,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -239,12 +239,337 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -293,7 +618,8 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -346,326 +672,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -689,15 +697,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -721,13 +729,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -751,13 +759,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -781,13 +789,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -811,13 +819,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -841,13 +849,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -871,13 +879,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -901,13 +909,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -969,8 +977,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1032,8 +1040,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1095,7 +1103,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1157,8 +1166,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1220,8 +1229,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1283,8 +1292,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1346,8 +1355,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1415,7 +1424,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , VDD , VSS , + prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1441,6 +1453,10 @@ output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1493,7 +1509,9 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , @@ -1501,8 +1519,8 @@ mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , @@ -1510,8 +1528,8 @@ mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , @@ -1519,8 +1537,8 @@ mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , @@ -1528,8 +1546,8 @@ mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , @@ -1537,8 +1555,8 @@ mux_tree_tapbuf_size10 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , @@ -1546,8 +1564,8 @@ mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , @@ -1555,8 +1573,8 @@ mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , @@ -1564,461 +1582,506 @@ mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1478 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1537 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1479 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1538 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1480 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1539 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1481 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1540 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1482 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1541 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1483 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1542 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1484 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1543 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1485 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1544 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1486 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1545 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1487 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1546 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1488 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1547 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1489 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1548 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1490 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1549 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1491 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1550 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1492 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1551 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2026,245 +2089,255 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x59800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2280,35 +2353,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v index be65117..dcdd6e1 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_1__1__icv_in_design.pt.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -20,13 +20,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -41,13 +41,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -62,13 +62,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -83,13 +83,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -104,13 +104,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__51 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,13 +125,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__50 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -146,13 +146,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__49 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -167,12 +167,276 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__48 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +endmodule + + +module cby_1__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -212,7 +476,7 @@ sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -256,272 +520,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -536,15 +536,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__47 ( .A ( mem_out[3] ) , - .X ( net_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_90 ( .A ( net_net_70 ) , +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( net_net_75 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_103 ( .A ( net_net_75 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -559,13 +559,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__46 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -580,13 +580,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__45 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -601,13 +601,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -622,13 +622,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__43 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -643,13 +643,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__42 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -664,13 +664,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__41 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -685,12 +685,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -742,7 +742,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -794,7 +794,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -846,7 +846,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -898,7 +898,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -950,7 +950,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1002,7 +1002,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1054,7 +1054,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module cby_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1112,7 +1112,10 @@ module cby_1__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ , - left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ) ; + left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , prog_clk__FEEDTHRU_1 , + prog_clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1136,6 +1139,10 @@ output [0:0] left_grid_pin_29_ ; output [0:0] left_grid_pin_30_ ; output [0:0] left_grid_pin_31_ ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1186,323 +1193,350 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; + +cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_3 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_4 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_7 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_11 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_12 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_15 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , - .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , +cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , + .ccff_tail ( { ropt_net_126 } ) , + .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_1__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_98 ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[13] , chany_top_in[13] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_110 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_111 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_109 ) ) ; +cby_1__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , +cby_1__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_bottom_in[0] ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__clkdlybuf4s50_2 prog_clk_0__bip379 ( .A ( prog_clk[0] ) , + .X ( prog_clk__FEEDTHRU_2_0_0 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_108 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_109 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_689 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_115 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_bottom_in[11] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( aps_rename_8_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_121 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_117 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_738 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_top_in[2] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_top_in[3] ) , - .X ( ropt_net_117 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( - .A ( chany_bottom_in[19] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chany_top_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( - .A ( chany_bottom_in[17] ) , .X ( ropt_net_111 ) ) ; + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_330709 ( .A ( prog_clk__FEEDTHRU_2_0_0 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_28__27 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[7] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_30__29 ( .A ( chany_top_in[9] ) , - .X ( aps_rename_1_ ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , - .X ( ropt_net_116 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( + .A ( chany_bottom_in[15] ) , .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_748 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( aps_rename_3_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_35__34 ( .A ( chany_top_in[14] ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_top_in[15] ) , - .X ( aps_rename_3_ ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_699 ( .A ( ropt_net_109 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_113 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_114 ) , - .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_115 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , - .X ( BUF_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_116 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_117 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_63 ( .A ( chany_top_in[0] ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_71 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_73 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( chany_bottom_in[1] ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_bottom_in[7] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_752 ( .A ( ropt_net_123 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_38__37 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[5] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( aps_rename_6_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_126 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_59 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_125 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( .A ( chany_bottom_in[7] ) , + .X ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( chany_bottom_in[11] ) , + .X ( BUF_net_63 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_64 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_72 ( .A ( chany_top_in[15] ) , + .X ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_88 ( .A ( aps_rename_1_ ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( aps_rename_3_ ) , +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( aps_rename_8_ ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_86 ( .A ( BUF_net_72 ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_92 ( .A ( BUF_net_59 ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_91 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_92 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_94 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_96 ( .A ( aps_rename_10_ ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_97 ( .A ( aps_rename_1_ ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_98 ( .A ( aps_rename_3_ ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_99 ( .A ( aps_rename_6_ ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_100 ( .A ( BUF_net_61 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_101 ( .A ( BUF_net_63 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v index 0f65450..8ee40cd 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,40 +12,61 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__direct_interc_0 ( in , out ) ; +input [0:0] in ; +output [0:0] out ; +endmodule + + +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; output [0:0] mem_outb ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; + +wire aps_rename_1_ ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -54,25 +75,27 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -81,33 +104,33 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; -direct_interc direct_interc_0_ ( + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc_0 direct_interc_0_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , + .out ( { SYNOPSYS_UNCONNECTED_2 } ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( + .in ( { SYNOPSYS_UNCONNECTED_3 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -116,19 +139,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -137,19 +160,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -158,19 +181,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -179,19 +202,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -200,19 +223,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -221,19 +244,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -242,19 +265,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -263,23 +286,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module cby_2__1__const1 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -289,8 +312,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -301,8 +325,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -318,20 +342,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15 ( const1 ) ; +module cby_2__1__const1_15 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -341,8 +363,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_15 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -353,8 +376,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -370,20 +393,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module cby_2__1__const1_14 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -393,8 +414,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_14 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -405,8 +427,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -422,20 +444,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module cby_2__1__const1_13 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -445,8 +465,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_13 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -457,8 +478,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -474,20 +495,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module cby_2__1__const1_12 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -497,8 +516,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_12 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -509,8 +529,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -526,20 +546,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_11 ( const1 ) ; +module cby_2__1__const1_11 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -549,8 +567,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_11 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -561,8 +580,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -578,20 +597,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_10 ( const1 ) ; +module cby_2__1__const1_10 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -601,8 +618,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_10 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -613,8 +631,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -630,20 +648,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_9 ( const1 ) ; +module cby_2__1__const1_9 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -653,8 +669,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_9 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -665,8 +682,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -682,16 +699,14 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -700,19 +715,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -721,19 +736,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -742,19 +757,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -763,19 +778,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -784,19 +799,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -805,19 +820,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -826,19 +841,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -847,19 +862,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -868,23 +883,23 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module const1_8 ( const1 ) ; +module cby_2__1__const1_8 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -896,8 +911,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_8 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -914,8 +930,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -931,20 +947,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_7 ( const1 ) ; +module cby_2__1__const1_7 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -956,8 +970,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -974,8 +989,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -991,20 +1006,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module cby_2__1__const1_6 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1016,8 +1029,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_6 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1034,8 +1048,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1051,20 +1065,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module cby_2__1__const1_5 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1076,8 +1088,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_5 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1094,8 +1107,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1111,20 +1124,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module cby_2__1__const1_4 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1136,8 +1147,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1154,8 +1166,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1171,20 +1183,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module cby_2__1__const1_3 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1196,8 +1206,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1214,8 +1225,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1231,20 +1242,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module cby_2__1__const1_2 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1256,8 +1265,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_2 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1274,8 +1284,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1291,20 +1301,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module cby_2__1__const1_1 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1316,8 +1324,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1334,8 +1343,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1351,20 +1360,18 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module cby_2__1__const1_0 ( const1 ) ; output [0:0] const1 ; - -assign const1[0] = 1'b1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1376,8 +1383,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( .const1 ( const1_0_const1 ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +cby_2__1__const1_0 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1394,8 +1402,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1420,7 +1428,8 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1451,6 +1460,7 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1504,275 +1514,349 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v index f319bd8..c6f7761 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,8 +12,8 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -25,33 +25,53 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 , VDD , VSS ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; +input VDD ; +input VSS ; + +supply1 VDD ; +wire aps_rename_1_ ; +supply0 VSS ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail , VDD , VSS ) ; + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -62,28 +82,31 @@ output [0:0] iopad_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; supply1 VDD ; supply0 VSS ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) , .VDD ( VDD ) , + .VSS ( VSS ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) , + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail , VDD , VSS ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , VDD , VSS , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -94,29 +117,27 @@ output [0:0] io_inpad ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output p_abuf0 ; supply1 VDD ; supply0 VSS ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , - .VSS ( VSS ) ) ; -direct_interc direct_interc_0_ ( + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -128,8 +149,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -142,11 +161,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -158,8 +179,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -172,11 +191,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -188,8 +209,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -202,11 +221,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -218,8 +239,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -232,11 +251,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -248,8 +269,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -262,11 +281,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -278,8 +299,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -292,11 +311,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -308,8 +329,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -322,11 +341,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -338,8 +359,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -352,18 +371,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -375,7 +397,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -390,9 +412,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -408,15 +430,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -428,7 +451,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -443,9 +466,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -461,15 +484,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -481,7 +505,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -496,9 +520,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -514,15 +538,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -534,7 +559,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -549,9 +574,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -567,15 +592,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -587,7 +613,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -602,9 +628,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -620,15 +646,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -640,7 +667,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -655,9 +682,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -673,15 +700,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -693,7 +721,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -708,9 +736,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -726,15 +754,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -746,7 +775,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -761,9 +790,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -779,8 +808,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -792,8 +821,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -806,11 +833,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -822,8 +851,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -836,11 +863,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -852,8 +881,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -866,11 +893,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -882,8 +911,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -896,11 +923,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -912,8 +941,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -926,11 +953,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -942,8 +971,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -956,11 +983,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -972,8 +1001,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -986,11 +1013,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1002,8 +1031,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1016,11 +1043,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1032,8 +1061,6 @@ input VSS ; supply1 VDD ; supply0 VSS ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1046,18 +1073,21 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1071,7 +1101,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1093,9 +1123,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1111,15 +1141,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1133,7 +1164,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1155,9 +1186,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1173,15 +1204,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1195,7 +1227,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1217,9 +1249,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1235,15 +1267,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1257,7 +1290,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1279,9 +1312,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1297,15 +1330,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1319,7 +1353,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1341,9 +1375,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1359,15 +1393,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1381,7 +1416,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1403,9 +1438,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1421,15 +1456,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1443,7 +1479,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1465,9 +1501,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1483,15 +1519,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1505,7 +1542,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1527,9 +1564,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1545,15 +1582,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; input VDD ; input VSS ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1567,7 +1605,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -1589,9 +1627,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1617,7 +1655,7 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , - VDD , VSS ) ; + VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1650,6 +1688,7 @@ output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1705,320 +1744,392 @@ supply1 VDD ; supply0 VSS ; // -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1494 ( .VNB ( VSS ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1553 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1495 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1554 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1496 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1555 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1497 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1556 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1498 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1557 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1499 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1558 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1500 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1559 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1501 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1560 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1502 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1561 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1503 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1562 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1504 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1563 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1505 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1564 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1506 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1565 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1507 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1566 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1508 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1567 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( @@ -2027,530 +2138,385 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x289800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x41400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( @@ -2565,35 +2531,35 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v index 4e481d0..9c803e6 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/cby_2__1__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module direct_interc ( in , out ) ; +module cby_2__1__direct_interc ( in , out ) ; input [0:0] in ; output [0:0] out ; @@ -12,40 +12,55 @@ assign out[0] = in[0] ; endmodule -module EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , ccff_head , - ccff_tail , mem_out , mem_outb ) ; +module cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( prog_clk , + ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; output [0:0] mem_outb ; -assign ccff_tail[0] = mem_out[0] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( N_gOb0_mem_outb_0_ ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__60 ( .A ( mem_out[0] ) , + .X ( net_aps_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_75 ( .A ( net_aps_60 ) , + .X ( ccff_tail[0] ) ) ; endmodule -module EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , FPGA_OUT , - FPGA_DIR ) ; +module cby_2__1__EMBEDDED_IO ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN , + FPGA_OUT , FPGA_DIR , p_abuf0 ) ; input SOC_IN ; output SOC_OUT ; output SOC_DIR ; output FPGA_IN ; input FPGA_OUT ; input FPGA_DIR ; +output p_abuf0 ; + +wire aps_rename_1_ ; -assign FPGA_IN = SOC_IN ; assign SOC_OUT = FPGA_OUT ; -assign SOC_DIR = FPGA_DIR ; + +sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__58 ( .A ( SOC_IN ) , .X ( FPGA_IN ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__59 ( .A ( FPGA_DIR ) , + .X ( aps_rename_1_ ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_62 ( .A ( FPGA_IN ) , + .X ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_78 ( .A ( BUF_net_62 ) , + .X ( p_abuf0 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_83 ( .A ( BUF_net_74 ) , + .X ( SOC_DIR ) ) ; endmodule -module logical_tile_io_mode_physical__iopad ( prog_clk , +module cby_2__1__logical_tile_io_mode_physical__iopad ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , iopad_outpad , ccff_head , iopad_inpad , - ccff_tail ) ; + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -54,25 +69,27 @@ input [0:0] iopad_outpad ; input [0:0] ccff_head ; output [0:0] iopad_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; wire [0:0] EMBEDDED_IO_0_en ; -wire [0:0] EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ; -EMBEDDED_IO EMBEDDED_IO_0_ ( .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , +cby_2__1__EMBEDDED_IO EMBEDDED_IO_0_ ( + .SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN[0] ) , .SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT[0] ) , .SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) , .FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) , - .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) ) ; -EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( + .FPGA_DIR ( EMBEDDED_IO_0_en[0] ) , .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , - .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , - .mem_outb ( EMBEDDED_IO_sky130_fd_sc_hd__dfxbp_1_mem_undriven_mem_outb ) ) ; + .ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_0_en ) , + .mem_outb ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; endmodule -module logical_tile_io_mode_io_ ( prog_clk , gfpga_pad_EMBEDDED_IO_SOC_IN , - gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , - io_outpad , ccff_head , io_inpad , ccff_tail ) ; +module cby_2__1__logical_tile_io_mode_io_ ( prog_clk , + gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , + gfpga_pad_EMBEDDED_IO_SOC_DIR , io_outpad , ccff_head , io_inpad , + ccff_tail , p_abuf0 ) ; input [0:0] prog_clk ; input [0:0] gfpga_pad_EMBEDDED_IO_SOC_IN ; output [0:0] gfpga_pad_EMBEDDED_IO_SOC_OUT ; @@ -81,33 +98,30 @@ input [0:0] io_outpad ; input [0:0] ccff_head ; output [0:0] io_inpad ; output [0:0] ccff_tail ; +output p_abuf0 ; -logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( +cby_2__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 ( .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) , - .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ; -direct_interc direct_interc_0_ ( + .iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) ) ; +cby_2__1__direct_interc direct_interc_1_ ( .in ( { SYNOPSYS_UNCONNECTED_1 } ) , - .out ( io_inpad ) ) ; -direct_interc direct_interc_1_ ( - .in ( { SYNOPSYS_UNCONNECTED_2 } ) , .out ( io_outpad ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -116,19 +130,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__57 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -137,19 +151,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__56 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -158,19 +172,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__55 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -179,19 +193,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__54 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -200,19 +214,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__53 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -221,19 +235,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__52 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -242,19 +256,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__51 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -263,16 +277,18 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__50 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_3 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -282,7 +298,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -293,8 +309,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -310,13 +326,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_2 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -326,7 +342,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -337,8 +353,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -354,13 +370,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -370,7 +386,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -381,8 +397,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -398,13 +414,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -414,7 +430,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -425,8 +441,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -442,13 +458,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_6 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -458,7 +474,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -469,8 +485,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -486,13 +502,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_5 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -502,7 +518,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -513,8 +529,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -530,13 +546,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_4 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -546,7 +562,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -557,8 +573,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -574,13 +590,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -590,7 +606,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -601,8 +617,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , @@ -618,16 +634,14 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -636,19 +650,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__49 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -657,19 +671,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__48 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -678,19 +692,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__47 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -699,19 +713,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__46 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -720,19 +734,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__45 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -741,19 +755,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__44 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -762,19 +776,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__43 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -783,19 +797,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__42 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module cby_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; output [0:3] mem_outb ; -assign ccff_tail[0] = mem_out[3] ; - sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , @@ -804,16 +818,18 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -825,7 +841,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -842,8 +858,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -859,13 +875,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -877,7 +893,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -894,8 +910,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -911,13 +927,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -929,7 +945,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -946,8 +962,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -963,13 +979,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -981,7 +997,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -998,8 +1014,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1015,13 +1031,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1033,7 +1049,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1050,8 +1066,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1067,13 +1083,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1085,7 +1101,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1102,8 +1118,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1119,13 +1135,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1137,7 +1153,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1154,8 +1170,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1171,13 +1187,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1189,7 +1205,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1206,8 +1222,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1223,13 +1239,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out ) ; +module cby_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; output [0:0] out ; +input p0 ; -wire [0:0] const1_0_const1 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; @@ -1241,7 +1257,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1258,8 +1274,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( const1_0_const1[0] ) , - .A1 ( in[9] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , @@ -1284,7 +1300,8 @@ module cby_2__1_ ( prog_clk , chany_bottom_in , chany_top_in , ccff_head , left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , gfpga_pad_EMBEDDED_IO_SOC_IN , gfpga_pad_EMBEDDED_IO_SOC_OUT , gfpga_pad_EMBEDDED_IO_SOC_DIR , left_width_0_height_0__pin_0_ , - left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower ) ; + left_width_0_height_0__pin_1_upper , left_width_0_height_0__pin_1_lower , + prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_bottom_in ; input [0:19] chany_top_in ; @@ -1315,6 +1332,7 @@ output [0:0] gfpga_pad_EMBEDDED_IO_SOC_DIR ; input [0:0] left_width_0_height_0__pin_0_ ; output [0:0] left_width_0_height_0__pin_1_upper ; output [0:0] left_width_0_height_0__pin_1_lower ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1368,275 +1386,349 @@ wire [0:0] mux_tree_tapbuf_size8_mem_6_ccff_tail ; wire [0:0] mux_tree_tapbuf_size8_mem_7_ccff_tail ; // -assign chany_bottom_out[0] = chany_top_in[0] ; -assign chany_bottom_out[1] = chany_top_in[1] ; -assign chany_bottom_out[2] = chany_top_in[2] ; -assign chany_bottom_out[3] = chany_top_in[3] ; -assign chany_bottom_out[4] = chany_top_in[4] ; -assign chany_bottom_out[5] = chany_top_in[5] ; -assign chany_bottom_out[6] = chany_top_in[6] ; -assign chany_bottom_out[7] = chany_top_in[7] ; -assign chany_bottom_out[8] = chany_top_in[8] ; -assign chany_bottom_out[9] = chany_top_in[9] ; -assign chany_bottom_out[10] = chany_top_in[10] ; -assign chany_bottom_out[11] = chany_top_in[11] ; -assign chany_bottom_out[12] = chany_top_in[12] ; -assign chany_bottom_out[13] = chany_top_in[13] ; -assign chany_bottom_out[14] = chany_top_in[14] ; -assign chany_bottom_out[15] = chany_top_in[15] ; -assign chany_bottom_out[16] = chany_top_in[16] ; -assign chany_bottom_out[17] = chany_top_in[17] ; -assign chany_bottom_out[18] = chany_top_in[18] ; -assign chany_bottom_out[19] = chany_top_in[19] ; -assign chany_top_out[0] = chany_bottom_in[0] ; -assign chany_top_out[1] = chany_bottom_in[1] ; -assign chany_top_out[2] = chany_bottom_in[2] ; -assign chany_top_out[3] = chany_bottom_in[3] ; -assign chany_top_out[4] = chany_bottom_in[4] ; -assign chany_top_out[5] = chany_bottom_in[5] ; -assign chany_top_out[6] = chany_bottom_in[6] ; -assign chany_top_out[7] = chany_bottom_in[7] ; -assign chany_top_out[8] = chany_bottom_in[8] ; -assign chany_top_out[9] = chany_bottom_in[9] ; -assign chany_top_out[10] = chany_bottom_in[10] ; -assign chany_top_out[11] = chany_bottom_in[11] ; -assign chany_top_out[12] = chany_bottom_in[12] ; -assign chany_top_out[13] = chany_bottom_in[13] ; -assign chany_top_out[14] = chany_bottom_in[14] ; -assign chany_top_out[15] = chany_bottom_in[15] ; -assign chany_top_out[16] = chany_bottom_in[16] ; -assign chany_top_out[17] = chany_bottom_in[17] ; -assign chany_top_out[18] = chany_bottom_in[18] ; -assign chany_top_out[19] = chany_bottom_in[19] ; - -mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( +cby_2__1__mux_tree_tapbuf_size10_0 mux_left_ipin_0 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( right_grid_pin_0_ ) ) ; -mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_0 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( left_grid_pin_16_ ) ) ; -mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_3 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( left_grid_pin_19_ ) ) ; -mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_4 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[5] , chany_top_in[5] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( left_grid_pin_20_ ) ) ; -mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_7 mux_right_ipin_7 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[8] , chany_top_in[8] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( left_grid_pin_23_ ) ) ; -mux_tree_tapbuf_size10 mux_right_ipin_8 ( + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_8 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[9] , chany_top_in[9] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( left_grid_pin_24_ ) ) ; -mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_11 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[12] , chany_top_in[12] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( left_grid_pin_27_ ) ) ; -mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_12 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[13] , chany_top_in[13] , chany_bottom_in[17] , chany_top_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( left_grid_pin_28_ ) ) ; -mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_15 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[4] , chany_top_in[4] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[16] , chany_top_in[16] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( left_grid_pin_31_ ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_left_ipin_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_0 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_3 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_4 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_7 mem_right_ipin_7 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_8 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_11 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_12 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( .prog_clk ( prog_clk ) , +cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .ccff_tail ( { ccff_tail_mid } ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( +cby_2__1__mux_tree_tapbuf_size8_0 mux_right_ipin_1 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( left_grid_pin_17_ ) ) ; -mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_4 mux_right_ipin_2 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( left_grid_pin_18_ ) ) ; -mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_5 mux_right_ipin_5 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( left_grid_pin_21_ ) ) ; -mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_6 mux_right_ipin_6 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_3_sram ) , .sram_inv ( mux_tree_tapbuf_size8_3_sram_inv ) , - .out ( left_grid_pin_22_ ) ) ; -mux_tree_tapbuf_size8 mux_right_ipin_9 ( + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8 mux_right_ipin_9 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[6] , chany_top_in[6] , chany_bottom_in[14] , chany_top_in[14] } ) , .sram ( mux_tree_tapbuf_size8_4_sram ) , .sram_inv ( mux_tree_tapbuf_size8_4_sram_inv ) , - .out ( left_grid_pin_25_ ) ) ; -mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_100 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_1 mux_right_ipin_10 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[7] , chany_top_in[7] , chany_bottom_in[15] , chany_top_in[15] } ) , .sram ( mux_tree_tapbuf_size8_5_sram ) , .sram_inv ( mux_tree_tapbuf_size8_5_sram_inv ) , - .out ( left_grid_pin_26_ ) ) ; -mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_102 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_2 mux_right_ipin_13 ( .in ( { chany_bottom_in[0] , chany_top_in[0] , chany_bottom_in[2] , chany_top_in[2] , chany_bottom_in[10] , chany_top_in[10] , chany_bottom_in[18] , chany_top_in[18] } ) , .sram ( mux_tree_tapbuf_size8_6_sram ) , .sram_inv ( mux_tree_tapbuf_size8_6_sram_inv ) , - .out ( left_grid_pin_29_ ) ) ; -mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_3 mux_right_ipin_14 ( .in ( { chany_bottom_in[1] , chany_top_in[1] , chany_bottom_in[3] , chany_top_in[3] , chany_bottom_in[11] , chany_top_in[11] , chany_bottom_in[19] , chany_top_in[19] } ) , .sram ( mux_tree_tapbuf_size8_7_sram ) , .sram_inv ( mux_tree_tapbuf_size8_7_sram_inv ) , - .out ( left_grid_pin_30_ ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_101 ) ) ; +cby_2__1__mux_tree_tapbuf_size8_mem_0 mem_right_ipin_1 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_4 mem_right_ipin_2 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_5 mem_right_ipin_5 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_6 mem_right_ipin_6 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_3_sram ) , .mem_outb ( mux_tree_tapbuf_size8_3_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem mem_right_ipin_9 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_4_sram ) , .mem_outb ( mux_tree_tapbuf_size8_4_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_1 mem_right_ipin_10 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_4_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_5_sram ) , .mem_outb ( mux_tree_tapbuf_size8_5_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_2 mem_right_ipin_13 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_6_sram ) , .mem_outb ( mux_tree_tapbuf_size8_6_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , - .ccff_tail ( { ccff_tail_mid } ) , +cby_2__1__mux_tree_tapbuf_size8_mem_3 mem_right_ipin_14 ( + .prog_clk ( prog_clk ) , + .ccff_head ( mux_tree_tapbuf_size8_mem_6_ccff_tail ) , + .ccff_tail ( mux_tree_tapbuf_size8_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_7_sram ) , .mem_outb ( mux_tree_tapbuf_size8_7_sram_inv ) ) ; -logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .prog_clk ( prog_clk ) , +cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( + .prog_clk ( prog_clk ) , .gfpga_pad_EMBEDDED_IO_SOC_IN ( gfpga_pad_EMBEDDED_IO_SOC_IN ) , - .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , - .gfpga_pad_EMBEDDED_IO_SOC_DIR ( { ropt_net_41 } ) , + .gfpga_pad_EMBEDDED_IO_SOC_OUT ( gfpga_pad_EMBEDDED_IO_SOC_OUT ) , + .gfpga_pad_EMBEDDED_IO_SOC_DIR ( gfpga_pad_EMBEDDED_IO_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_upper ) , - .ccff_tail ( { ropt_net_42 } ) ) ; -sky130_fd_sc_hd__buf_4 FTB_41__40 ( - .A ( left_width_0_height_0__pin_1_upper[0] ) , - .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_731 ( .A ( ropt_net_41 ) , - .X ( gfpga_pad_EMBEDDED_IO_SOC_DIR[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_732 ( .A ( ropt_net_42 ) , + .io_inpad ( { aps_rename_4_ } ) , + .ccff_tail ( { ropt_net_107 } ) , + .p_abuf0 ( left_width_0_height_0__pin_1_upper[0] ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip369 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1103 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_bottom_in[1] ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_bottom_in[2] ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_4__3 ( .A ( chany_bottom_in[3] ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_5__4 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chany_bottom_in[5] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_104 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_8__7 ( .A ( chany_bottom_in[7] ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_11__10 ( .A ( chany_bottom_in[10] ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_321690 ( .A ( ctsbuf_net_1103 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[13] ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_105 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_16__15 ( .A ( chany_bottom_in[15] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_18__17 ( .A ( chany_bottom_in[17] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_19__18 ( .A ( chany_bottom_in[18] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_20__19 ( .A ( chany_bottom_in[19] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_21__20 ( .A ( chany_top_in[0] ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_top_in[1] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_23__22 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__23 ( .A ( chany_top_in[3] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_25__24 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__25 ( .A ( chany_top_in[5] ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_106 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_107 ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_30__29 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_31__30 ( .A ( chany_top_in[10] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_32__31 ( .A ( chany_top_in[11] ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( chany_top_in[12] ) , + .X ( chany_bottom_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_top_in[16] ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chany_top_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_41__40 ( .A ( aps_rename_4_ ) , + .X ( aps_rename_5_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_66 ( .A ( chany_bottom_in[8] ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_67 ( .A ( chany_bottom_in[9] ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chany_top_in[17] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_73 ( .A ( aps_rename_5_ ) , + .X ( left_width_0_height_0__pin_1_lower[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chany_bottom_in[0] ) , + .X ( chany_top_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_80 ( .A ( aps_rename_3_ ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_85 ( .A ( chany_bottom_in[11] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[14] ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_88 ( .A ( chany_top_in[15] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_89 ( .A ( chany_bottom_in[12] ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_90 ( .A ( chany_top_in[8] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_93 ( .A ( chany_bottom_in[6] ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_94 ( .A ( chany_top_in[6] ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_95 ( .A ( chany_top_in[7] ) , + .X ( chany_bottom_out[7] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v index 5d2854f..e4304d9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,8 +23,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -42,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -61,8 +61,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -80,12 +80,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module const1 ( const1 ) ; +module sb_0__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -97,7 +97,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1 const1_0_ ( +sb_0__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -115,12 +115,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18 ( const1 ) ; +module sb_0__0__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -132,7 +132,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18 const1_0_ ( +sb_0__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -150,12 +150,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17 ( const1 ) ; +module sb_0__0__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -167,42 +167,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_16 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_16 const1_0_ ( +sb_0__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -220,8 +185,39 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_0__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -234,13 +230,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -256,8 +252,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -273,8 +269,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -290,8 +286,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -307,8 +303,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -324,8 +320,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -341,8 +337,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -358,8 +354,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -375,8 +371,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -392,8 +388,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -409,8 +405,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -426,8 +422,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -443,7 +439,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -460,8 +456,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -477,8 +473,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -494,12 +490,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module const1_15 ( const1 ) ; +module sb_0__0__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -509,7 +505,88 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15 const1_0_ ( +sb_0__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -521,12 +598,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14 ( const1 ) ; +module sb_0__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -536,34 +613,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13 const1_0_ ( +sb_0__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -575,12 +625,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12 ( const1 ) ; +module sb_0__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -590,7 +640,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12 const1_0_ ( +sb_0__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -602,12 +652,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11 ( const1 ) ; +module sb_0__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -617,7 +667,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_11 const1_0_ ( +sb_0__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -629,12 +679,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_10 ( const1 ) ; +module sb_0__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -644,7 +694,61 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_10 const1_0_ ( +sb_0__0__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_7 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__const1_6 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -656,12 +760,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_9 ( const1 ) ; +module sb_0__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -671,7 +775,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_9 const1_0_ ( +sb_0__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -683,12 +787,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_8 ( const1 ) ; +module sb_0__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -698,7 +802,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_8 const1_0_ ( +sb_0__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -710,12 +814,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_7 ( const1 ) ; +module sb_0__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -725,7 +829,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_7 const1_0_ ( +sb_0__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -737,12 +841,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6 ( const1 ) ; +module sb_0__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -752,7 +856,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_6 const1_0_ ( +sb_0__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -764,12 +868,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_5 ( const1 ) ; +module sb_0__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -779,7 +883,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_5 const1_0_ ( +sb_0__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -791,12 +895,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_4 ( const1 ) ; +module sb_0__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -806,115 +910,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_4 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_3 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_3 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_0 const1_0_ ( +sb_0__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -1007,303 +1003,344 @@ wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; // -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , .X ( chanx_right_out[18] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v index 02aaba8..806c3e5 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -31,8 +31,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -58,8 +58,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -85,8 +85,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -112,7 +112,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -147,7 +148,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -182,42 +184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -252,8 +220,40 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -273,13 +273,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -302,8 +302,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -326,8 +326,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -350,8 +350,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -374,8 +374,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -398,8 +398,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -422,8 +422,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -446,8 +446,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -470,8 +470,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -494,8 +494,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -518,8 +518,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -542,8 +542,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -566,7 +566,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -590,8 +590,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -614,8 +614,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -638,8 +638,89 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -665,33 +746,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -717,7 +773,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -743,7 +800,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -769,7 +827,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -795,7 +908,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -821,7 +935,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -847,7 +962,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -873,7 +989,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -899,7 +1016,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -925,115 +1043,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1144,427 +1155,511 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1219 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1128 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1220 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1129 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1221 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1130 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1222 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1131 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1223 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1132 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1224 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1133 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1225 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1134 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1226 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1135 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1136 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1137 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1138 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1139 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1140 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1141 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1142 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1143 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1144 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1145 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1146 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1147 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1148 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1149 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1150 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1151 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1152 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1153 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1154 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1155 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1156 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1157 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1158 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1159 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1160 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1161 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1162 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1163 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1580,46 +1675,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( @@ -1634,41 +1729,53 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1688,89 +1795,95 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y108800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1794,35 +1907,37 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1838,27 +1953,49 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1882,30 +2019,40 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( @@ -1920,22 +2067,48 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( @@ -1948,36 +2121,52 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( @@ -1992,35 +2181,43 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2032,31 +2229,51 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2066,37 +2283,47 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2116,25 +2343,31 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2146,33 +2379,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2184,40 +2423,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( @@ -2228,28 +2473,26 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( @@ -2262,37 +2505,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2302,45 +2541,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2352,103 +2591,127 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2458,95 +2721,91 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2554,37 +2813,43 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2598,44 +2863,80 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( @@ -2644,27 +2945,101 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2682,33 +3057,253 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v index 2edde34..753dbe4 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__0__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,8 +23,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -42,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -61,8 +61,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -80,7 +80,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -108,7 +108,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -136,35 +136,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_45 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -192,8 +164,32 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -206,13 +202,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__35 ( .A ( mem_out[1] ) , .X ( net_aps_35 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_92 ( .A ( net_aps_35 ) , +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_63 ( .A ( net_aps_35 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -228,8 +224,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -245,8 +241,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -262,8 +258,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -279,8 +275,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -296,8 +292,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -313,8 +309,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -330,8 +326,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -347,8 +343,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -364,8 +360,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -381,8 +377,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -398,8 +394,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -415,7 +411,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -432,8 +428,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -449,8 +445,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -466,7 +462,67 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_86 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_84 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -486,27 +542,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_83 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -526,7 +562,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -546,7 +582,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -566,7 +602,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -586,7 +662,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -606,7 +682,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -626,7 +702,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -646,7 +722,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -666,7 +742,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -686,87 +762,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -867,303 +863,344 @@ wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ; wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ; // -mux_tree_tapbuf_size2_12 mux_top_track_0 ( +sb_0__0__mux_tree_tapbuf_size2_12 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_14 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[5] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_13 mux_top_track_24 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_0 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_1 mux_right_track_12 ( .in ( { chany_top_in[5] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_2 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_16 ( + .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_3 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_18 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_101 } ) , + .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_4 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_24 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_100 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_26 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_32 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_103 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_106 } ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_34 ( + .out ( { ropt_net_107 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , + .out ( { ropt_net_106 } ) , + .p0 ( optlc_net_97 ) ) ; +sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , - .ccff_tail ( { ropt_net_110 } ) , + .ccff_tail ( { ropt_net_102 } ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_0 ( +sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( { ropt_net_118 } ) , - .p0 ( optlc_net_103 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_right_track_6 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_99 ) ) ; +sb_0__0__mux_tree_tapbuf_size4 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_98 ) ) ; +sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[18] ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[0] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_125 ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_105 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_126 ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_106 ) , - .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( ropt_net_129 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_691 ( .A ( ropt_net_107 ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_692 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_110 ) , - .X ( ropt_net_129 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_47 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( ropt_net_131 ) , - .X ( chanx_right_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( ropt_net_132 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_111 ) , - .X ( ropt_net_127 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_696 ( .A ( chanx_right_in[17] ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_58 ( .A ( chanx_right_in[15] ) , - .X ( BUF_net_58 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_61 ( .A ( chanx_right_in[19] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( chanx_right_in[16] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_67 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( chanx_right_in[18] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_700 ( .A ( chanx_right_in[4] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_118 ) , - .X ( ropt_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_78 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_80 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chanx_right_in[14] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_703 ( .A ( ropt_net_119 ) , - .X ( ropt_net_126 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_86 ( .A ( chanx_right_in[7] ) , +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_126 ) , .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_704 ( .A ( ropt_net_120 ) , +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_127 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_99 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_100 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_128 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_701 ( .A ( ropt_net_101 ) , .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_89 ( .A ( BUF_net_58 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_702 ( .A ( ropt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_103 ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_105 ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_122 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_706 ( .A ( ropt_net_106 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( ropt_net_107 ) , + .X ( chanx_right_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_708 ( .A ( ropt_net_108 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_709 ( .A ( chanx_right_in[18] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_right_in[16] ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_710 ( .A ( chanx_right_in[12] ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[19] ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chany_top_in[10] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_714 ( .A ( chanx_right_in[15] ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_129 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_53 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_54 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_55 ( .A ( chanx_right_in[7] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_56 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_57 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_130 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_131 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_119 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_115 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( BUF_net_50 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_116 ) , + .X ( ropt_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_77 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_78 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_118 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_79 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_115 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_81 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_105 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_87 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_117 ) , + .X ( ropt_net_126 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_118 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_119 ) , .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_707 ( .A ( ropt_net_123 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_120 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_121 ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_122 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_123 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_139 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_739 ( .A ( ropt_net_140 ) , .X ( chanx_right_out[18] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v index bb44fad..073bb51 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21,8 +21,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -38,8 +38,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -55,8 +55,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -72,8 +72,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -89,8 +89,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -106,12 +106,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module const1 ( const1 ) ; +module sb_0__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -121,7 +121,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1 const1_0_ ( +sb_0__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -133,12 +133,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_31 ( const1 ) ; +module sb_0__1__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -148,7 +148,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31 const1_0_ ( +sb_0__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -160,12 +160,58 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30 ( const1 ) ; +module sb_0__1__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__1__const1_29 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_28 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -175,7 +221,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30 const1_0_ ( +sb_0__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -187,12 +233,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29 ( const1 ) ; +module sb_0__1__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -202,7 +248,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29 const1_0_ ( +sb_0__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -214,62 +260,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -281,13 +273,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -304,8 +296,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -321,8 +313,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -338,8 +330,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -355,12 +347,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module const1_26 ( const1 ) ; +module sb_0__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -371,7 +363,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_26 const1_0_ ( +sb_0__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -386,12 +378,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_25 ( const1 ) ; +module sb_0__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -402,7 +394,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_25 const1_0_ ( +sb_0__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -417,12 +409,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_24 ( const1 ) ; +module sb_0__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -433,7 +425,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24 const1_0_ ( +sb_0__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -448,12 +440,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23 ( const1 ) ; +module sb_0__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -464,7 +456,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23 const1_0_ ( +sb_0__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -479,12 +471,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22 ( const1 ) ; +module sb_0__1__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -495,7 +487,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22 const1_0_ ( +sb_0__1__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -510,7 +502,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -529,8 +521,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -548,8 +540,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -567,12 +559,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module const1_21 ( const1 ) ; +module sb_0__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -587,7 +579,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_21 const1_0_ ( +sb_0__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -614,12 +606,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_20 ( const1 ) ; +module sb_0__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -634,7 +626,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_20 const1_0_ ( +sb_0__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -661,12 +653,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_19 ( const1 ) ; +module sb_0__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -681,7 +673,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_19 const1_0_ ( +sb_0__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -708,8 +700,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -727,8 +719,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -746,8 +738,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -765,8 +757,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -784,8 +776,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -803,7 +795,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -822,8 +814,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -841,12 +833,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module const1_18 ( const1 ) ; +module sb_0__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -858,7 +850,42 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18 const1_0_ ( +sb_0__1__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sb_0__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -876,12 +903,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17 ( const1 ) ; +module sb_0__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -893,7 +920,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17 const1_0_ ( +sb_0__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -911,12 +938,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_16 ( const1 ) ; +module sb_0__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -928,42 +955,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_16 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -const1_15 const1_0_ ( +sb_0__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -981,12 +973,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module sb_0__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -998,7 +990,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_14 const1_0_ ( +sb_0__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -1016,12 +1008,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module sb_0__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1033,7 +1025,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_13 const1_0_ ( +sb_0__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -1051,12 +1043,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module sb_0__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1068,7 +1060,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_12 const1_0_ ( +sb_0__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -1086,8 +1078,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1105,8 +1097,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1124,8 +1116,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1143,8 +1135,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1162,7 +1154,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1181,12 +1173,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module const1_11 ( const1 ) ; +module sb_0__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1199,7 +1191,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_11 const1_0_ ( +sb_0__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1220,12 +1212,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10 ( const1 ) ; +module sb_0__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1238,7 +1230,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_10 const1_0_ ( +sb_0__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1259,12 +1251,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9 ( const1 ) ; +module sb_0__1__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1277,7 +1269,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_9 const1_0_ ( +sb_0__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1298,12 +1290,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8 ( const1 ) ; +module sb_0__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1316,7 +1308,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_8 const1_0_ ( +sb_0__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1337,12 +1329,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_7 ( const1 ) ; +module sb_0__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1355,7 +1347,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_7 const1_0_ ( +sb_0__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1376,8 +1368,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1395,8 +1387,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1414,8 +1406,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1433,8 +1425,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1452,7 +1444,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1471,8 +1463,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1490,8 +1482,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1509,12 +1501,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module const1_6 ( const1 ) ; +module sb_0__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1528,7 +1520,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_6 const1_0_ ( +sb_0__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1552,12 +1544,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module sb_0__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1571,7 +1563,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_5 const1_0_ ( +sb_0__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1595,12 +1587,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_0__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1614,7 +1606,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_4 const1_0_ ( +sb_0__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1638,12 +1630,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module sb_0__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1657,7 +1649,52 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_3 const1_0_ ( +sb_0__1__const1_3 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__const1_2 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1681,12 +1718,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_0__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1700,7 +1737,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_2 const1_0_ ( +sb_0__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1724,12 +1761,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module sb_0__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1743,50 +1780,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module const1_0 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -const1_0 const1_0_ ( +sb_0__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1816,7 +1810,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -1836,6 +1830,7 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -1937,467 +1932,543 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_36 ( + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v index 0af336e..6a29590 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -28,8 +28,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -52,8 +52,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -76,8 +76,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -100,8 +100,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -124,8 +124,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -148,7 +148,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -174,7 +175,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -200,7 +202,54 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -226,7 +275,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -252,60 +302,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -324,13 +322,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -354,8 +352,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -378,8 +376,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -402,8 +400,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -426,7 +424,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -457,7 +456,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -488,7 +488,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -519,7 +520,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -550,7 +552,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -581,7 +584,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -608,8 +611,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -635,8 +638,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -662,7 +665,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -711,7 +715,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -760,7 +765,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -809,8 +815,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -836,8 +842,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -863,8 +869,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -890,8 +896,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -917,8 +923,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -944,7 +950,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -971,8 +977,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -998,7 +1004,44 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1033,7 +1076,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1068,42 +1112,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1138,7 +1148,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1173,7 +1184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1208,7 +1220,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1243,8 +1256,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1270,8 +1283,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1297,8 +1310,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1324,8 +1337,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1351,7 +1364,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1378,7 +1391,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1418,7 +1432,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1458,7 +1473,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1498,7 +1514,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1538,7 +1555,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1578,8 +1596,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1605,8 +1623,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1632,8 +1650,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1659,8 +1677,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1686,7 +1704,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1713,8 +1731,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1740,8 +1758,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1767,7 +1785,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1811,7 +1830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1855,7 +1875,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1899,7 +1920,55 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1943,7 +2012,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1987,51 +2057,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -2081,7 +2108,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail , VDD , VSS ) ; + chany_bottom_out , ccff_tail , VDD , VSS , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -2103,6 +2130,7 @@ output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -2206,263 +2234,278 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , @@ -2470,314 +2513,413 @@ mux_tree_tapbuf_size7_1 mux_right_track_4 ( .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_36 ( + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1165 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1166 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1167 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1168 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1240 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1169 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1170 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1171 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1172 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1173 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1174 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1175 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1176 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1177 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1178 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1179 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1180 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1181 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1182 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1183 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1184 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1185 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1186 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1187 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1188 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1189 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1190 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1191 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1192 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1193 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1194 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1195 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1196 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1197 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1198 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1199 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1200 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1201 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1202 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , - .X ( ropt_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( @@ -2786,263 +2928,341 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x174800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3050,339 +3270,409 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x133400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3390,517 +3680,717 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x423200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y816000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y870400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y924800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3910,41 +4400,147 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v index b7ded23..541c426 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__1__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -21,8 +21,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -38,8 +38,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -55,8 +55,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -72,8 +72,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -89,8 +89,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -106,7 +106,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -126,7 +126,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -146,7 +146,39 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -166,7 +198,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -186,48 +218,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -239,13 +231,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__53 ( .A ( mem_out[1] ) , - .X ( net_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_82 ( .A ( net_net_82 ) , + .X ( net_aps_53 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_114 ( .A ( net_aps_53 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -262,8 +254,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -279,8 +271,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -296,8 +288,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -313,7 +305,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -337,7 +329,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -361,7 +353,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -385,7 +377,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -409,7 +401,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -433,7 +425,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -452,8 +444,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -471,8 +463,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -490,7 +482,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -530,7 +522,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -570,7 +562,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -610,8 +602,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -629,8 +621,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -648,8 +640,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__44 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -667,8 +659,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -686,8 +678,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -705,7 +697,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -724,8 +716,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size4_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -743,7 +735,35 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -771,7 +791,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -799,35 +819,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_64 ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -855,7 +847,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -883,7 +875,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -911,7 +903,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size4_5 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -939,8 +931,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -958,8 +950,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -977,8 +969,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -996,8 +988,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size5_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1015,7 +1007,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1034,7 +1026,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1066,7 +1058,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1098,7 +1090,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1130,7 +1122,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5_3 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1162,7 +1154,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1194,8 +1186,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1213,8 +1205,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1232,8 +1224,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1251,8 +1243,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1270,7 +1262,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1289,8 +1281,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1308,8 +1300,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__1__mux_tree_tapbuf_size6_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1327,7 +1319,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__27 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1363,7 +1355,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1399,7 +1391,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1435,7 +1427,45 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_60 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( BUF_net_60 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( BUF_net_60 ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1471,7 +1501,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1507,43 +1537,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size6_4 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1585,7 +1579,7 @@ module sb_0__1_ ( prog_clk , chany_top_in , top_left_grid_pin_1_ , right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ , right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ , chany_bottom_in , bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , ccff_tail ) ; + chany_bottom_out , ccff_tail , prog_clk__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_1_ ; @@ -1605,6 +1599,7 @@ output [0:19] chany_top_out ; output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; wire [0:1] mux_tree_tapbuf_size2_0_sram_inv ; @@ -1706,467 +1701,543 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // -mux_tree_tapbuf_size6_4 mux_top_track_0 ( +sb_0__1__mux_tree_tapbuf_size6_4 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] , chany_bottom_in[2] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_5 mux_top_track_4 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_5 mux_top_track_4 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , chany_bottom_in[5] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_8 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] , chany_bottom_in[6] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size6_3 mux_right_track_0 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_0 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , + .out ( { ropt_net_137 } ) , + .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( mux_tree_tapbuf_size6_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[3] , chanx_right_in[10] , chanx_right_in[17] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( mux_tree_tapbuf_size6_5_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( mux_tree_tapbuf_size6_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_4_sram ) , .mem_outb ( mux_tree_tapbuf_size6_4_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_5_sram ) , .mem_outb ( mux_tree_tapbuf_size6_5_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_6_sram ) , .mem_outb ( mux_tree_tapbuf_size6_6_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_top_track_2 ( +sb_0__1__mux_tree_tapbuf_size5 mux_top_track_2 ( .in ( { chanx_right_in[2] , chanx_right_in[9] , chanx_right_in[16] , chany_bottom_in[4] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size5_3 mux_top_track_16 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_16 ( .in ( { chanx_right_in[5] , chanx_right_in[12] , chanx_right_in[19] , chany_bottom_in[8] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_2 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[18] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( mux_tree_tapbuf_size5_4_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size5_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_4_sram ) , .mem_outb ( mux_tree_tapbuf_size5_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_5 mux_top_track_24 ( +sb_0__1__mux_tree_tapbuf_size4_5 mux_top_track_24 ( .in ( { chanx_right_in[6] , chanx_right_in[13] , chany_bottom_in[9] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4 mux_top_track_32 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size4 mux_top_track_32 ( .in ( { chanx_right_in[0] , chanx_right_in[7] , chanx_right_in[14] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_4 mux_right_track_8 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[7] , chany_top_in[8] , right_bottom_grid_pin_34_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_right_track_10 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_0 mux_right_track_10 ( .in ( { chany_top_in[9] , chany_top_in[11] , right_bottom_grid_pin_35_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_1 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_1 mux_right_track_12 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_36_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , - .out ( { ropt_net_130 } ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_2 mux_right_track_14 ( + .sram_inv ( mux_tree_tapbuf_size4_4_sram_inv ) , + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_14 ( .in ( { chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( mux_tree_tapbuf_size4_5_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size4_3 mux_right_track_24 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_131 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_24 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_34_[0] , chany_bottom_in[18] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size4_6_sram_inv ) , + .out ( { ropt_net_136 } ) , + .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_4_sram ) , .mem_outb ( mux_tree_tapbuf_size4_4_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_5_sram ) , .mem_outb ( mux_tree_tapbuf_size4_5_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_6_sram ) , .mem_outb ( mux_tree_tapbuf_size4_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_0 mux_right_track_2 ( +sb_0__1__mux_tree_tapbuf_size7_0 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size7_1 mux_right_track_4 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_6 ( +sb_0__1__mux_tree_tapbuf_size7 mux_right_track_6 ( .in ( { chany_top_in[3] , chany_top_in[6] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_128 ) ) ; +sb_0__1__mux_tree_tapbuf_size7_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem_1 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size7_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_1 mux_right_track_16 ( +sb_0__1__mux_tree_tapbuf_size3_1 mux_right_track_16 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_38_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3_2 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_18 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_39_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size3_3 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_20 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_40_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size3 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size3 mux_right_track_22 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_41_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[6] , chanx_right_in[13] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_131 } ) , + .ccff_tail ( { ropt_net_151 } ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_right_track_26 ( +sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_26 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_1 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_28 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_2 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_129 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_30 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_3 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_32 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_34 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_36 ( + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2 mux_right_track_36 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_130 ) ) ; +sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_115 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_119 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_140 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( ropt_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_719 ( .A ( ropt_net_131 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_132 ) , - .X ( ropt_net_147 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_722 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( chany_bottom_in[2] ) , +sky130_fd_sc_hd__conb_1 optlc_117 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_129 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_130 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_124 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__8 ( .A ( chany_top_in[13] ) , .X ( ropt_net_146 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( - .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_727 ( .A ( ropt_net_139 ) , - .X ( ropt_net_148 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_126 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__10 ( .A ( chany_top_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__buf_2 prog_clk_0__bip393 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_765 ( .A ( ropt_net_136 ) , + .X ( chanx_right_out[12] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__15 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__17 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_345738 ( .A ( ctsbuf_net_1135 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_137 ) , + .X ( chanx_right_out[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chany_bottom_in[10] ) , + .X ( aps_rename_1_ ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chany_bottom_in[13] ) , .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[14] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( ropt_net_146 ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_140 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( .A ( chany_top_in[4] ) , - .X ( BUF_net_69 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( ropt_net_147 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_142 ) , - .X ( ropt_net_150 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( ropt_net_148 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_143 ) , - .X ( ropt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_75 ( .A ( chany_top_in[14] ) , - .X ( BUF_net_75 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_144 ) , - .X ( ropt_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_77 ( - .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( ropt_net_149 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_150 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_151 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chany_bottom_in[16] ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chany_top_in[18] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_152 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_162 ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_741 ( .A ( ropt_net_153 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_100 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_101 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_103 ( .A ( BUF_net_69 ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chany_top_in[6] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_69 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_70 ( .A ( chany_top_in[14] ) , .X ( ropt_net_142 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_106 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_143 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_107 ( .A ( chany_top_in[12] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_top_in[13] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_163 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_140 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_74 ( .A ( aps_rename_1_ ) , + .X ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( ropt_net_142 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_164 ) , .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_109 ( .A ( BUF_net_75 ) , - .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_772 ( + .A ( chany_bottom_in[17] ) , .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_773 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( + .A ( chany_bottom_in[18] ) , .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_146 ) , + .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_147 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_148 ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_149 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_98 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_165 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_102 ( .A ( BUF_net_74 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_150 ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_151 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_152 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_153 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_111 ( + .A ( right_bottom_grid_pin_41_[0] ) , .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_112 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( .A ( ropt_net_167 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_154 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_155 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_156 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_157 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_159 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_160 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_168 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( ropt_net_169 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_170 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_172 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_174 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_804 ( .A ( ropt_net_175 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_178 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v index 6d15198..88ad7ae 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.fm.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16,15 +16,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -57,8 +59,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -74,7 +76,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -91,8 +93,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -108,8 +110,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,8 +127,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -142,8 +144,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -159,8 +161,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -176,8 +178,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -193,8 +195,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -210,8 +212,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -227,8 +229,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -244,8 +246,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -261,8 +263,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -278,8 +280,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -295,8 +297,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -312,12 +314,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module const1 ( const1 ) ; +module sb_0__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -327,7 +329,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1 const1_0_ ( +sb_0__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -339,12 +341,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22 ( const1 ) ; +module sb_0__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -354,7 +356,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22 const1_0_ ( +sb_0__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -366,12 +368,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21 ( const1 ) ; +module sb_0__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -381,7 +383,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21 const1_0_ ( +sb_0__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -393,12 +395,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20 ( const1 ) ; +module sb_0__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -408,7 +410,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20 const1_0_ ( +sb_0__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -420,12 +422,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19 ( const1 ) ; +module sb_0__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_0__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -435,7 +460,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19 const1_0_ ( +sb_0__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -447,12 +472,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18 ( const1 ) ; +module sb_0__2__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -462,7 +487,34 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_18 const1_0_ ( +sb_0__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_0__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -474,12 +526,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17 ( const1 ) ; +module sb_0__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -489,7 +541,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17 const1_0_ ( +sb_0__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -501,12 +553,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16 ( const1 ) ; +module sb_0__2__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -516,7 +568,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16 const1_0_ ( +sb_0__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -528,12 +580,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15 ( const1 ) ; +module sb_0__2__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -543,7 +595,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15 const1_0_ ( +sb_0__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -555,12 +607,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14 ( const1 ) ; +module sb_0__2__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -570,7 +622,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14 const1_0_ ( +sb_0__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -582,12 +634,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_13 ( const1 ) ; +module sb_0__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -597,7 +649,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_13 const1_0_ ( +sb_0__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -609,12 +661,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12 ( const1 ) ; +module sb_0__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -624,7 +676,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12 const1_0_ ( +sb_0__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -636,12 +688,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11 ( const1 ) ; +module sb_0__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -651,7 +703,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_11 const1_0_ ( +sb_0__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -663,12 +715,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_10 ( const1 ) ; +module sb_0__2__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -678,7 +730,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_10 const1_0_ ( +sb_0__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -690,12 +742,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_9 ( const1 ) ; +module sb_0__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -705,7 +757,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_9 const1_0_ ( +sb_0__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -717,12 +769,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_8 ( const1 ) ; +module sb_0__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -732,36 +784,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_7 const1_0_ ( +sb_0__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -773,35 +796,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -817,7 +813,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -834,12 +830,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module const1_5 ( const1 ) ; +module sb_0__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -850,7 +846,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_5 const1_0_ ( +sb_0__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -865,12 +861,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_0__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -881,7 +877,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_4 const1_0_ ( +sb_0__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -896,7 +892,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -915,8 +911,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -934,12 +930,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module const1_3 ( const1 ) ; +module sb_0__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -952,7 +948,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3 const1_0_ ( +sb_0__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -973,12 +969,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_0__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -991,7 +987,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2 const1_0_ ( +sb_0__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1012,7 +1008,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1031,8 +1027,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1050,12 +1046,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module const1_1 ( const1 ) ; +module sb_0__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1069,7 +1065,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1 const1_0_ ( +sb_0__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1093,12 +1089,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module sb_0__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1112,7 +1108,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0 const1_0_ ( +sb_0__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1240,330 +1236,379 @@ wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_38 ( + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v index 6946ab3..7c720fc 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.lvs.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -23,15 +23,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -54,8 +56,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -78,8 +80,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -102,7 +104,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -126,8 +128,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -150,8 +152,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -174,8 +176,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -198,8 +200,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -222,8 +224,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -246,8 +248,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -270,8 +272,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -294,8 +296,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -318,8 +320,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -342,8 +344,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -366,8 +368,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -390,8 +392,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -414,8 +416,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -438,7 +440,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -464,7 +467,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -490,7 +494,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -516,7 +521,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -542,7 +548,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -552,300 +559,6 @@ input VSS ; input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; @@ -853,17 +566,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -889,7 +598,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -915,8 +652,278 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -939,7 +946,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -963,7 +970,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -994,7 +1002,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1025,7 +1034,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1052,8 +1061,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1079,7 +1088,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1119,7 +1129,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1159,7 +1170,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1186,8 +1197,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1213,7 +1224,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1257,7 +1269,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1409,497 +1422,582 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_38 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1204 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1205 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1206 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1207 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1208 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1209 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1210 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1263 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1211 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1212 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1213 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1214 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1215 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1216 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1217 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1218 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1219 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1220 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1221 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1222 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1223 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1224 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1225 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1226 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1227 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1228 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1229 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1230 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1231 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1232 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1233 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1234 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1235 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1236 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1237 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1238 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1239 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1907,85 +2005,141 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x805000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -1993,243 +2147,293 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x736000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2237,104 +2441,138 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y462400 ( @@ -2345,131 +2583,149 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x529000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x340400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2477,90 +2733,92 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y598400 ( @@ -2577,27 +2835,39 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2613,35 +2883,45 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2657,37 +2937,43 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x676200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2711,35 +2997,33 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2755,44 +3039,46 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( @@ -2815,38 +3101,44 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x892400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( @@ -2861,37 +3153,51 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2915,37 +3221,389 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v index d2ca854..5cae38b 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_0__2__icv_in_design.pt.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -16,15 +16,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_24__40 ( .A ( mem_out[1] ) , - .X ( net_net_59 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_74 ( .A ( net_net_59 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__40 ( .A ( mem_out[1] ) , + .X ( net_net_63 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_63 ( .A ( net_net_63 ) , + .X ( net_net_62 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_88 ( .A ( net_net_62 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -40,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -57,8 +59,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -74,7 +76,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__37 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -91,8 +93,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -108,8 +110,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -125,8 +127,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -142,8 +144,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -159,8 +161,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -176,8 +178,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -193,8 +195,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -210,8 +212,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -227,8 +229,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -244,8 +246,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -261,8 +263,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -278,8 +280,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -295,8 +297,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -312,7 +314,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -332,7 +334,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -352,7 +354,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -372,7 +374,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -392,7 +394,23 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -412,7 +430,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -432,7 +470,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -452,7 +490,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -472,7 +510,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -492,7 +530,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -512,7 +550,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -532,7 +570,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -552,7 +590,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -572,7 +610,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -592,7 +630,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -612,29 +650,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( BUF_net_43 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_75 ( .A ( BUF_net_43 ) , - .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -654,28 +670,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -691,7 +687,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -708,7 +704,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -732,7 +728,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -756,7 +752,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -775,8 +771,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__20 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -794,7 +790,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__19 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -826,7 +822,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -858,7 +854,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_0__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -877,8 +873,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__18 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_0__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -896,7 +892,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__17 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -932,7 +928,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1072,330 +1068,379 @@ wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_right_track_0 ( +sb_0__2__mux_tree_tapbuf_size6_0 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6 mux_right_track_4 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size6 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size6_mem_0 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size6_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_right_track_2 ( +sb_0__2__mux_tree_tapbuf_size5_0 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5 mux_right_track_6 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5 mux_right_track_6 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_6 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size5_mem mem_right_track_6 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_right_track_8 ( +sb_0__2__mux_tree_tapbuf_size3 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[14] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_0 mux_right_track_24 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_24 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size3_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_4 mux_right_track_10 ( +sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_10 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_5 mux_right_track_12 ( + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_12 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_6 mux_right_track_14 ( + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_7 mux_right_track_16 ( + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_8 mux_right_track_18 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_9 mux_right_track_20 ( + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; -mux_tree_tapbuf_size2_10 mux_right_track_22 ( + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; -mux_tree_tapbuf_size2_11 mux_right_track_26 ( + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_104 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { right_bottom_grid_pin_34_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_12 mux_right_track_28 ( + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_106 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_28 ( .in ( { right_bottom_grid_pin_35_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_13 mux_right_track_30 ( + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_14 mux_right_track_32 ( + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2_15 mux_right_track_34 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_16 mux_right_track_36 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_111 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; -mux_tree_tapbuf_size2 mux_right_track_38 ( + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_108 } ) , + .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_0 mux_bottom_track_1 ( .in ( { chanx_right_in[18] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_2 mux_bottom_track_5 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_3 mux_bottom_track_9 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_1 mux_bottom_track_25 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_95 ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_105 ) ) ; +sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_28 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_30 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_34 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_36 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_right_track_38 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem mem_right_track_38 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , - .ccff_tail ( { ropt_net_106 } ) , + .ccff_tail ( { ropt_net_121 } ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chanx_right_in[1] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_84 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_86 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_88 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_109 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( chanx_right_in[2] ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_680 ( .A ( ropt_net_98 ) , - .X ( ropt_net_115 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_108 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_681 ( .A ( chanx_right_in[8] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__0 ( .A ( chanx_right_in[0] ) , + .X ( aps_rename_10_ ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_724 ( .A ( ropt_net_127 ) , .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chanx_right_in[19] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , - .X ( chany_bottom_out[8] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_52 ( .A ( chanx_right_in[7] ) , - .X ( BUF_net_52 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_115 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_682 ( .A ( chanx_right_in[3] ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_683 ( .A ( ropt_net_101 ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_102 ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_right_in[17] ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_686 ( .A ( ropt_net_104 ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_688 ( .A ( ropt_net_106 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_103 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( ropt_net_128 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_104 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_726 ( .A ( ropt_net_129 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_66 ( .A ( chanx_right_in[15] ) , - .X ( ropt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_72 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_132 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__12 ( .A ( chanx_right_in[13] ) , + .X ( aps_rename_3_ ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( ropt_net_133 ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_78 ( .A ( BUF_net_52 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_134 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( ropt_net_135 ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_17__16 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_48 ( .A ( aps_rename_10_ ) , + .X ( BUF_net_48 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_136 ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_120 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_137 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_138 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_139 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_737 ( .A ( ropt_net_140 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_705 ( .A ( ropt_net_107 ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_58 ( .A ( aps_rename_3_ ) , + .X ( BUF_net_58 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_106 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_706 ( .A ( ropt_net_108 ) , + .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_707 ( .A ( chanx_right_in[10] ) , + .X ( chany_bottom_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_74 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_84 ( .A ( BUF_net_48 ) , + .X ( ropt_net_134 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( chanx_right_in[3] ) , + .X ( ropt_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_87 ( .A ( BUF_net_58 ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_708 ( .A ( ropt_net_110 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_93 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_709 ( .A ( ropt_net_111 ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_710 ( .A ( ropt_net_112 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_711 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_712 ( .A ( chanx_right_in[19] ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_713 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_715 ( .A ( chanx_right_in[17] ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_716 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_79 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_80 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_717 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_718 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_120 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_121 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_721 ( .A ( ropt_net_122 ) , + .X ( ropt_net_127 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_123 ) , + .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_124 ) , + .X ( ropt_net_131 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v index 3fed6b9..abeca44 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.fm.v @@ -4,7 +4,28 @@ // // // -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,38 +39,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1 ( const1 ) ; +module sb_1__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -62,7 +62,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1 const1_0_ ( +sb_1__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -83,12 +83,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26 ( const1 ) ; +module sb_1__0__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -101,7 +101,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_26 const1_0_ ( +sb_1__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -122,7 +122,26 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -136,36 +155,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_25 ( const1 ) ; +module sb_1__0__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -177,9 +177,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_25 const1_0_ ( +sb_1__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -193,18 +196,19 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module const1_24 ( const1 ) ; +module sb_1__0__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -216,9 +220,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_24 const1_0_ ( +sb_1__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -232,14 +239,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -254,13 +262,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -275,17 +283,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_23 ( const1 ) ; +module sb_1__0__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -304,7 +312,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_23 const1_0_ ( +sb_1__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; @@ -343,12 +351,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_22 ( const1 ) ; +module sb_1__0__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -367,10 +375,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22 const1_0_ ( +sb_1__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -403,10 +409,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -418,17 +426,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_21 ( const1 ) ; +module sb_1__0__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -438,7 +446,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21 const1_0_ ( +sb_1__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -450,7 +458,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -462,13 +470,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -479,13 +487,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -496,13 +504,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -513,13 +521,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -530,13 +538,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -547,13 +555,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -564,17 +572,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_20 ( const1 ) ; +module sb_1__0__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -585,7 +593,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_20 const1_0_ ( +sb_1__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -600,12 +608,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_19 ( const1 ) ; +module sb_1__0__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -616,7 +624,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_19 const1_0_ ( +sb_1__0__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -631,12 +639,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_18 ( const1 ) ; +module sb_1__0__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -647,7 +655,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_18 const1_0_ ( +sb_1__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -662,12 +670,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_17 ( const1 ) ; +module sb_1__0__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -678,7 +686,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_17 const1_0_ ( +sb_1__0__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -693,12 +701,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_16 ( const1 ) ; +module sb_1__0__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -709,7 +717,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_16 const1_0_ ( +sb_1__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -724,12 +732,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_15 ( const1 ) ; +module sb_1__0__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -740,7 +748,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_15 const1_0_ ( +sb_1__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -755,12 +763,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module sb_1__0__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -771,7 +779,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_14 const1_0_ ( +sb_1__0__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -786,7 +794,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -800,36 +827,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; +module sb_1__0__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -841,7 +849,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_13 const1_0_ ( +sb_1__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -859,12 +867,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module sb_1__0__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -876,7 +884,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_12 const1_0_ ( +sb_1__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -894,7 +902,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -908,13 +1030,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -927,13 +1049,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -946,131 +1068,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; +module sb_1__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1085,7 +1093,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11 const1_0_ ( +sb_1__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1112,12 +1120,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10 ( const1 ) ; +module sb_1__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1132,7 +1140,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10 const1_0_ ( +sb_1__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1159,12 +1167,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9 ( const1 ) ; +module sb_1__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1179,7 +1187,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9 const1_0_ ( +sb_1__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1206,12 +1214,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8 ( const1 ) ; +module sb_1__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1226,7 +1234,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_8 const1_0_ ( +sb_1__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1253,12 +1261,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_7 ( const1 ) ; +module sb_1__0__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1273,7 +1281,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_7 const1_0_ ( +sb_1__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1300,12 +1308,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module sb_1__0__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1320,7 +1328,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_6 const1_0_ ( +sb_1__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1347,12 +1355,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module sb_1__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1367,7 +1375,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_5 const1_0_ ( +sb_1__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1394,12 +1402,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_1__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1414,7 +1422,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_4 const1_0_ ( +sb_1__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1441,12 +1449,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module sb_1__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1461,7 +1469,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_3 const1_0_ ( +sb_1__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1488,7 +1496,49 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1504,59 +1554,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_2 ( const1 ) ; +module sb_1__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1572,7 +1580,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_2 const1_0_ ( +sb_1__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1602,12 +1610,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module sb_1__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1623,7 +1631,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_1 const1_0_ ( +sb_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1653,12 +1661,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module sb_1__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1674,7 +1682,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_0 const1_0_ ( +sb_1__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1715,7 +1723,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1749,6 +1761,16 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -1836,271 +1858,292 @@ wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_6 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_24 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -2108,199 +2151,256 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v index 2cfb214..362f3bd 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.lvs.v @@ -4,7 +4,36 @@ // // // -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26,41 +55,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -100,7 +101,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -140,7 +142,34 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -162,39 +191,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -208,9 +211,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -227,14 +234,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -248,9 +256,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -267,15 +279,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -299,13 +311,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -329,13 +341,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -402,7 +414,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -425,9 +438,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -466,10 +476,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -488,12 +501,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -519,7 +533,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -538,13 +552,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -562,13 +576,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -586,13 +600,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -610,13 +624,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -634,13 +648,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -658,13 +672,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -682,12 +696,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -718,7 +733,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -749,7 +765,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -780,7 +797,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -811,7 +829,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -842,7 +861,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -873,7 +893,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -904,7 +925,34 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -926,39 +974,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -993,7 +1015,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1028,7 +1051,169 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1050,13 +1235,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1077,13 +1262,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1104,174 +1289,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1320,7 +1344,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1369,7 +1394,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1418,7 +1444,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1467,7 +1494,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1516,7 +1544,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1565,7 +1594,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1614,7 +1644,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1663,7 +1694,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1712,7 +1744,67 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1737,72 +1829,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1855,7 +1888,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1908,7 +1942,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1972,7 +2007,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_BOT , VDD , VSS , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2008,6 +2047,16 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -2097,8 +2146,11 @@ supply0 VSS ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , @@ -2106,307 +2158,324 @@ mux_tree_tapbuf_size8 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_6 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_24 ( + .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -2415,71 +2484,141 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1241 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1242 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1243 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1244 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1245 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1246 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1247 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1248 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1249 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1250 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1251 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1252 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1253 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1254 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1255 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1256 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1257 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1258 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1259 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1260 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1261 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1262 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1263 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1264 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1265 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1266 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1267 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1268 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1269 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1270 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1271 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1272 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1273 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1274 ( .VNB ( VSS ) , @@ -2488,1232 +2627,1812 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1275 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1276 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1277 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , - .X ( ropt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y0 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y27200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x786600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x901600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1044200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1081000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x878600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1062600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1081000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x860200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1030400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1025800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1062600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x984400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x938400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x772800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1071800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1081000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x938400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x947600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x952200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1071800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x800400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1085600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x473800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3721,79 +4440,321 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x841800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x644000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v index f1ce1ea..aa0a8f0 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__0__icv_in_design.pt.v @@ -4,7 +4,28 @@ // // // -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__63 ( .A ( mem_out[2] ) , + .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_110 ( .A ( net_net_88 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,33 +39,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__60 ( .A ( mem_out[2] ) , - .X ( net_net_105 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_105 ( .A ( net_net_105 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__62 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -76,7 +76,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -108,7 +108,26 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__61 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -122,31 +141,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__60 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -158,7 +158,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -172,13 +175,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -190,7 +194,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -204,14 +211,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -226,13 +234,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size11_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -247,12 +255,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11_0 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -308,7 +316,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size11 ( in , sram , sram_inv , out , p0 ) ; input [0:10] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -327,8 +335,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -361,10 +367,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_69 ( + .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -376,12 +384,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -401,7 +409,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -413,13 +421,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -430,13 +438,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -447,13 +455,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -464,13 +472,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -481,13 +489,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -498,13 +506,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -515,12 +523,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -544,7 +552,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -568,7 +576,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -592,7 +600,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -616,7 +624,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -640,7 +648,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -664,7 +672,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -688,7 +696,26 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -702,31 +729,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__48 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -754,7 +762,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -782,7 +790,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__42 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -796,13 +918,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__41 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -815,13 +937,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__40 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__0__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -834,126 +956,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__39 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -993,7 +1001,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1033,7 +1041,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1073,7 +1081,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1113,7 +1121,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1153,7 +1161,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1193,7 +1201,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1233,7 +1241,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1273,7 +1281,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1313,7 +1321,49 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__0__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__38 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__0__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1329,54 +1379,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__36 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1420,7 +1428,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1464,7 +1472,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__0__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1519,7 +1527,11 @@ module sb_1__0_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_7_ , left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ , ccff_head , chany_top_out , chanx_right_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , SC_OUT_TOP , - SC_OUT_BOT ) ; + SC_OUT_BOT , prog_clk__FEEDTHRU_1 , prog_clk__FEEDTHRU_2 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , Test_en__FEEDTHRU_2 , + clk__FEEDTHRU_0 , clk__FEEDTHRU_1 , clk__FEEDTHRU_2 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1553,6 +1565,16 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +output [0:0] prog_clk__FEEDTHRU_1 ; +output [0:0] prog_clk__FEEDTHRU_2 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +output [0:0] Test_en__FEEDTHRU_2 ; +input [0:0] clk__FEEDTHRU_0 ; +output [0:0] clk__FEEDTHRU_1 ; +output [0:0] clk__FEEDTHRU_2 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size11_0_sram ; wire [0:3] mux_tree_tapbuf_size11_0_sram_inv ; @@ -1640,271 +1662,292 @@ wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ; // assign SC_IN_TOP = SC_IN_BOT ; +assign clk__FEEDTHRU_1[0] = clk__FEEDTHRU_0[0] ; +assign clk__FEEDTHRU_2[0] = clk__FEEDTHRU_0[0] ; +assign prog_clk__FEEDTHRU_1[0] = prog_clk__FEEDTHRU_2[0] ; -mux_tree_tapbuf_size8 mux_top_track_0 ( +sb_1__0__mux_tree_tapbuf_size8 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_left_in[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size8_1 mux_right_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_0 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[7] , chany_top_in[14] , chanx_right_in[2] , chanx_right_in[12] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size8_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_top_track_2 ( +sb_1__0__mux_tree_tapbuf_size7_6 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_7 mux_top_track_4 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_7 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[5] , chanx_right_in[7] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_6 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size7 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_3 mux_right_track_0 ( + .out ( chany_top_out[3] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_0 ( .in ( { chany_top_in[6] , chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size7_5 mux_right_track_8 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_5 mux_right_track_8 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_9_[0] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_4 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_16 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_3 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_1 mux_left_track_3 ( .in ( { chany_top_in[6] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[13] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_9 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_2 mux_left_track_9 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , chanx_right_in[6] , chanx_right_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_133 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_0 mux_left_track_17 ( .in ( { chany_top_in[3] , chany_top_in[10] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( mux_tree_tapbuf_size7_8_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_top_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_8_sram ) , .mem_outb ( mux_tree_tapbuf_size7_8_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_top_track_8 ( +sb_1__0__mux_tree_tapbuf_size4 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_0 mux_top_track_10 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_right_in[9] , chanx_right_in[19] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[5] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size4_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_12 ( +sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_right_in[10] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_1 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_right_in[12] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[7] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3_2 mux_top_track_16 ( +sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_right_in[13] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_3 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_right_in[14] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_4 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_4 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_right_in[16] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size3_5 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_5 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_right_in[17] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size3 mux_top_track_24 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_132 ) ) ; +sb_1__0__mux_tree_tapbuf_size3 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , chanx_right_in[18] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( mux_tree_tapbuf_size3_6_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_4 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem_5 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_6_sram ) , .mem_outb ( mux_tree_tapbuf_size3_6_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_top_track_38 ( +sb_1__0__mux_tree_tapbuf_size2 mux_top_track_38 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[19] ) , .p0 ( optlc_net_135 ) ) ; +sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_38 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size11 mux_right_track_4 ( +sb_1__0__mux_tree_tapbuf_size11 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_11_[0] , chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size11_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_129 ) ) ; -mux_tree_tapbuf_size11_0 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size11_0_sram_inv ) , + .out ( { ropt_net_142 } ) , + .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_0 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , chanx_right_in[5] , chanx_right_in[14] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_5_[0] , @@ -1912,199 +1955,256 @@ mux_tree_tapbuf_size11_0 mux_left_track_5 ( left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size11_1_sram ) , .sram_inv ( mux_tree_tapbuf_size11_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size11_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size11_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_0_sram ) , .mem_outb ( mux_tree_tapbuf_size11_0_sram_inv ) ) ; -mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size11_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size11_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size11_1_sram ) , .mem_outb ( mux_tree_tapbuf_size11_1_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_right_track_24 ( +sb_1__0__mux_tree_tapbuf_size6 mux_right_track_24 ( .in ( { chany_top_in[4] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_5_[0] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size6_0 mux_left_track_25 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_0 mux_left_track_25 ( .in ( { chany_top_in[2] , chany_top_in[9] , chany_top_in[16] , chanx_right_in[9] , chanx_right_in[18] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_130 ) ) ; -mux_tree_tapbuf_size6_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_136 ) ) ; +sb_1__0__mux_tree_tapbuf_size6_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__0__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { chany_top_in[5] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_7_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_131 ) ) ; -mux_tree_tapbuf_size5_0 mux_left_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_134 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_0 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[8] , chany_top_in[15] , chanx_right_in[10] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_131 ) ) ; +sb_1__0__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , - .ccff_tail ( { ropt_net_139 } ) , + .ccff_tail ( { ropt_net_155 } ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_154 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_159 ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_160 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_761 ( .A ( ropt_net_161 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_129 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_130 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( ropt_net_162 ) , - .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_163 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_131 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[18] ) , - .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_723 ( .A ( ropt_net_133 ) , - .X ( ropt_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_134 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_164 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_725 ( .A ( ropt_net_135 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( ropt_net_165 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_166 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( ropt_net_138 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__24 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_158 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( ropt_net_139 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_156 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_167 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_155 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_730 ( .A ( chanx_left_in[11] ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_153 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_141 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_168 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_169 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_170 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[15] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_171 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_733 ( .A ( chanx_left_in[7] ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_70 ( .A ( chanx_left_in[3] ) , - .X ( BUF_net_70 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_141 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_72 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_734 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_735 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_736 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_175 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_80 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_157 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( - .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( chanx_right_in[9] ) , - .X ( ropt_net_159 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( chanx_left_in[19] ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( top_left_grid_pin_43_[0] ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_743 ( .A ( chanx_right_in[13] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_744 ( .A ( ropt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chanx_right_in[4] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_121 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_131 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_123 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_132 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__5 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_125 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_133 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_127 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_134 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_129 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_131 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_136 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip398 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_3139 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_140 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_142 ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__buf_8 cts_buf_368766 ( .A ( ctsbuf_net_3139 ) , + .X ( prog_clk__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chanx_left_in[8] ) , .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_176 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_745 ( .A ( ropt_net_154 ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_746 ( .A ( ropt_net_155 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_left_in[9] ) , .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_95 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_106 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_107 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_135 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_157 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_114 ( .A ( BUF_net_70 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_793 ( .A ( chanx_right_in[18] ) , + .X ( chanx_left_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_145 ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_795 ( + .A ( Test_en__FEEDTHRU_0[0] ) , .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__25 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_796 ( .A ( ropt_net_147 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_left_in[19] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_151 ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_828 ( .A ( ropt_net_174 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_152 ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_829 ( .A ( ropt_net_175 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_176 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_832 ( .A ( ropt_net_178 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_833 ( .A ( ropt_net_179 ) , + .X ( chanx_right_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_834 ( .A ( ropt_net_180 ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_115 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_138 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_835 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_left_in[7] ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chanx_left_in[11] ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_81 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[15] ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_837 ( .A ( ropt_net_183 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_153 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_154 ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_155 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_156 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_157 ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_158 ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_159 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_838 ( .A ( ropt_net_184 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_105 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chanx_left_in[14] ) , .X ( ropt_net_164 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_109 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_160 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_113 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_161 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_162 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_163 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_164 ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_165 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_166 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_167 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_168 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_170 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_171 ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_172 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_839 ( .A ( ropt_net_185 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_840 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_841 ( .A ( ropt_net_187 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_842 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_843 ( .A ( ropt_net_189 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_845 ( .A ( ropt_net_191 ) , + .X ( Test_en__FEEDTHRU_2[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_192 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_193 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_194 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_195 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_196 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_852 ( .A ( ropt_net_197 ) , + .X ( chanx_left_out[13] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v index e14db9d..90de602 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.fm.v @@ -4,7 +4,68 @@ // // // -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,76 +79,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1 ( const1 ) ; +module sb_1__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -102,7 +104,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1 const1_0_ ( +sb_1__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -129,12 +131,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26 ( const1 ) ; +module sb_1__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -149,7 +151,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_26 const1_0_ ( +sb_1__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -176,12 +178,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_25 ( const1 ) ; +module sb_1__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -196,7 +198,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_25 const1_0_ ( +sb_1__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -223,12 +225,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_24 ( const1 ) ; +module sb_1__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -241,12 +243,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_24 const1_0_ ( +sb_1__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -263,15 +262,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -286,13 +284,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -307,13 +305,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -328,13 +326,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -349,13 +347,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -370,13 +368,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -391,13 +389,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -412,13 +410,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -433,13 +431,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -454,13 +452,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -475,13 +473,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -496,13 +494,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -517,17 +515,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_23 ( const1 ) ; +module sb_1__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -545,7 +543,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_23 const1_0_ ( +sb_1__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -581,12 +579,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_22 ( const1 ) ; +module sb_1__1__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -604,7 +602,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_22 const1_0_ ( +sb_1__1__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -640,12 +638,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_21 ( const1 ) ; +module sb_1__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -663,7 +661,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_21 const1_0_ ( +sb_1__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -699,12 +697,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_20 ( const1 ) ; +module sb_1__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -722,7 +720,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_20 const1_0_ ( +sb_1__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -758,12 +756,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_19 ( const1 ) ; +module sb_1__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -781,7 +779,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_19 const1_0_ ( +sb_1__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -817,12 +815,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_18 ( const1 ) ; +module sb_1__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -840,7 +838,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_18 const1_0_ ( +sb_1__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -876,12 +874,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_17 ( const1 ) ; +module sb_1__1__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -899,7 +897,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_17 const1_0_ ( +sb_1__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -935,12 +933,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_16 ( const1 ) ; +module sb_1__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -958,7 +956,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_16 const1_0_ ( +sb_1__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -994,12 +992,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_15 ( const1 ) ; +module sb_1__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1017,7 +1015,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_15 const1_0_ ( +sb_1__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1053,12 +1051,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module sb_1__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1076,7 +1074,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_14 const1_0_ ( +sb_1__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1112,12 +1110,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module sb_1__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1135,7 +1133,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_13 const1_0_ ( +sb_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1171,12 +1169,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module sb_1__1__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1194,7 +1192,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_12 const1_0_ ( +sb_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1230,8 +1228,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1248,13 +1246,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1271,13 +1269,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1294,13 +1292,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1317,17 +1315,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_11 ( const1 ) ; +module sb_1__1__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1351,7 +1349,173 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_11 const1_0_ ( +sb_1__1__const1_11 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_10 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; @@ -1405,91 +1569,12 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module const1_10 ( const1 ) ; +module sb_1__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1513,10 +1598,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_9 const1_0_ ( +sb_1__1__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1564,94 +1647,13 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1666,13 +1668,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1687,13 +1689,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1708,13 +1710,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1729,13 +1731,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1750,13 +1752,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1771,13 +1773,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1792,13 +1794,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1813,17 +1815,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_7 ( const1 ) ; +module sb_1__1__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1843,7 +1845,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_7 const1_0_ ( +sb_1__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -1885,12 +1887,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module sb_1__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1910,7 +1912,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( +sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -1952,12 +1954,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module sb_1__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1977,7 +1979,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +sb_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2019,12 +2021,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_1__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2044,7 +2046,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +sb_1__1__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2086,12 +2088,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module sb_1__1__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2111,7 +2113,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_3 const1_0_ ( +sb_1__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2153,12 +2155,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_1__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2178,7 +2180,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_2 const1_0_ ( +sb_1__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2220,12 +2222,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module sb_1__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2245,7 +2247,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( +sb_1__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2287,12 +2289,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module sb_1__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2312,7 +2314,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( +sb_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; @@ -2370,7 +2372,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail ) ; + chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2414,6 +2419,11 @@ output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2500,7 +2510,7 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -2508,8 +2518,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -2517,8 +2527,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -2526,8 +2536,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -2535,8 +2545,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -2544,8 +2554,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -2553,8 +2563,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -2562,8 +2572,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -2571,48 +2581,54 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -2621,9 +2637,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -2633,8 +2650,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -2643,9 +2660,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -2654,354 +2672,509 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; + .X ( ropt_net_168 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v index bba0c8d..5f16111 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.lvs.v @@ -4,7 +4,92 @@ // // // -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26,95 +111,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -163,7 +166,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -212,7 +216,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -261,7 +266,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -276,13 +282,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -303,15 +305,15 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -335,13 +337,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -365,13 +367,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -395,13 +397,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -425,13 +427,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -455,13 +457,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -485,13 +487,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -515,13 +517,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -545,13 +547,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -575,13 +577,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -605,13 +607,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -635,13 +637,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -665,13 +667,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -733,8 +735,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -796,8 +798,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -859,8 +861,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -922,8 +924,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -985,8 +987,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1048,8 +1050,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1111,8 +1113,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1174,8 +1176,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1237,8 +1239,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1300,8 +1302,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1363,7 +1365,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1425,8 +1428,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1453,13 +1456,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1486,13 +1489,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1519,13 +1522,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1552,13 +1555,193 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1647,94 +1830,8 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1762,9 +1859,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1820,100 +1914,14 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1937,13 +1945,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1967,13 +1975,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1997,13 +2005,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2027,13 +2035,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2057,13 +2065,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2087,13 +2095,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2117,13 +2125,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2147,13 +2155,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2224,8 +2232,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2296,8 +2304,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2368,8 +2376,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2440,8 +2448,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2512,8 +2520,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2584,7 +2592,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2655,8 +2664,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2743,7 +2752,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS ) ; + chany_bottom_out , chanx_left_out , ccff_tail , VDD , VSS , + prog_clk__FEEDTHRU_1 , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2789,6 +2801,11 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2877,7 +2894,7 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -2886,8 +2903,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -2896,8 +2913,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -2906,8 +2923,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -2916,8 +2933,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -2926,8 +2943,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -2936,8 +2953,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -2946,8 +2963,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -2956,56 +2973,62 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -3014,10 +3037,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -3028,8 +3051,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -3038,10 +3061,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -3050,34 +3073,37 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , @@ -3085,8 +3111,8 @@ mux_tree_tapbuf_size10 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , @@ -3094,8 +3120,8 @@ mux_tree_tapbuf_size10_9 mux_top_track_16 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , @@ -3103,8 +3129,8 @@ mux_tree_tapbuf_size10_10 mux_top_track_24 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , @@ -3112,8 +3138,8 @@ mux_tree_tapbuf_size10_8 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , @@ -3121,8 +3147,8 @@ mux_tree_tapbuf_size10_6 mux_right_track_16 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , @@ -3130,8 +3156,8 @@ mux_tree_tapbuf_size10_7 mux_right_track_24 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , @@ -3139,8 +3165,8 @@ mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , @@ -3148,8 +3174,8 @@ mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , @@ -3157,8 +3183,8 @@ mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , @@ -3166,8 +3192,8 @@ mux_tree_tapbuf_size10_5 mux_left_track_9 ( .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , @@ -3175,8 +3201,8 @@ mux_tree_tapbuf_size10_3 mux_left_track_17 ( .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -3184,135 +3210,199 @@ mux_tree_tapbuf_size10_4 mux_left_track_25 ( .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1278 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1279 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1280 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1281 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1282 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1283 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1284 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1285 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1286 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1287 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1288 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1289 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1290 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1291 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1292 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1293 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1294 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1295 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1296 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1297 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1298 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1299 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1300 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1301 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1302 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1303 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1304 ( .VNB ( VSS ) , @@ -3339,543 +3429,986 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1314 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1315 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1316 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x124200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x271400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1090200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x179400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x78200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x984400y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1067200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1127000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y272000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1002800y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1090200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1154600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y244800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x860200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x82800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1131600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y299200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x805000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x133400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x777400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x846400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x897000y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1122400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3883,371 +4416,999 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x906200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x933800y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1021200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1039600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1136200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x892400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x993600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x759000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x851000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x869400y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y571200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x874000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x883200y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1062600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x901600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1021200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1067200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1076400y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y680000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x828000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x989000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1025800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1044200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x69000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x910800y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x970600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x979800y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1113200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x892400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x910800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x920000y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x956800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1145400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1104000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1122400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1154600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1016600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1035000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1191400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y843200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y870400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1150000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1168400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y870400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x887800y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1108600y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y870400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x920000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x993600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1012000y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1140800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x855600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y1033600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v index bee694a..609f326 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__1__icv_in_design.pt.v @@ -4,7 +4,68 @@ // // // -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__81 ( .A ( mem_out[2] ) , + .X ( net_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_99 ( .A ( net_net_99 ) , + .X ( net_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_123 ( .A ( net_net_98 ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__80 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__79 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,71 +79,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_28__79 ( .A ( mem_out[2] ) , - .X ( net_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_87 ( .A ( net_net_87 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__78 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_27__78 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_26__77 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_25__76 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -122,7 +124,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -162,7 +164,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -202,7 +204,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -215,10 +217,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -235,15 +234,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -258,13 +256,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__75 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__77 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -279,13 +277,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__74 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__76 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -300,13 +298,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__73 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__75 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -321,13 +319,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__72 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__74 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -342,13 +340,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_20__71 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__73 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -363,13 +361,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_19__70 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__72 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -384,13 +382,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__69 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__71 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -405,13 +403,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__68 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__70 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -426,13 +424,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__67 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__69 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -447,13 +445,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_15__66 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__68 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -468,13 +466,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_14__65 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__67 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -489,12 +487,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__64 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__66 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_4 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -546,7 +544,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_3 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -598,7 +596,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_5 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -650,7 +648,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -702,7 +700,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -754,7 +752,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_2 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -806,7 +804,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_7 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -858,7 +856,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_6 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -910,7 +908,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_8 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -962,7 +960,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1014,7 +1012,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10_9 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1066,7 +1064,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1118,8 +1116,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1136,13 +1134,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_12__63 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__65 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1159,13 +1157,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_11__62 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__64 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1182,13 +1180,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__61 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__63 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size16_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1205,12 +1203,164 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_4_ ( .D ( mem_out[3] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[4] ) , .Q_N ( mem_outb[4] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__60 ( .A ( mem_out[4] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__62 ( .A ( mem_out[4] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_126 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:15] in ; +input [0:4] sram ; +input [0:4] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , + .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_1__1__mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1286,79 +1436,7 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( endmodule -module mux_tree_tapbuf_size16_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_4 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size16_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; input [0:15] in ; input [0:4] sram ; input [0:4] sram_inv ; @@ -1382,8 +1460,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -1431,87 +1507,13 @@ sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size16 ( in , sram , sram_inv , out , p0 ) ; -input [0:15] in ; -input [0:4] sram ; -input [0:4] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_12_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_13_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_14_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_15_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_15_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_4_ ( .A0 ( in[10] ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_5_ ( .A0 ( in[12] ) , .A1 ( in[11] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_6_ ( .A0 ( in[14] ) , .A1 ( in[13] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_7_ ( .A0 ( p0 ) , .A1 ( in[15] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_2_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_3_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_12_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_13_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_12_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_14_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l5_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_14_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .S ( sram[4] ) , - .X ( sky130_fd_sc_hd__mux2_1_15_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1526,13 +1528,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_8__59 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__61 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1547,13 +1549,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__58 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__60 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1568,13 +1570,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_6__57 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__59 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1589,13 +1591,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__56 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__58 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1610,13 +1612,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__55 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__57 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1631,13 +1633,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__54 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__56 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1652,13 +1654,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__53 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__55 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__1__mux_tree_tapbuf_size12_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1673,12 +1675,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__52 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__54 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_3 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1738,7 +1740,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_2 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1798,7 +1800,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_1 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1858,7 +1860,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_0 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1918,7 +1920,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_5 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1978,7 +1980,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_4 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2038,7 +2040,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2098,7 +2100,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__1__mux_tree_tapbuf_size12_6 ( in , sram , sram_inv , out , p0 ) ; input [0:11] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2174,7 +2176,10 @@ module sb_1__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chanx_right_out , - chany_bottom_out , chanx_left_out , ccff_tail ) ; + chany_bottom_out , chanx_left_out , ccff_tail , prog_clk__FEEDTHRU_1 , + Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2218,6 +2223,11 @@ output [0:19] chanx_right_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +output [0:0] prog_clk__FEEDTHRU_1 ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2304,7 +2314,7 @@ wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ; wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ; // -mux_tree_tapbuf_size12_6 mux_top_track_0 ( +sb_1__1__mux_tree_tapbuf_size12_6 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , chanx_right_in[1] , chanx_right_in[2] , chanx_right_in[12] , @@ -2312,8 +2322,8 @@ mux_tree_tapbuf_size12_6 mux_top_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( mux_tree_tapbuf_size12_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12 mux_top_track_2 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_right_in[3] , chanx_right_in[4] , chanx_right_in[13] , @@ -2321,8 +2331,8 @@ mux_tree_tapbuf_size12 mux_top_track_2 ( chanx_left_in[13] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( mux_tree_tapbuf_size12_1_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size12_4 mux_right_track_0 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_4 mux_right_track_0 ( .in ( { chany_top_in[2] , chany_top_in[12] , chany_top_in[19] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , @@ -2330,8 +2340,8 @@ mux_tree_tapbuf_size12_4 mux_right_track_0 ( chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( mux_tree_tapbuf_size12_2_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size12_5 mux_right_track_2 ( + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_5 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_top_in[4] , chany_top_in[13] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , @@ -2339,8 +2349,8 @@ mux_tree_tapbuf_size12_5 mux_right_track_2 ( chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( mux_tree_tapbuf_size12_3_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chanx_right_in[15] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , @@ -2348,8 +2358,8 @@ mux_tree_tapbuf_size12_0 mux_bottom_track_1 ( chanx_left_in[1] , chanx_left_in[2] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( mux_tree_tapbuf_size12_4_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chanx_right_in[4] , chanx_right_in[11] , chanx_right_in[13] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , @@ -2357,8 +2367,8 @@ mux_tree_tapbuf_size12_1 mux_bottom_track_3 ( chanx_left_in[3] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( mux_tree_tapbuf_size12_5_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_2 mux_left_track_1 ( + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_2 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_top_in[12] , chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[2] , chany_bottom_in[12] , chany_bottom_in[19] , @@ -2366,8 +2376,8 @@ mux_tree_tapbuf_size12_2 mux_left_track_1 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( mux_tree_tapbuf_size12_6_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_3 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_3 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , chany_top_in[19] , chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[4] , chany_bottom_in[13] , @@ -2375,48 +2385,54 @@ mux_tree_tapbuf_size12_3 mux_left_track_3 ( left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( mux_tree_tapbuf_size12_7_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_0_sram ) , .mem_outb ( mux_tree_tapbuf_size12_0_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem mem_top_track_2 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_1_sram ) , .mem_outb ( mux_tree_tapbuf_size12_1_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_2_sram ) , .mem_outb ( mux_tree_tapbuf_size12_2_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_3_sram ) , .mem_outb ( mux_tree_tapbuf_size12_3_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_4_sram ) , .mem_outb ( mux_tree_tapbuf_size12_4_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_5_sram ) , .mem_outb ( mux_tree_tapbuf_size12_5_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_6_sram ) , .mem_outb ( mux_tree_tapbuf_size12_6_sram_inv ) ) ; -mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size12_mem_3 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size12_7_sram ) , .mem_outb ( mux_tree_tapbuf_size12_7_sram_inv ) ) ; -mux_tree_tapbuf_size16 mux_top_track_4 ( +sb_1__1__mux_tree_tapbuf_size16 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -2425,9 +2441,10 @@ mux_tree_tapbuf_size16 mux_top_track_4 ( chany_bottom_in[5] , chany_bottom_in[14] , chanx_left_in[5] , chanx_left_in[14] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size16_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size16_2 mux_right_track_4 ( + .sram_inv ( mux_tree_tapbuf_size16_0_sram_inv ) , + .out ( { ropt_net_151 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_2 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[5] , chany_top_in[14] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , @@ -2437,8 +2454,8 @@ mux_tree_tapbuf_size16_2 mux_right_track_4 ( chanx_left_in[5] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_1_sram ) , .sram_inv ( mux_tree_tapbuf_size16_1_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chanx_right_in[5] , chanx_right_in[7] , chanx_right_in[14] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , @@ -2447,9 +2464,10 @@ mux_tree_tapbuf_size16_0 mux_bottom_track_5 ( bottom_left_grid_pin_49_[0] , chanx_left_in[5] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size16_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_1 mux_left_track_5 ( + .sram_inv ( mux_tree_tapbuf_size16_2_sram_inv ) , + .out ( { ropt_net_148 } ) , + .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_1 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , chany_top_in[15] , chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[5] , chany_bottom_in[14] , @@ -2458,354 +2476,509 @@ mux_tree_tapbuf_size16_1 mux_left_track_5 ( left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size16_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size16_3_sram_inv ) , + .out ( { ropt_net_152 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size16_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_0_sram ) , .mem_outb ( mux_tree_tapbuf_size16_0_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_2 mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_1_sram ) , .mem_outb ( mux_tree_tapbuf_size16_1_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_2_sram ) , .mem_outb ( mux_tree_tapbuf_size16_2_sram_inv ) ) ; -mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size16_mem_1 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size16_3_sram ) , .mem_outb ( mux_tree_tapbuf_size16_3_sram_inv ) ) ; -mux_tree_tapbuf_size10 mux_top_track_8 ( +sb_1__1__mux_tree_tapbuf_size10 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , chanx_right_in[6] , chanx_right_in[11] , chanx_right_in[16] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_9 mux_top_track_16 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_9 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chanx_right_in[8] , chanx_right_in[15] , chanx_right_in[17] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[7] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_10 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_10 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chanx_right_in[9] , chanx_right_in[18] , chanx_right_in[19] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[3] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( mux_tree_tapbuf_size10_2_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_8 mux_right_track_8 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_8 mux_right_track_8 ( .in ( { chany_top_in[3] , chany_top_in[6] , chany_top_in[16] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( mux_tree_tapbuf_size10_3_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_6 mux_right_track_16 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_6 mux_right_track_16 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( mux_tree_tapbuf_size10_4_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_7 mux_right_track_24 ( .in ( { chany_top_in[9] , chany_top_in[11] , chany_top_in[18] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( mux_tree_tapbuf_size10_5_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_2 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , chanx_right_in[3] , chanx_right_in[6] , chanx_right_in[16] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[6] , chanx_left_in[11] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( mux_tree_tapbuf_size10_6_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , chanx_right_in[1] , chanx_right_in[8] , chanx_right_in[17] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[8] , chanx_left_in[15] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( mux_tree_tapbuf_size10_7_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_126 ) ) ; -mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_1 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , chanx_right_in[0] , chanx_right_in[9] , chanx_right_in[18] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[9] , chanx_left_in[18] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size10_8_sram ) , .sram_inv ( mux_tree_tapbuf_size10_8_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size10_5 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_5 mux_left_track_9 ( .in ( { chany_top_in[6] , chany_top_in[11] , chany_top_in[16] , chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[3] , chany_bottom_in[6] , chany_bottom_in[16] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( mux_tree_tapbuf_size10_9_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_3 mux_left_track_17 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_146 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_3 mux_left_track_17 ( .in ( { chany_top_in[7] , chany_top_in[8] , chany_top_in[17] , chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[7] , chany_bottom_in[8] , chany_bottom_in[17] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size10_10_sram ) , .sram_inv ( mux_tree_tapbuf_size10_10_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_4 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_4 mux_left_track_25 ( .in ( { chany_top_in[3] , chany_top_in[9] , chany_top_in[18] , chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[9] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size10_11_sram ) , .sram_inv ( mux_tree_tapbuf_size10_11_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size10_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_9 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_10 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_2_sram ) , .mem_outb ( mux_tree_tapbuf_size10_2_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_8 mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_3_sram ) , .mem_outb ( mux_tree_tapbuf_size10_3_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_4_sram ) , .mem_outb ( mux_tree_tapbuf_size10_4_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_7 mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_5_sram ) , .mem_outb ( mux_tree_tapbuf_size10_5_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_2 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_6_sram ) , .mem_outb ( mux_tree_tapbuf_size10_6_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .mem_outb ( mux_tree_tapbuf_size10_7_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_8_sram ) , .mem_outb ( mux_tree_tapbuf_size10_8_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_5 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size16_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_9_sram ) , .mem_outb ( mux_tree_tapbuf_size10_9_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_10_sram ) , .mem_outb ( mux_tree_tapbuf_size10_10_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size10_mem_4 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_11_sram ) , .mem_outb ( mux_tree_tapbuf_size10_11_sram_inv ) ) ; -mux_tree_tapbuf_size7 mux_top_track_32 ( +sb_1__1__mux_tree_tapbuf_size7 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chanx_right_in[0] , chanx_right_in[10] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_2 mux_right_track_32 ( + .out ( chany_top_out[16] ) , .p0 ( optlc_net_145 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_2 mux_right_track_32 ( .in ( { chany_top_in[10] , chany_top_in[15] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[10] , chany_bottom_in[19] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_128 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_0 mux_bottom_track_33 ( .in ( { chany_top_in[10] , chanx_right_in[10] , chanx_right_in[19] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_125 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_33 ( + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_1 mux_left_track_33 ( .in ( { chany_top_in[1] , chany_top_in[10] , chanx_right_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_127 ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__1__mux_tree_tapbuf_size7_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_2 mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_1__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_11_ccff_tail ) , - .ccff_tail ( { ropt_net_130 } ) , + .ccff_tail ( { ropt_net_172 } ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_1__0 ( .A ( chany_top_in[2] ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_2__1 ( .A ( chany_top_in[4] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_116 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_125 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_4__3 ( .A ( chany_top_in[6] ) , + .X ( ropt_net_183 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chany_top_in[8] ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_8__7 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( chany_bottom_out[15] ) ) ; + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_9__8 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_197 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_118 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_126 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_13__12 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_163 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_13__12 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chanx_right_in[2] ) , - .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_15__14 ( .A ( chanx_right_in[4] ) , .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_120 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_127 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_122 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_128 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_18__17 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_850 ( .A ( ropt_net_200 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_146 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_20__19 ( .A ( chanx_right_in[10] ) , .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_right_in[12] ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_23__22 ( .A ( chanx_right_in[14] ) , - .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_851 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_852 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 FTB_24__23 ( .A ( chanx_right_in[16] ) , - .X ( aps_rename_1_ ) ) ; + .X ( ropt_net_168 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_25__24 ( .A ( chanx_right_in[17] ) , .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_729 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_133 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_731 ( .A ( ropt_net_130 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_732 ( .A ( chanx_left_in[5] ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_132 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_32__31 ( .A ( chany_bottom_in[9] ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_134 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_37__36 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_39__38 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_40__39 ( .A ( chanx_left_in[2] ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_41__40 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_43__42 ( .A ( chanx_left_in[6] ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_44__43 ( .A ( chanx_left_in[8] ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_49__48 ( .A ( chanx_left_in[14] ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , - .X ( ropt_net_132 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_85 ( .A ( chany_bottom_in[10] ) , - .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chanx_left_in[10] ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_90 ( .A ( chanx_left_in[9] ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_91 ( .A ( chanx_left_in[17] ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_101 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_102 ( .A ( chany_top_in[17] ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_103 ( .A ( chanx_right_in[6] ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_104 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_right_in[18] ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_105 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_106 ( .A ( chany_bottom_in[6] ) , - .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_107 ( .A ( chany_bottom_in[8] ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_108 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_bottom_in[14] ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[16] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_28__27 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_165 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0__bip409 ( .A ( prog_clk[0] ) , + .X ( ctsbuf_net_1147 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_30__29 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_31__30 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_178 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_148 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_33__32 ( .A ( chany_bottom_in[10] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_34__33 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_35__34 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_36__35 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_854 ( .A ( ropt_net_203 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_38__37 ( .A ( chany_bottom_in[17] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_359768 ( .A ( ctsbuf_net_1147 ) , + .X ( prog_clk__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_228 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_797 ( .A ( chanx_left_in[14] ) , + .X ( chanx_right_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_151 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_152 ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_224 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_45__44 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_46__45 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_47__46 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_48__47 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( chany_top_in[9] ) , + .X ( chany_bottom_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( chanx_right_in[6] ) , + .X ( ropt_net_225 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_223 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_52__51 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_53__52 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_157 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_855 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_856 ( .A ( ropt_net_205 ) , + .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( + .A ( chany_bottom_in[16] ) , .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_94 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_857 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_96 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_97 ( .A ( chanx_left_in[16] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_227 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_226 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( chanx_left_in[5] ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_112 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_858 ( .A ( ropt_net_207 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_114 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_859 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_116 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_118 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_860 ( .A ( ropt_net_209 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_863 ( .A ( ropt_net_210 ) , .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_112 ( .A ( aps_rename_1_ ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_113 ( .A ( chanx_right_in[5] ) , +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_121 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_810 ( .A ( ropt_net_163 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_864 ( .A ( ropt_net_211 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_97 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_165 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_166 ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_167 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_168 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_169 ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_170 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_171 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_172 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_173 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_822 ( .A ( ropt_net_175 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_176 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_177 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_825 ( .A ( ropt_net_178 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_826 ( .A ( ropt_net_179 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_827 ( .A ( ropt_net_180 ) , + .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_181 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_183 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_184 ) , + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_833 ( .A ( ropt_net_185 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_834 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_835 ( .A ( ropt_net_187 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_836 ( .A ( ropt_net_188 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_839 ( .A ( ropt_net_189 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_840 ( .A ( ropt_net_190 ) , + .X ( chany_top_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_841 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_843 ( .A ( ropt_net_192 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_844 ( .A ( ropt_net_193 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_846 ( .A ( ropt_net_194 ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_847 ( .A ( ropt_net_195 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_848 ( .A ( ropt_net_196 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_849 ( .A ( ropt_net_197 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_866 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_867 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_870 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_871 ( .A ( ropt_net_215 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_872 ( .A ( ropt_net_216 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_874 ( .A ( ropt_net_217 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_875 ( .A ( ropt_net_218 ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_877 ( .A ( ropt_net_219 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_878 ( .A ( ropt_net_220 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_880 ( .A ( ropt_net_221 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_886 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_891 ( .A ( ropt_net_223 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_892 ( .A ( ropt_net_224 ) , .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_893 ( .A ( ropt_net_225 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_894 ( .A ( ropt_net_226 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_895 ( .A ( ropt_net_227 ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_896 ( .A ( ropt_net_228 ) , + .X ( chany_top_out[6] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v index ea3ca3a..6a42f1f 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,19 +18,19 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module sb_1__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -44,7 +44,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1 const1_0_ ( +sb_1__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -68,7 +68,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -80,17 +80,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_26 ( const1 ) ; +module sb_1__2__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -100,19 +100,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_26 const1_0_ ( +sb_1__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -124,13 +124,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -141,13 +141,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -158,13 +158,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -175,13 +175,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -192,13 +192,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -209,17 +209,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_25 ( const1 ) ; +module sb_1__2__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -230,7 +230,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_25 const1_0_ ( +sb_1__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -240,17 +240,17 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_24 ( const1 ) ; +module sb_1__2__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -261,7 +261,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24 const1_0_ ( +sb_1__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -276,12 +276,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23 ( const1 ) ; +module sb_1__2__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -292,7 +292,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23 const1_0_ ( +sb_1__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -307,12 +307,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22 ( const1 ) ; +module sb_1__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -323,7 +323,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22 const1_0_ ( +sb_1__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -338,12 +338,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_21 ( const1 ) ; +module sb_1__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -354,7 +354,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_21 const1_0_ ( +sb_1__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -369,12 +369,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_20 ( const1 ) ; +module sb_1__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -385,7 +385,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_20 const1_0_ ( +sb_1__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -400,7 +400,45 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -414,55 +452,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_19 ( const1 ) ; +module sb_1__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -474,7 +474,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_19 const1_0_ ( +sb_1__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -492,12 +492,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18 ( const1 ) ; +module sb_1__2__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -509,7 +509,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18 const1_0_ ( +sb_1__2__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -527,12 +527,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_17 ( const1 ) ; +module sb_1__2__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -544,7 +544,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_17 const1_0_ ( +sb_1__2__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -562,7 +562,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -576,17 +576,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_16 ( const1 ) ; +module sb_1__2__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -599,7 +599,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_16 const1_0_ ( +sb_1__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -620,7 +620,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -634,13 +748,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -653,131 +767,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_15 ( const1 ) ; +module sb_1__2__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -792,54 +792,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_14 const1_0_ ( +sb_1__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -866,12 +819,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_13 ( const1 ) ; +module sb_1__2__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -886,7 +839,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_13 const1_0_ ( +sb_1__2__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -913,12 +866,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module sb_1__2__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -933,7 +886,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_12 const1_0_ ( +sb_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -960,12 +913,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_11 ( const1 ) ; +module sb_1__2__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -978,9 +931,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11 const1_0_ ( +sb_1__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1000,19 +952,16 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module const1_10 ( const1 ) ; +module sb_1__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1027,7 +976,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10 const1_0_ ( +sb_1__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1054,12 +1003,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9 ( const1 ) ; +module sb_1__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1074,7 +1023,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_9 const1_0_ ( +sb_1__2__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1101,12 +1050,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_8 ( const1 ) ; +module sb_1__2__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1121,7 +1070,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_8 const1_0_ ( +sb_1__2__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1148,7 +1097,75 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_1__2__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1164,38 +1181,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; +module sb_1__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1211,7 +1207,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_7 const1_0_ ( +sb_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1241,12 +1237,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module sb_1__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1262,7 +1258,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_6 const1_0_ ( +sb_1__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1292,8 +1288,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1308,13 +1304,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1329,17 +1325,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_5 ( const1 ) ; +module sb_1__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1361,7 +1357,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +sb_1__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -1409,12 +1405,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_1__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1436,7 +1432,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_4 const1_0_ ( +sb_1__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -1484,7 +1480,49 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1500,59 +1538,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_3 ( const1 ) ; +module sb_1__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1569,7 +1565,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_3 const1_0_ ( +sb_1__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -1602,63 +1598,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_1__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_1 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1675,7 +1620,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_1 const1_0_ ( +sb_1__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -1708,8 +1653,63 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__const1_1 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sb_1__2__const1_1 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1724,17 +1724,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_0 ( const1 ) ; +module sb_1__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1752,7 +1752,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( +sb_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -1803,7 +1803,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -1843,6 +1845,8 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1931,7 +1935,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -1939,52 +1943,55 @@ mux_tree_tapbuf_size10 mux_right_track_0 ( chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -1994,8 +2001,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -2004,435 +2011,466 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size8 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_9 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v index e22ee70..2f359de 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -26,14 +26,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -77,7 +78,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -96,12 +97,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -115,19 +117,19 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -146,13 +148,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -170,13 +172,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -194,13 +196,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -218,13 +220,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -242,13 +244,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -266,12 +268,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -296,13 +299,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -333,7 +337,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -364,7 +369,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -395,7 +401,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -426,7 +433,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -457,7 +465,61 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -479,66 +541,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -573,7 +582,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -608,7 +618,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -643,7 +654,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -665,12 +676,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -710,7 +722,169 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -732,13 +906,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -759,223 +933,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1024,7 +988,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1073,7 +1038,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1122,7 +1088,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1137,7 +1104,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; @@ -1163,15 +1129,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1220,7 +1184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1269,7 +1234,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1318,7 +1284,87 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1343,42 +1389,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1431,7 +1448,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1484,8 +1502,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1509,13 +1527,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1539,13 +1557,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1625,7 +1643,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1705,7 +1724,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1730,72 +1809,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1853,61 +1873,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1965,8 +1932,67 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1990,12 +2016,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2072,7 +2099,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT , VDD , VSS ) ; + SC_OUT_TOP , SC_OUT_BOT , VDD , VSS , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -2114,6 +2143,8 @@ output SC_OUT_TOP ; output SC_OUT_BOT ; input VDD ; input VSS ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2204,7 +2235,7 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -2213,14 +2244,14 @@ mux_tree_tapbuf_size10 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , @@ -2228,8 +2259,8 @@ mux_tree_tapbuf_size9 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , @@ -2237,8 +2268,8 @@ mux_tree_tapbuf_size9_0 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , @@ -2246,26 +2277,29 @@ mux_tree_tapbuf_size9_1 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -2276,8 +2310,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -2287,20 +2321,22 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , @@ -2308,295 +2344,355 @@ mux_tree_tapbuf_size8 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_9 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_6 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_24 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1317 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1318 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1319 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1320 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1321 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1322 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1323 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1324 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1325 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1326 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1327 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1328 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1329 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1330 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1331 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1332 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1333 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1334 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1335 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1336 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1337 ( .VNB ( VSS ) , @@ -2631,1177 +2727,2103 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1351 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1352 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1353 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y27200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y54400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y81600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x432400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x929200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x966000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1002800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1113200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1150000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1186800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x998200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1044200y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x897000y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1127000y136000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x915400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1025800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1035000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y190400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x851000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1039600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1058000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x786600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1071800y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x920000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x938400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x749800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x929200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x975200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1012000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x846400y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1048800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x864800y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1067200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x197800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x924600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1058000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1076400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x515200y353600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1168400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x754400y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y380800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x285200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x294400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x782000y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x800400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x883200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x952200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1048800y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x308200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x671600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x841800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x924600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x970600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x989000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1085600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1104000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1113200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x653200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x906200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1007400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x809600y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x915400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1002800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1053400y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1099400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1108600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x878600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x897000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x956800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x966000y516800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1094800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x869400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x975200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1012000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1030400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1039600y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x96600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x133400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x303600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x975200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1094800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y571200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x345000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x961400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x979800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x989000y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1081000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x225400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x956800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1136200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1154600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1163800y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x740600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x901600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1035000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1053400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x855600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x874000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x450800y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x864800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x998200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1016600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1062600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1099400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1136200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1173000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1209800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x823400y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y707200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x933800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x943000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x851000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x860200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1039600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1076400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1113200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1159200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1196000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x676200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x809600y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x956800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x993600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1030400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1067200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1104000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1140800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1177600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1214400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1002800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1021200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x878600y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x933800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x970600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1007400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1025800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x947600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x984400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1021200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1058000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1094800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1131600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1150000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1205200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1223600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x469200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x924600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x961400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x998200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1035000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1071800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1108600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1145400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1182200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x979800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1016600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1053400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1090200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1127000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x1163800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x1200600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x1219000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x1228200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v index 1f771c2..36e4727 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_1__2__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -18,14 +18,14 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__60 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__61 ( .A ( mem_out[2] ) , .X ( net_net_89 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( .A ( net_net_89 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_117 ( .A ( net_net_89 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -61,7 +61,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -73,12 +73,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__60 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -88,17 +88,17 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_68 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -110,13 +110,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -127,13 +127,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -144,13 +144,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -161,13 +161,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -178,13 +178,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -195,12 +195,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -219,12 +219,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_95 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_119 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -248,7 +248,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -272,7 +272,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -296,7 +296,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -320,7 +320,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -344,7 +344,45 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__53 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__52 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -358,50 +396,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__52 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__51 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__51 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__50 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -429,7 +429,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -457,7 +457,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -485,7 +485,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -499,12 +499,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__49 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__50 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -536,7 +536,121 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__46 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__45 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -550,13 +664,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -569,166 +683,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__47 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__44 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__43 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_66 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -768,7 +728,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -808,7 +768,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -848,7 +808,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -861,7 +821,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -881,14 +840,11 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_128 ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -928,7 +884,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -968,7 +924,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1008,7 +964,68 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size7_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__41 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1024,33 +1041,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__40 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__40 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__39 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1094,7 +1090,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1138,8 +1134,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1154,13 +1150,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__38 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__39 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1175,12 +1171,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__37 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__38 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1248,7 +1244,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1316,7 +1312,49 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_1__2__mux_tree_tapbuf_size9_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__37 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__36 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1332,54 +1370,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__36 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__35 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__35 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__34 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_1 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1427,51 +1423,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:8] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_8 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size9_0 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1519,8 +1471,56 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_1__2__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +input [0:8] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[7] ) , .A1 ( in[6] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[8] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1535,12 +1535,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_1__2__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1607,7 +1607,9 @@ module sb_1__2_ ( prog_clk , chanx_right_in , right_top_grid_pin_1_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chanx_right_out , chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_TOP , SC_IN_BOT , - SC_OUT_TOP , SC_OUT_BOT ) ; + SC_OUT_TOP , SC_OUT_BOT , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 , + grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chanx_right_in ; input [0:0] right_top_grid_pin_1_ ; @@ -1647,6 +1649,8 @@ input SC_IN_TOP ; input SC_IN_BOT ; output SC_OUT_TOP ; output SC_OUT_BOT ; +input [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0 ; +output [0:0] grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1735,7 +1739,7 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size10 mux_right_track_0 ( +sb_1__2__mux_tree_tapbuf_size10 mux_right_track_0 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[5] , @@ -1743,52 +1747,55 @@ mux_tree_tapbuf_size10 mux_right_track_0 ( chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size10_mem mem_right_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size10_mem mem_right_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_right_track_2 ( +sb_1__2__mux_tree_tapbuf_size9 mux_right_track_2 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , chanx_left_in[4] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size9_0 mux_left_track_1 ( + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_0 mux_left_track_1 ( .in ( { chanx_right_in[2] , chanx_right_in[12] , chany_bottom_in[6] , chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( mux_tree_tapbuf_size9_1_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size9_1 mux_left_track_3 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_1 mux_left_track_3 ( .in ( { chanx_right_in[4] , chanx_right_in[13] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( mux_tree_tapbuf_size9_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size9_mem mem_right_track_2 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size9_mem mem_right_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_1_sram ) , .mem_outb ( mux_tree_tapbuf_size9_1_sram_inv ) ) ; -mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size9_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .mem_outb ( mux_tree_tapbuf_size9_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_right_track_4 ( +sb_1__2__mux_tree_tapbuf_size14 mux_right_track_4 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_38_[0] , @@ -1798,8 +1805,8 @@ mux_tree_tapbuf_size14 mux_right_track_4 ( chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size14_0 mux_left_track_5 ( + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_0 mux_left_track_5 ( .in ( { chanx_right_in[5] , chanx_right_in[14] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_35_[0] , @@ -1808,435 +1815,466 @@ mux_tree_tapbuf_size14_0 mux_left_track_5 ( left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size14_mem mem_right_track_4 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size14_mem mem_right_track_4 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size14_mem_0 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size8 mux_right_track_8 ( +sb_1__2__mux_tree_tapbuf_size8 mux_right_track_8 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , chanx_left_in[6] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size8_0 mux_left_track_9 ( + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_0 mux_left_track_9 ( .in ( { chanx_right_in[6] , chanx_right_in[16] , chany_bottom_in[2] , chany_bottom_in[9] , chany_bottom_in[16] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size8_mem mem_right_track_8 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size8_mem mem_right_track_8 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_6 mux_right_track_16 ( +sb_1__2__mux_tree_tapbuf_size7_6 mux_right_track_16 ( .in ( { right_bottom_grid_pin_34_[0] , right_bottom_grid_pin_38_[0] , chany_bottom_in[1] , chany_bottom_in[8] , chany_bottom_in[15] , chanx_left_in[8] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7 mux_right_track_24 ( + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7 mux_right_track_24 ( .in ( { right_bottom_grid_pin_35_[0] , right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , chany_bottom_in[7] , chany_bottom_in[14] , chanx_left_in[9] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_0 mux_bottom_track_1 ( .in ( { chanx_right_in[2] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[1] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_1 mux_bottom_track_3 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( { ropt_net_175 } ) , - .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_2 mux_bottom_track_5 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[5] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , + .out ( { ropt_net_145 } ) , + .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_3 mux_bottom_track_7 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[6] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_17 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_4 mux_left_track_17 ( .in ( { chanx_right_in[8] , chanx_right_in[17] , chany_bottom_in[3] , chany_bottom_in[10] , chany_bottom_in[17] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size7_5 mux_left_track_25 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_25 ( .in ( { chanx_right_in[9] , chanx_right_in[18] , chany_bottom_in[4] , chany_bottom_in[11] , chany_bottom_in[18] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size7_7_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , - .out ( { ropt_net_165 } ) , - .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_7_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_right_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_right_track_24 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem mem_right_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_7_sram ) , .mem_outb ( mux_tree_tapbuf_size7_7_sram_inv ) ) ; -mux_tree_tapbuf_size5 mux_right_track_32 ( +sb_1__2__mux_tree_tapbuf_size5 mux_right_track_32 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_40_[0] , chany_bottom_in[6] , chany_bottom_in[13] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size5_mem mem_right_track_32 ( .prog_clk ( prog_clk ) , + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size5_mem mem_right_track_32 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_bottom_track_9 ( +sb_1__2__mux_tree_tapbuf_size4 mux_bottom_track_9 ( .in ( { chanx_right_in[8] , bottom_left_grid_pin_42_[0] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_0 mux_bottom_track_11 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_43_[0] , chanx_left_in[9] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_158 ) ) ; -mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_25 ( .in ( { chanx_right_in[18] , chanx_right_in[19] , bottom_left_grid_pin_42_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size4_mem mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( +sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_13 ( .in ( { chanx_right_in[10] , bottom_left_grid_pin_44_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_15 ( .in ( { chanx_right_in[12] , bottom_left_grid_pin_45_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_17 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_46_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_140 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_3 mux_bottom_track_19 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_47_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_139 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_4 mux_bottom_track_21 ( .in ( { chanx_right_in[16] , bottom_left_grid_pin_48_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_161 ) ) ; -mux_tree_tapbuf_size3 mux_bottom_track_23 ( + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_23 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( mux_tree_tapbuf_size3_5_sram_inv ) , - .out ( { ropt_net_176 } ) , - .p0 ( optlc_net_160 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_153 } ) , + .p0 ( optlc_net_142 ) ) ; +sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_3 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem_4 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_5_sram ) , .mem_outb ( mux_tree_tapbuf_size3_5_sram_inv ) ) ; -mux_tree_tapbuf_size2 mux_bottom_track_27 ( +sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_27 ( .in ( { chanx_right_in[15] , bottom_left_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_157 ) ) ; -mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , + .out ( { ropt_net_147 } ) , + .p0 ( optlc_net_143 ) ) ; +sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_left_track_33 ( +sb_1__2__mux_tree_tapbuf_size6 mux_left_track_33 ( .in ( { chanx_right_in[10] , chany_bottom_in[5] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_159 ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_33 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_141 ) ) ; +sb_1__2__mux_tree_tapbuf_size6_mem mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) , - .ccff_tail ( { ropt_net_181 } ) , + .ccff_tail ( { ropt_net_165 } ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_5__4 ( .A ( chanx_right_in[4] ) , - .X ( chanx_left_out[5] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_799 ( .A ( ropt_net_179 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_165 ) , - .X ( ropt_net_200 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_10__9 ( .A ( chanx_right_in[9] ) , - .X ( chanx_left_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chanx_right_in[10] ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_751 ( .A ( ropt_net_166 ) , - .X ( ropt_net_208 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_13__12 ( .A ( chanx_right_in[12] ) , - .X ( ropt_net_186 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_196 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_168 ) , - .X ( chanx_right_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_193 ) , - .X ( chanx_left_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_170 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_756 ( .A ( chanx_right_in[1] ) , - .X ( ropt_net_214 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_789 ( .A ( ropt_net_194 ) , - .X ( chanx_right_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , - .X ( chanx_right_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_172 ) , - .X ( ropt_net_202 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_790 ( .A ( ropt_net_195 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_758 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_212 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_759 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_26__25 ( .A ( chanx_left_in[10] ) , - .X ( ropt_net_207 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_27__26 ( .A ( chanx_left_in[12] ) , - .X ( ropt_net_187 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_175 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , - .X ( ropt_net_189 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_791 ( .A ( ropt_net_196 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_31__30 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_185 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( ropt_net_176 ) , - .X ( ropt_net_209 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_792 ( .A ( ropt_net_197 ) , - .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_794 ( .A ( ropt_net_198 ) , - .X ( chanx_left_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_199 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_796 ( .A ( ropt_net_200 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_201 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_798 ( .A ( ropt_net_202 ) , - .X ( chany_bottom_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_203 ) , - .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_77 ( .A ( chanx_right_in[14] ) , - .X ( BUF_net_77 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_78 ( .A ( chanx_right_in[16] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_79 ( .A ( chanx_right_in[17] ) , - .X ( BUF_net_79 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( chanx_right_in[5] ) , - .X ( ropt_net_210 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_81 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_82 ( .A ( chanx_left_in[5] ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_right_in[7] ) , - .X ( ropt_net_215 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_84 ( .A ( chanx_left_in[9] ) , - .X ( BUF_net_84 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_right_in[2] ) , - .X ( ropt_net_211 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( chanx_left_in[13] ) , - .X ( ropt_net_213 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_181 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_182 ) , - .X ( ropt_net_198 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_769 ( .A ( ropt_net_183 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_770 ( .A ( ropt_net_184 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_185 ) , - .X ( chanx_right_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_186 ) , - .X ( ropt_net_197 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_187 ) , - .X ( chanx_right_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_188 ) , - .X ( ropt_net_201 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_189 ) , - .X ( chanx_right_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_190 ) , - .X ( ropt_net_199 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_803 ( .A ( ropt_net_204 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_205 ) , - .X ( chanx_right_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_805 ( .A ( ropt_net_206 ) , - .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_806 ( .A ( ropt_net_207 ) , - .X ( chanx_right_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_807 ( .A ( ropt_net_208 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_119 ( .A ( chanx_right_in[8] ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_120 ( .A ( chanx_right_in[13] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_800 ( .A ( ropt_net_180 ) , .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_121 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_122 ( .A ( chanx_left_in[8] ) , - .X ( ropt_net_188 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_808 ( .A ( ropt_net_209 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_809 ( .A ( ropt_net_210 ) , - .X ( chanx_left_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_211 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chanx_right_in[2] ) , .X ( chanx_left_out[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_133 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__conb_1 optlc_132 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_140 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__6 ( .A ( chanx_right_in[6] ) , .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_812 ( .A ( ropt_net_212 ) , - .X ( chanx_right_out[7] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_213 ) , - .X ( chanx_right_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_136 ( .A ( BUF_net_77 ) , +sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_141 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chanx_right_in[8] ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_142 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_757 ( .A ( ropt_net_144 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_145 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__13 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__14 ( .A ( chanx_right_in[14] ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_181 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__16 ( .A ( chanx_right_in[17] ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_802 ( .A ( ropt_net_182 ) , .X ( chanx_left_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_137 ( .A ( BUF_net_79 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_214 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_146 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_147 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__20 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__21 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chanx_right_in[12] ) , + .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_762 ( .A ( ropt_net_149 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_139 ( .A ( BUF_net_84 ) , - .X ( chanx_right_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_215 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_141 ( .A ( chanx_left_in[18] ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_764 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_152 ) , .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_766 ( .A ( ropt_net_153 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_29__28 ( .A ( chanx_left_in[14] ) , + .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_767 ( .A ( chanx_left_in[10] ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chanx_right_in[7] ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( .A ( chanx_left_in[8] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_33__32 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_144 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_803 ( .A ( ropt_net_183 ) , + .X ( chany_bottom_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_804 ( .A ( ropt_net_184 ) , + .X ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_185 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_71 ( .A ( chanx_right_in[3] ) , + .X ( BUF_net_71 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_186 ) , + .X ( chanx_right_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_807 ( .A ( ropt_net_187 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_808 ( .A ( ropt_net_188 ) , + .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_771 ( .A ( chanx_right_in[0] ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( chanx_right_in[11] ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_809 ( .A ( ropt_net_189 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_811 ( .A ( ropt_net_190 ) , + .X ( chanx_right_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_79 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_191 ) , + .X ( chanx_left_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_813 ( .A ( ropt_net_192 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_193 ) , + .X ( chanx_right_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_815 ( .A ( ropt_net_194 ) , + .X ( chanx_right_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_816 ( .A ( ropt_net_195 ) , + .X ( SC_OUT_BOT ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_817 ( .A ( ropt_net_196 ) , + .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_86 ( + .A ( grid_clb_0_bottom_width_0_height_0__pin_50___FEEDTHRU_0[0] ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_818 ( .A ( ropt_net_197 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_93 ( .A ( chanx_right_in[1] ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( chanx_left_in[17] ) , + .X ( chanx_right_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( chanx_right_in[4] ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_777 ( .A ( chanx_left_in[18] ) , + .X ( chanx_right_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_97 ( .A ( chanx_right_in[10] ) , + .X ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( chanx_left_in[13] ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_779 ( .A ( chanx_left_in[16] ) , + .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( chanx_right_in[18] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_784 ( .A ( ropt_net_166 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_108 ( .A ( chanx_right_in[9] ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chanx_left_in[9] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chanx_left_in[12] ) , + .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_819 ( .A ( ropt_net_198 ) , + .X ( chanx_right_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_820 ( .A ( ropt_net_199 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_116 ( .A ( chanx_right_in[16] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_121 ( .A ( BUF_net_71 ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_167 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_821 ( .A ( ropt_net_200 ) , + .X ( chanx_right_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_124 ( .A ( BUF_net_97 ) , + .X ( chanx_left_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_823 ( .A ( ropt_net_201 ) , + .X ( chanx_right_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_824 ( .A ( ropt_net_202 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_168 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_169 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_170 ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_789 ( .A ( ropt_net_171 ) , + .X ( chanx_right_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_790 ( .A ( ropt_net_172 ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_173 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_794 ( .A ( ropt_net_174 ) , + .X ( chanx_right_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_797 ( .A ( ropt_net_175 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_176 ) , + .X ( chanx_right_out[15] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v index aac13eb..fa5e8ab 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,8 +23,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -42,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -61,8 +61,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -80,12 +80,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module const1 ( const1 ) ; +module sb_2__0__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -97,7 +97,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1 const1_0_ ( +sb_2__0__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -115,12 +115,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_28 ( const1 ) ; +module sb_2__0__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -132,7 +132,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_28 const1_0_ ( +sb_2__0__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -150,12 +150,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_27 ( const1 ) ; +module sb_2__0__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -167,7 +167,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_27 const1_0_ ( +sb_2__0__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -185,12 +185,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_26 ( const1 ) ; +module sb_2__0__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -202,10 +202,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_26 const1_0_ ( +sb_2__0__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -217,11 +215,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -232,15 +232,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -256,8 +256,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -273,8 +273,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -290,8 +290,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -307,8 +307,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -324,8 +324,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -341,8 +341,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -358,8 +358,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -375,8 +375,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -392,8 +392,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -409,8 +409,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -426,7 +426,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -443,8 +443,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -460,8 +460,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -477,8 +477,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -494,8 +494,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -511,8 +511,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -528,8 +528,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -545,8 +545,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -562,12 +562,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module const1_25 ( const1 ) ; +module sb_2__0__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -577,78 +577,24 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_25 const1_0_ ( +sb_2__0__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_24 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_24 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module const1_23 ( const1 ) ; +module sb_2__0__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_23 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_22 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -657,7 +603,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_22 const1_0_ ( +sb_2__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -666,12 +612,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_21 ( const1 ) ; +module sb_2__0__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -681,24 +627,24 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_21 const1_0_ ( +sb_2__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_20 ( const1 ) ; +module sb_2__0__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -708,7 +654,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20 const1_0_ ( +sb_2__0__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -720,12 +666,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19 ( const1 ) ; +module sb_2__0__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -735,7 +681,215 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19 const1_0_ ( +sb_2__0__const1_21 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_20 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_20 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_19 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_2__0__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sb_2__0__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__0__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -747,12 +901,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18 ( const1 ) ; +module sb_2__0__const1_12 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -762,7 +916,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_18 const1_0_ ( +sb_2__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -774,12 +928,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17 ( const1 ) ; +module sb_2__0__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -789,7 +943,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17 const1_0_ ( +sb_2__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -801,12 +955,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16 ( const1 ) ; +module sb_2__0__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -816,7 +970,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_16 const1_0_ ( +sb_2__0__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -828,12 +982,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15 ( const1 ) ; +module sb_2__0__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -843,7 +997,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_15 const1_0_ ( +sb_2__0__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -855,12 +1009,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_14 ( const1 ) ; +module sb_2__0__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -870,7 +1024,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_14 const1_0_ ( +sb_2__0__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -882,12 +1036,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_13 ( const1 ) ; +module sb_2__0__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -897,7 +1051,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_13 const1_0_ ( +sb_2__0__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -909,12 +1063,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_12 ( const1 ) ; +module sb_2__0__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -924,7 +1078,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_12 const1_0_ ( +sb_2__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -936,170 +1090,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_6 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_6 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1115,7 +1107,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1132,12 +1124,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module const1_5 ( const1 ) ; +module sb_2__0__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1148,7 +1140,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_5 const1_0_ ( +sb_2__0__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -1163,12 +1155,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_2__0__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1179,7 +1171,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_4 const1_0_ ( +sb_2__0__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -1194,7 +1186,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1213,8 +1205,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1232,12 +1224,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module const1_3 ( const1 ) ; +module sb_2__0__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1250,7 +1242,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_3 const1_0_ ( +sb_2__0__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1271,12 +1263,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_2__0__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1289,7 +1281,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_2 const1_0_ ( +sb_2__0__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1310,7 +1302,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1329,8 +1321,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1348,12 +1340,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module const1_1 ( const1 ) ; +module sb_2__0__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1367,7 +1359,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1 const1_0_ ( +sb_2__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1391,12 +1383,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module sb_2__0__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1410,8 +1402,10 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0 const1_0_ ( +sb_2__0__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1429,8 +1423,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1556,391 +1548,450 @@ wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // -mux_tree_tapbuf_size6_0 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5 mux_top_track_6 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_26 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_7 ( + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v index b049ff9..ec8914c 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -31,8 +31,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -58,8 +58,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -85,8 +85,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -112,7 +112,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -147,7 +148,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -182,7 +184,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -217,7 +220,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -233,9 +237,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -249,11 +250,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -271,15 +275,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -302,8 +306,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -326,8 +330,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -350,8 +354,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -374,8 +378,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -398,8 +402,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -422,8 +426,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -446,8 +450,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -470,8 +474,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -494,8 +498,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -518,8 +522,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -542,7 +546,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -566,8 +570,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -590,8 +594,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -614,8 +618,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -638,8 +642,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -662,8 +666,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -686,8 +690,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -710,8 +714,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -734,8 +738,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -749,71 +753,20 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -835,7 +788,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -855,13 +809,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -887,7 +842,216 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -913,7 +1077,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -939,7 +1104,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -965,7 +1131,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -991,7 +1158,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1017,8 +1185,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1044,7 +1212,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1070,8 +1239,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1097,170 +1266,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1283,7 +1290,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1307,7 +1314,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1338,7 +1346,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1369,7 +1378,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1396,8 +1405,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1423,7 +1432,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1463,7 +1473,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1503,7 +1514,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1530,8 +1541,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1557,7 +1568,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1601,7 +1613,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1619,6 +1632,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1639,9 +1655,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; endmodule @@ -1771,380 +1784,428 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size6_0 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5 mux_top_track_6 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_26 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_7 ( + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1354 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1355 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1356 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1357 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1358 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1359 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1360 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1361 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1362 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1363 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1364 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1365 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1366 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1367 ( .VNB ( VSS ) , @@ -2177,74 +2238,118 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1380 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1381 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1382 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y0 ( @@ -2259,45 +2364,51 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -2305,1053 +2416,1507 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x165600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x381800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x138000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y108800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x381800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y136000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x119600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x464600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x216200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x266800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x450800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x170200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x529000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y299200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y326400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x662400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x754400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y380800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x59800y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x515200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x478400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x64400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x156400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x473800y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x579600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x294400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x271400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x386400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x464600y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x510600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x322000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x828000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x864800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x395600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x731400y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x538200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x119600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x174800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x363400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x542800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x266800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x487600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x478400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x395600y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x731400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x358800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x524400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x717600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x354200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x740600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v index d0a9d2b..507d5cd 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__0__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,8 +23,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__39 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -42,8 +42,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__38 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -61,8 +61,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__37 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -80,7 +80,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__36 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -108,7 +108,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -136,7 +136,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -164,7 +164,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -176,8 +176,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -189,11 +187,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_100 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -204,15 +204,15 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_26__35 ( .A ( mem_out[1] ) , - .X ( net_net_71 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_71 ( .A ( net_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__35 ( .A ( mem_out[1] ) , + .X ( net_net_61 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_61 ( .A ( net_net_61 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -228,8 +228,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -245,8 +245,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -262,8 +262,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -279,8 +279,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -296,8 +296,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -313,8 +313,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -330,8 +330,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -347,8 +347,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -364,8 +364,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -381,8 +381,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -398,7 +398,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -415,8 +415,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -432,8 +432,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -449,8 +449,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -466,8 +466,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -483,8 +483,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -500,8 +500,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -517,8 +517,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -534,7 +534,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -544,57 +544,17 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_51 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -610,7 +570,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -625,12 +585,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_49 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -650,7 +610,159 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_96 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_95 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_94 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_43 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_41 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_89 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__0__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -670,7 +782,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -690,7 +802,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -710,7 +822,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -730,7 +842,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -750,7 +862,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -770,7 +882,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -790,7 +902,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -810,128 +922,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -947,7 +939,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -964,7 +956,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -988,7 +980,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1012,7 +1004,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1031,8 +1023,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1050,7 +1042,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1082,7 +1074,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1114,7 +1106,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__0__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1133,8 +1125,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__0__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1152,7 +1144,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1188,7 +1180,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__0__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1202,6 +1194,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1219,8 +1213,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_40 ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -1346,391 +1338,450 @@ wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ; wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ; // -mux_tree_tapbuf_size6_0 mux_top_track_0 ( +sb_2__0__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[0] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( { ropt_net_109 } ) , - .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size6 mux_top_track_4 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( chany_top_out[0] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size6 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chany_top_out[2] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size6_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_top_track_2 ( +sb_2__0__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5 mux_top_track_6 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5 mux_top_track_6 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[3] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size5_mem mem_top_track_6 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size3 mux_top_track_8 ( +sb_2__0__mux_tree_tapbuf_size3 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size3_0 mux_top_track_24 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_24 ( .in ( { top_left_grid_pin_42_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , + .out ( chany_top_out[12] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size3_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_24 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_12 mux_top_track_10 ( +sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_10 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_13 mux_top_track_12 ( + .out ( chany_top_out[5] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_12 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_14 mux_top_track_14 ( + .out ( chany_top_out[6] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_15 mux_top_track_16 ( + .out ( chany_top_out[7] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_15 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_16 mux_top_track_18 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_16 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_17 mux_top_track_20 ( + .out ( chany_top_out[9] ) , .p0 ( optlc_net_112 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_17 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_18 mux_top_track_22 ( + .out ( chany_top_out[10] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_18 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2 mux_top_track_26 ( + .out ( chany_top_out[11] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2 mux_top_track_26 ( .in ( { top_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_9 ( + .out ( chany_top_out[13] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_11 mux_left_track_9 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , + .out ( { ropt_net_123 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_0 mux_left_track_11 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_13 ( + .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , + .out ( { ropt_net_122 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_1 mux_left_track_13 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_113 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_2 mux_left_track_15 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_17 ( + .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , + .out ( { ropt_net_124 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_3 mux_left_track_17 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_4 mux_left_track_19 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_5 mux_left_track_25 ( + .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , + .out ( { ropt_net_130 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_5 mux_left_track_25 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_6 mux_left_track_27 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( { ropt_net_131 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_6 mux_left_track_27 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( { ropt_net_108 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_7 mux_left_track_29 ( + .out ( { ropt_net_121 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_7 mux_left_track_29 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( { ropt_net_103 } ) , - .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_8 mux_left_track_31 ( + .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_8 mux_left_track_31 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_99 ) ) ; -mux_tree_tapbuf_size2_9 mux_left_track_33 ( + .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , + .out ( { ropt_net_119 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_9 mux_left_track_33 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_35 ( + .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , + .out ( { ropt_net_120 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_10 mux_left_track_35 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_100 ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , + .out ( { ropt_net_126 } ) , + .p0 ( optlc_net_114 ) ) ; +sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_10 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_12 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_14 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_top_track_18 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_top_track_20 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_top_track_22 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem mem_top_track_26 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_left_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , - .ccff_tail ( { ropt_net_105 } ) , + .ccff_tail ( { ropt_net_134 } ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_1 ( +sb_2__0__mux_tree_tapbuf_size4_0 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_128 } ) , + .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_1 mux_left_track_3 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_2 mux_left_track_5 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_102 ) ) ; -mux_tree_tapbuf_size4 mux_left_track_7 ( + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4 mux_left_track_7 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_101 ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_111 ) ) ; +sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[1] ) , - .X ( ropt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[9] ) , - .X ( ropt_net_113 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_89 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_99 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_697 ( .A ( ropt_net_118 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_100 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_101 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_698 ( .A ( ropt_net_119 ) , - .X ( chanx_left_out[18] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_102 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_685 ( .A ( ropt_net_103 ) , - .X ( ropt_net_118 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_699 ( .A ( ropt_net_120 ) , - .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[1] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_55 ( .A ( chanx_left_in[3] ) , - .X ( ropt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_56 ( .A ( chanx_left_in[4] ) , - .X ( BUF_net_56 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_57 ( .A ( chanx_left_in[5] ) , - .X ( BUF_net_57 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_700 ( .A ( ropt_net_121 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_687 ( .A ( ropt_net_105 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_RR_66 ( .A ( BUF_net_56 ) , - .X ( chany_top_out[16] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_107 ) , - .X ( ropt_net_122 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_701 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_690 ( .A ( ropt_net_108 ) , - .X ( ropt_net_124 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_84 ( .A ( chanx_left_in[2] ) , - .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_85 ( .A ( BUF_net_57 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_86 ( .A ( chanx_left_in[6] ) , - .X ( ropt_net_107 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_109 ) , - .X ( chany_top_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_110 ) , - .X ( ropt_net_121 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_111 ) , - .X ( ropt_net_120 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_112 ) , - .X ( ropt_net_119 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_113 ) , - .X ( ropt_net_123 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_696 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__conb_1 optlc_106 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_111 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_112 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_736 ( .A ( ropt_net_146 ) , .X ( chanx_left_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_703 ( .A ( ropt_net_123 ) , - .X ( chanx_left_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_704 ( .A ( ropt_net_124 ) , +sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_113 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__4 ( .A ( chanx_left_in[1] ) , + .X ( ropt_net_133 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__5 ( .A ( chanx_left_in[2] ) , + .X ( ropt_net_136 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_114 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_715 ( .A ( ropt_net_119 ) , + .X ( ropt_net_151 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_716 ( .A ( ropt_net_120 ) , + .X ( ropt_net_148 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__9 ( .A ( chanx_left_in[6] ) , + .X ( ropt_net_139 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_737 ( .A ( ropt_net_147 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_738 ( .A ( ropt_net_148 ) , + .X ( chanx_left_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_739 ( .A ( ropt_net_149 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_740 ( .A ( ropt_net_150 ) , + .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_717 ( .A ( ropt_net_121 ) , + .X ( ropt_net_154 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_718 ( .A ( ropt_net_122 ) , + .X ( ropt_net_155 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_741 ( .A ( ropt_net_151 ) , + .X ( chanx_left_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_719 ( .A ( ropt_net_123 ) , + .X ( ropt_net_153 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_81 ( .A ( chanx_left_in[3] ) , + .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_82 ( .A ( chanx_left_in[4] ) , + .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_83 ( .A ( chanx_left_in[5] ) , + .X ( ropt_net_138 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_720 ( .A ( ropt_net_124 ) , + .X ( chanx_left_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( .A ( ropt_net_152 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_153 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_721 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_161 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_722 ( .A ( ropt_net_126 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_723 ( .A ( chany_top_in[9] ) , + .X ( ropt_net_162 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_724 ( .A ( ropt_net_128 ) , + .X ( ropt_net_157 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_725 ( .A ( chany_top_in[2] ) , + .X ( ropt_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_726 ( .A ( ropt_net_130 ) , + .X ( ropt_net_159 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_727 ( .A ( ropt_net_131 ) , + .X ( ropt_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_728 ( .A ( chany_top_in[1] ) , + .X ( ropt_net_146 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_729 ( .A ( ropt_net_133 ) , + .X ( ropt_net_147 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_730 ( .A ( ropt_net_134 ) , + .X ( ropt_net_152 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_731 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_732 ( .A ( ropt_net_136 ) , + .X ( ropt_net_150 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_733 ( .A ( ropt_net_137 ) , + .X ( ropt_net_149 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_734 ( .A ( ropt_net_138 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_735 ( .A ( ropt_net_139 ) , + .X ( ropt_net_156 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_154 ) , .X ( chanx_left_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_705 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_155 ) , + .X ( chanx_left_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_156 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_157 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_158 ) , + .X ( chanx_left_out[12] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( .A ( ropt_net_159 ) , + .X ( chanx_left_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_754 ( .A ( ropt_net_160 ) , + .X ( chanx_left_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_161 ) , .X ( chanx_left_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_162 ) , + .X ( chanx_left_out[11] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v index 2b9876d..0417782 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.fm.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16,15 +16,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -35,13 +37,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -52,13 +54,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -69,13 +71,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -86,13 +88,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -103,17 +105,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1 ( const1 ) ; +module sb_2__1__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -123,7 +125,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1 const1_0_ ( +sb_2__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -135,12 +137,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_31 ( const1 ) ; +module sb_2__1__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -150,7 +152,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31 const1_0_ ( +sb_2__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -162,12 +164,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30 ( const1 ) ; +module sb_2__1__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -177,7 +179,34 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30 const1_0_ ( +sb_2__1__const1_30 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_29 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__1__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -189,12 +218,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29 ( const1 ) ; +module sb_2__1__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -204,7 +233,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29 const1_0_ ( +sb_2__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -216,12 +245,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28 ( const1 ) ; +module sb_2__1__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -231,46 +260,19 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_28 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_27 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_27 const1_0_ ( +sb_2__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -282,13 +284,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -299,13 +301,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -316,13 +318,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -333,13 +335,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -350,17 +352,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_26 ( const1 ) ; +module sb_2__1__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -371,38 +373,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_26 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_25 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -const1_25 const1_0_ ( +sb_2__1__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -417,12 +388,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_24 ( const1 ) ; +module sb_2__1__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -433,7 +404,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_24 const1_0_ ( +sb_2__1__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -448,12 +419,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_23 ( const1 ) ; +module sb_2__1__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -464,7 +435,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_23 const1_0_ ( +sb_2__1__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -479,12 +450,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_22 ( const1 ) ; +module sb_2__1__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -495,7 +466,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_22 const1_0_ ( +sb_2__1__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -510,7 +481,95 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__const1_22 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sb_2__1__const1_22 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -524,74 +583,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_21 ( const1 ) ; +module sb_2__1__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -603,7 +605,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_21 const1_0_ ( +sb_2__1__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -621,12 +623,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_20 ( const1 ) ; +module sb_2__1__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -638,7 +640,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_20 const1_0_ ( +sb_2__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -656,12 +658,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_19 ( const1 ) ; +module sb_2__1__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -673,7 +675,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_19 const1_0_ ( +sb_2__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; @@ -691,12 +693,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_18 ( const1 ) ; +module sb_2__1__const1_18 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -708,10 +710,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -const1_18 const1_0_ ( +sb_2__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -723,10 +723,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -742,17 +744,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_17 ( const1 ) ; +module sb_2__1__const1_17 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -769,7 +771,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -const1_17 const1_0_ ( +sb_2__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; @@ -802,7 +804,45 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -816,55 +856,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_16 ( const1 ) ; +module sb_2__1__const1_16 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -878,7 +880,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_16 const1_0_ ( +sb_2__1__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -902,12 +904,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_15 ( const1 ) ; +module sb_2__1__const1_15 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -921,7 +923,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_15 const1_0_ ( +sb_2__1__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -945,12 +947,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_14 ( const1 ) ; +module sb_2__1__const1_14 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -964,10 +966,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_14 const1_0_ ( +sb_2__1__const1_14 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -985,10 +985,107 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1002,13 +1099,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1021,112 +1118,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; +module sb_2__1__const1_13 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1141,7 +1143,101 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_13 const1_0_ ( +sb_2__1__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_11 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sb_2__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1168,12 +1264,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_12 ( const1 ) ; +module sb_2__1__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1188,7 +1284,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_12 const1_0_ ( +sb_2__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1210,17 +1306,17 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_11 ( const1 ) ; +module sb_2__1__const1_9 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1235,7 +1331,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_11 const1_0_ ( +sb_2__1__const1_9 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1262,12 +1358,55 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_10 ( const1 ) ; +module sb_2__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sb_2__1__const1_8 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_7 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1282,7 +1421,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -const1_10 const1_0_ ( +sb_2__1__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; @@ -1309,149 +1448,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module const1_7 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -const1_7 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1466,13 +1464,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1487,17 +1485,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_6 ( const1 ) ; +module sb_2__1__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1519,7 +1517,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_6 const1_0_ ( +sb_2__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -1567,12 +1565,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module sb_2__1__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1594,7 +1592,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_5 const1_0_ ( +sb_2__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_13_X[0] ) , .X ( out[0] ) ) ; @@ -1642,7 +1640,28 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1658,13 +1677,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1679,38 +1698,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module const1_4 ( const1 ) ; +module sb_2__1__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1726,7 +1724,58 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_4 const1_0_ ( +sb_2__1__const1_4 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__const1_3 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sb_2__1__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1756,12 +1805,12 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_3 ( const1 ) ; +module sb_2__1__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1777,7 +1826,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -const1_3 const1_0_ ( +sb_2__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; @@ -1807,59 +1856,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module const1_2 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -const1_2 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1874,13 +1872,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1895,17 +1893,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module const1_1 ( const1 ) ; +module sb_2__1__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1923,7 +1921,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_1 const1_0_ ( +sb_2__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -1955,18 +1953,16 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule -module const1_0 ( const1 ) ; +module sb_2__1__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1984,7 +1980,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -const1_0 const1_0_ ( +sb_2__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; @@ -2033,7 +2029,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2069,6 +2065,8 @@ output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2170,71 +2168,75 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // -mux_tree_tapbuf_size10 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8 mux_top_track_8 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -2243,8 +2245,8 @@ mux_tree_tapbuf_size14 mux_top_track_4 ( chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -2253,425 +2255,512 @@ mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) ) ; + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v index dd4256c..0744bc4 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.lvs.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -23,15 +23,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -49,13 +51,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -73,13 +75,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -97,13 +99,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -121,13 +123,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -145,12 +147,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -176,7 +179,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -202,7 +206,35 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -228,7 +260,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -254,33 +287,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -300,13 +308,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -325,13 +333,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -349,13 +357,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -373,13 +381,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -397,13 +405,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -421,43 +429,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -488,7 +466,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -519,7 +498,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -550,7 +530,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -581,7 +562,120 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -603,93 +697,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -724,7 +738,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -759,7 +774,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -794,7 +810,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -810,9 +827,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -826,10 +840,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -854,12 +871,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -917,7 +935,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -939,66 +1011,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1042,7 +1061,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1086,7 +1106,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1104,9 +1125,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1127,10 +1145,148 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1152,13 +1308,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1179,147 +1335,113 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; -input VDD ; -input VSS ; - -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1368,7 +1490,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1411,13 +1534,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1466,7 +1590,54 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1515,155 +1686,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1687,13 +1711,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1717,13 +1741,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1803,7 +1827,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1883,7 +1908,37 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; +input VDD ; +input VSS ; + +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1908,13 +1963,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1938,42 +1993,67 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; input VDD ; input VSS ; +input p0 ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2026,7 +2106,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2079,61 +2160,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2157,13 +2185,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -2187,13 +2215,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2250,14 +2278,13 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -2332,7 +2359,8 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail , VDD , VSS ) ; + chanx_left_out , ccff_tail , VDD , VSS , Test_en__FEEDTHRU_0 , + Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -2370,6 +2398,8 @@ output [0:19] chanx_left_out ; output [0:0] ccff_tail ; input VDD ; input VSS ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -2473,7 +2503,7 @@ supply1 VDD ; supply0 VSS ; // -mux_tree_tapbuf_size10 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , @@ -2481,29 +2511,30 @@ mux_tree_tapbuf_size10 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , @@ -2511,42 +2542,44 @@ mux_tree_tapbuf_size8_1 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8 mux_top_track_8 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -2556,8 +2589,8 @@ mux_tree_tapbuf_size14 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -2567,159 +2600,168 @@ mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_24 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size9 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , @@ -2727,218 +2769,217 @@ mux_tree_tapbuf_size9 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_25 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1383 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1384 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1385 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1386 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1387 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1388 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1389 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1390 ( .VNB ( VSS ) , - .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1391 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1392 ( .VNB ( VSS ) , @@ -2961,243 +3002,384 @@ sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1400 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1401 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1402 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1419 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1420 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1421 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1422 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1423 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1424 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1425 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1426 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1427 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1428 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_220 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , + .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) , .VPWR ( VDD ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x377200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x593400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y54400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y27200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y54400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x800400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y81600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y81600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y81600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3205,651 +3387,881 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x377200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x542800y163200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x460000y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y217600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y244800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x202400y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x69000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x105800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x124200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x400200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x437000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x777400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x151800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x437000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x487600y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x602600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x791200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x78200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x184000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x814200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y353600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x69000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x478400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x496800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y408000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x846400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x248400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x602600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x745200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x823400y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x326600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x519800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x345000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x616400y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x657800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y435200 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y435200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x680800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x161000y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x179400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x814200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y462400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x69000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x128800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x248400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y489600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x473800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y489600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x763600y489600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x170200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x110400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x253000y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x639400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x455400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x561200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x506000y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x542800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y544000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x749800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x818800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x161000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y571200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x308200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x363400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x400200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x501400y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x584200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x832600y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x211600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x262200y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x671600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y598400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y598400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x105800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x340400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x791200y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x837200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x855600y598400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x289800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x211600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x115000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x322000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x432400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x611800y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y652800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x713000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x837200y652800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x197800y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x147200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x285200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x446200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y680000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y680000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x805000y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x763600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x207000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x404800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x579600y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x556600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y707200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x809600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x818800y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y707200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x193200y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x225400y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x142600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x510600y734400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x621000y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y734400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x703800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x722200y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y734400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3857,179 +4269,397 @@ sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x115000y761600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x124200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x207000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x243800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x253000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x441600y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x506000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y761600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x524400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x303600y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y816000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y816000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y816000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y816000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y843200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x156400y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y843200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y816000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x225400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x496800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x418600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y843200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y843200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y843200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y870400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y870400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y870400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y897600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x492200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x510600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x736000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x828000y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x593400y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y897600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x391000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x722200y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y897600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x437000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y897600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y897600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y897600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y924800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x588800y897600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y924800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x901600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x938400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y924800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y924800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y924800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y924800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x128800y924800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x607200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x745200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y952000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y952000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x391000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x690000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y952000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y952000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y979200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y952000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y979200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y979200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1006400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1006400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y1033600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y1060800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y1060800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y1060800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v index 35225a7..67887b2 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__1__icv_in_design.pt.v @@ -4,7 +4,7 @@ // // // -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -16,15 +16,17 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__59 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__60 ( .A ( mem_out[1] ) , .X ( net_net_91 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_90 ( .A ( net_net_91 ) , +sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_91 ( .A ( net_net_91 ) , + .X ( net_net_90 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_126 ( .A ( net_net_90 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -35,13 +37,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__58 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__59 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -52,13 +54,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__57 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__58 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -69,13 +71,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__56 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__57 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -86,13 +88,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__55 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__56 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -103,12 +105,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__54 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__55 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -128,7 +130,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -148,7 +150,27 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_79 ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -168,7 +190,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -188,27 +210,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -223,12 +225,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_125 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -240,13 +242,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__53 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__54 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -257,13 +259,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__52 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__53 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -274,13 +276,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__51 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -291,13 +293,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__50 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__51 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -308,36 +310,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__49 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__50 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_124 ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -361,7 +339,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -385,7 +363,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -409,7 +387,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -433,7 +411,88 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_135 ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__49 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__48 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__47 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -447,69 +506,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__48 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__46 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size4_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__47 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__46 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__45 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_2 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -537,7 +539,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_1 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -565,7 +567,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4_0 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -593,7 +595,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size4 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -605,8 +607,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -618,10 +618,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_134 ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size9_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -637,12 +639,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_18__44 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__45 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size9 ( in , sram , sram_inv , out , p0 ) ; input [0:8] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -690,7 +692,45 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__44 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__43 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -704,50 +744,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__43 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__42 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__42 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__41 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -783,7 +785,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -819,7 +821,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -833,8 +835,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -852,10 +852,107 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_133 ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size7_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__41 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__40 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__39 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__38 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:2] mem_out ; +output [0:2] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__37 ( .A ( mem_out[2] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -869,13 +966,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__40 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__36 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -888,107 +985,92 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__39 ( .A ( mem_out[2] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__35 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__38 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_98 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__37 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_67 ( + .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__36 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__35 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:2] mem_out ; -output [0:2] mem_outb ; - -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__34 ( .A ( mem_out[2] ) , - .X ( ccff_tail[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_4 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1028,7 +1110,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1063,12 +1145,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_123 ( +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_P_130 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size7_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1108,7 +1190,43 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; +input [0:6] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; input [0:6] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1148,128 +1266,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size7_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size7_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:6] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( p0 ) , .A1 ( in[6] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1284,13 +1282,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__33 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__34 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size14_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1305,12 +1303,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__32 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__33 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14_0 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1378,7 +1376,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size14 ( in , sram , sram_inv , out , p0 ) ; input [0:13] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1446,7 +1444,28 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , ccff_tail , +module sb_2__1__mux_tree_tapbuf_size8_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; +input [0:0] prog_clk ; +input [0:0] ccff_head ; +output [0:0] ccff_tail ; +output [0:3] mem_out ; +output [0:3] mem_outb ; + +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; +sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , + .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__32 ( .A ( mem_out[3] ) , + .X ( ccff_tail[0] ) ) ; +endmodule + + +module sb_2__1__mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1462,13 +1481,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__31 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__31 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1483,33 +1502,56 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__30 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__30 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; -input [0:0] prog_clk ; -input [0:0] ccff_head ; -output [0:0] ccff_tail ; -output [0:3] mem_out ; -output [0:3] mem_outb ; +module sb_2__1__mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:7] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[0] ) , .Q_N ( mem_outb[0] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; -sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__29 ( .A ( mem_out[3] ) , - .X ( ccff_tail[0] ) ) ; +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_62 ( + .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size8_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1553,7 +1595,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; input [0:7] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1597,52 +1639,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module mux_tree_tapbuf_size8_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:7] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[4] ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[6] ) , .A1 ( in[5] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1657,13 +1655,13 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__28 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__29 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__1__mux_tree_tapbuf_size10_mem ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1678,12 +1676,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[2] ) , .Q_N ( mem_outb[2] ) ) ; sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[3] ) , .Q_N ( mem_outb[3] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__27 ( .A ( mem_out[3] ) , +sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__28 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1731,13 +1729,11 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_61 ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( BUF_net_61 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_122 ( .A ( BUF_net_61 ) , - .X ( out[0] ) ) ; + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__1__mux_tree_tapbuf_size10 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; input [0:3] sram_inv ; @@ -1802,7 +1798,7 @@ module sb_2__1_ ( prog_clk , chany_top_in , top_left_grid_pin_42_ , left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ , left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ , left_bottom_grid_pin_41_ , ccff_head , chany_top_out , chany_bottom_out , - chanx_left_out , ccff_tail ) ; + chanx_left_out , ccff_tail , Test_en__FEEDTHRU_0 , Test_en__FEEDTHRU_1 ) ; input [0:0] prog_clk ; input [0:19] chany_top_in ; input [0:0] top_left_grid_pin_42_ ; @@ -1838,6 +1834,8 @@ output [0:19] chany_top_out ; output [0:19] chany_bottom_out ; output [0:19] chanx_left_out ; output [0:0] ccff_tail ; +input [0:0] Test_en__FEEDTHRU_0 ; +output [0:0] Test_en__FEEDTHRU_1 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; wire [0:3] mux_tree_tapbuf_size10_0_sram_inv ; @@ -1939,71 +1937,75 @@ wire [0:3] mux_tree_tapbuf_size9_0_sram_inv ; wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ; // -mux_tree_tapbuf_size10 mux_top_track_0 ( +sb_2__1__mux_tree_tapbuf_size10 mux_top_track_0 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[2] , chany_bottom_in[12] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( mux_tree_tapbuf_size10_0_sram_inv ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( + .out ( chany_top_out[0] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_0 mux_bottom_track_1 ( .in ( { chany_top_in[2] , chany_top_in[12] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( mux_tree_tapbuf_size10_1_sram_inv ) , - .out ( { ropt_net_166 } ) , - .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , + .out ( { ropt_net_163 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size10_mem mem_top_track_0 ( .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_0_sram ) , .mem_outb ( mux_tree_tapbuf_size10_0_sram_inv ) ) ; -mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size10_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_1_sram ) , .mem_outb ( mux_tree_tapbuf_size10_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_1 mux_top_track_2 ( +sb_2__1__mux_tree_tapbuf_size8_1 mux_top_track_2 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[4] , chany_bottom_in[13] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( mux_tree_tapbuf_size8_0_sram_inv ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8 mux_top_track_8 ( + .out ( chany_top_out[1] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size8 mux_top_track_8 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_46_[0] , top_right_grid_pin_1_[0] , chany_bottom_in[6] , chany_bottom_in[16] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( mux_tree_tapbuf_size8_1_sram_inv ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( + .out ( chany_top_out[4] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_0 mux_bottom_track_9 ( .in ( { chany_top_in[6] , chany_top_in[16] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_left_in[11] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size8_2_sram ) , - .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size8_2_sram_inv ) , + .out ( { ropt_net_166 } ) , + .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size8_mem_1 mem_top_track_2 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_0_sram ) , .mem_outb ( mux_tree_tapbuf_size8_0_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem mem_top_track_8 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_1_sram ) , .mem_outb ( mux_tree_tapbuf_size8_1_sram_inv ) ) ; -mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size8_mem_0 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size8_2_sram ) , .mem_outb ( mux_tree_tapbuf_size8_2_sram_inv ) ) ; -mux_tree_tapbuf_size14 mux_top_track_4 ( +sb_2__1__mux_tree_tapbuf_size14 mux_top_track_4 ( .in ( { top_left_grid_pin_42_[0] , top_left_grid_pin_43_[0] , top_left_grid_pin_44_[0] , top_left_grid_pin_45_[0] , top_left_grid_pin_46_[0] , top_left_grid_pin_47_[0] , @@ -2012,8 +2014,8 @@ mux_tree_tapbuf_size14 mux_top_track_4 ( chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size14_0_sram ) , .sram_inv ( mux_tree_tapbuf_size14_0_sram_inv ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( + .out ( chany_top_out[2] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( .in ( { chany_top_in[5] , chany_top_in[14] , bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_45_[0] , @@ -2022,425 +2024,512 @@ mux_tree_tapbuf_size14_0 mux_bottom_track_5 ( chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size14_1_sram ) , .sram_inv ( mux_tree_tapbuf_size14_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size14_mem mem_top_track_4 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_0_sram ) , .mem_outb ( mux_tree_tapbuf_size14_0_sram_inv ) ) ; -mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size14_mem_0 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size14_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size14_1_sram ) , .mem_outb ( mux_tree_tapbuf_size14_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_5 mux_top_track_16 ( +sb_2__1__mux_tree_tapbuf_size7_5 mux_top_track_16 ( .in ( { top_left_grid_pin_43_[0] , top_left_grid_pin_47_[0] , chany_bottom_in[8] , chany_bottom_in[17] , chanx_left_in[3] , chanx_left_in[10] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( mux_tree_tapbuf_size7_0_sram_inv ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7 mux_top_track_24 ( + .out ( chany_top_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7 mux_top_track_24 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_48_[0] , chany_bottom_in[9] , chany_bottom_in[18] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( mux_tree_tapbuf_size7_1_sram_inv ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( + .out ( chany_top_out[12] ) , .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_0 mux_bottom_track_17 ( .in ( { chany_top_in[8] , chany_top_in[17] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_46_[0] , chanx_left_in[5] , chanx_left_in[12] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( mux_tree_tapbuf_size7_2_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_1 mux_left_track_1 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_1 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[2] , chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size7_2 mux_left_track_3 ( + .sram_inv ( mux_tree_tapbuf_size7_3_sram_inv ) , + .out ( { ropt_net_173 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_2 mux_left_track_3 ( .in ( { chany_top_in[4] , chany_bottom_in[0] , chany_bottom_in[4] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( mux_tree_tapbuf_size7_4_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_3 mux_left_track_5 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_3 mux_left_track_5 ( .in ( { chany_top_in[5] , chany_bottom_in[1] , chany_bottom_in[5] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( mux_tree_tapbuf_size7_5_sram_inv ) , - .out ( { ropt_net_158 } ) , - .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_4 mux_left_track_7 ( + .out ( { ropt_net_161 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_4 mux_left_track_7 ( .in ( { chany_top_in[6] , chany_bottom_in[3] , chany_bottom_in[6] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size7_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size7_6_sram_inv ) , + .out ( { ropt_net_164 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size7_mem_5 mem_top_track_16 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_0_sram ) , .mem_outb ( mux_tree_tapbuf_size7_0_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem mem_top_track_24 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_1_sram ) , .mem_outb ( mux_tree_tapbuf_size7_1_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_0 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_2_sram ) , .mem_outb ( mux_tree_tapbuf_size7_2_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_1 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_3_sram ) , .mem_outb ( mux_tree_tapbuf_size7_3_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_4_sram ) , .mem_outb ( mux_tree_tapbuf_size7_4_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_3 mem_left_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_5_sram ) , .mem_outb ( mux_tree_tapbuf_size7_5_sram_inv ) ) ; -mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size7_mem_4 mem_left_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size7_6_sram ) , .mem_outb ( mux_tree_tapbuf_size7_6_sram_inv ) ) ; -mux_tree_tapbuf_size6 mux_top_track_32 ( +sb_2__1__mux_tree_tapbuf_size6 mux_top_track_32 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_49_[0] , chany_bottom_in[10] , chanx_left_in[1] , chanx_left_in[8] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( + .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , + .out ( { ropt_net_171 } ) , + .p0 ( optlc_net_160 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_0 mux_bottom_track_25 ( .in ( { chany_top_in[9] , chany_top_in[18] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[6] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_1 mux_bottom_track_33 ( .in ( { chany_top_in[10] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[0] , chanx_left_in[7] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_157 ) ) ; +sb_2__1__mux_tree_tapbuf_size6_mem mem_top_track_32 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size9 mux_bottom_track_3 ( +sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_3 ( .in ( { chany_top_in[4] , chany_top_in[13] , bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] , chanx_left_in[9] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( mux_tree_tapbuf_size9_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_151 ) ) ; -mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_159 ) ) ; +sb_2__1__mux_tree_tapbuf_size9_mem mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_0_sram ) , .mem_outb ( mux_tree_tapbuf_size9_0_sram_inv ) ) ; -mux_tree_tapbuf_size4 mux_left_track_9 ( +sb_2__1__mux_tree_tapbuf_size4 mux_left_track_9 ( .in ( { chany_top_in[8] , chany_bottom_in[7] , chany_bottom_in[8] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size4_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_0 mux_left_track_11 ( + .sram_inv ( mux_tree_tapbuf_size4_0_sram_inv ) , + .out ( { ropt_net_170 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_0 mux_left_track_11 ( .in ( { chany_top_in[9] , chany_bottom_in[9] , chany_bottom_in[11] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( mux_tree_tapbuf_size4_1_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_1 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_1 mux_left_track_13 ( .in ( { chany_top_in[10] , chany_bottom_in[10] , chany_bottom_in[15] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( mux_tree_tapbuf_size4_2_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_2 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_2 mux_left_track_15 ( .in ( { chany_top_in[12] , chany_bottom_in[12] , chany_bottom_in[19] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( mux_tree_tapbuf_size4_3_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size4_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_0_sram ) , .mem_outb ( mux_tree_tapbuf_size4_0_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_0 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_1_sram ) , .mem_outb ( mux_tree_tapbuf_size4_1_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_1 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_2_sram ) , .mem_outb ( mux_tree_tapbuf_size4_2_sram_inv ) ) ; -mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size4_mem_2 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_3_sram ) , .mem_outb ( mux_tree_tapbuf_size4_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_left_track_17 ( +sb_2__1__mux_tree_tapbuf_size3_0 mux_left_track_17 ( .in ( { chany_top_in[13] , chany_bottom_in[13] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_19 ( + .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , + .out ( { ropt_net_169 } ) , + .p0 ( optlc_net_158 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_1 mux_left_track_19 ( .in ( { chany_top_in[14] , chany_bottom_in[14] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; -mux_tree_tapbuf_size3_2 mux_left_track_21 ( + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_2 mux_left_track_21 ( .in ( { chany_top_in[16] , chany_bottom_in[16] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_3 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_3 mux_left_track_23 ( .in ( { chany_top_in[17] , chany_bottom_in[17] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( mux_tree_tapbuf_size3_3_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_25 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3 mux_left_track_25 ( .in ( { chany_top_in[18] , chany_bottom_in[18] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , - .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , - .out ( { ropt_net_155 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( .prog_clk ( prog_clk ) , + .sram_inv ( mux_tree_tapbuf_size3_4_sram_inv ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size3_mem_0 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_1 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_2 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem_3 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_3_sram ) , .mem_outb ( mux_tree_tapbuf_size3_3_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size3_mem mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_4_sram ) , .mem_outb ( mux_tree_tapbuf_size3_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_0 mux_left_track_29 ( +sb_2__1__mux_tree_tapbuf_size2_0 mux_left_track_29 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( { ropt_net_156 } ) , - .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_1 mux_left_track_31 ( + .out ( { ropt_net_168 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_1 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_2 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_2 mux_left_track_33 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_3 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_3 mux_left_track_35 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2_4 mux_left_track_37 ( + .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , + .out ( { ropt_net_162 } ) , + .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_4 mux_left_track_37 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_149 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_150 ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_156 ) ) ; +sb_2__1__mux_tree_tapbuf_size2_mem_0 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_1 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_2 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_3 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem_4 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__1__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , - .ccff_tail ( { ropt_net_154 } ) , + .ccff_tail ( { ropt_net_180 } ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -sky130_fd_sc_hd__conb_1 optlc_134 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_2__1 ( .A ( chany_top_in[4] ) , - .X ( chany_bottom_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_3__2 ( .A ( chany_top_in[5] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_1__0 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[3] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chany_top_in[4] ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_3__2 ( .A ( chany_top_in[5] ) , + .X ( ropt_net_191 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_4__3 ( .A ( chany_top_in[6] ) , - .X ( chany_bottom_out[7] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_136 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_150 ) ) ; + .X ( ropt_net_220 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chany_top_in[8] ) , + .X ( ropt_net_189 ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_6__5 ( .A ( chany_top_in[9] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__dlymetal6s2s_1 FTB_7__6 ( .A ( chany_top_in[10] ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_138 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_9__8 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_10__9 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_742 ( - .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_743 ( .A ( ropt_net_154 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_744 ( .A ( ropt_net_155 ) , + .X ( ropt_net_182 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_157 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_158 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_11__10 ( .A ( chany_top_in[16] ) , .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , - .X ( ropt_net_175 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_745 ( .A ( ropt_net_156 ) , - .X ( chanx_left_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_19__18 ( .A ( chany_bottom_in[9] ) , - .X ( ropt_net_163 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_774 ( .A ( ropt_net_171 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_12__11 ( .A ( chany_top_in[17] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_746 ( - .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_747 ( .A ( ropt_net_158 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_748 ( .A ( chany_top_in[18] ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_775 ( .A ( ropt_net_172 ) , - .X ( chany_top_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_749 ( .A ( chany_top_in[12] ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_750 ( .A ( ropt_net_161 ) , - .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_78 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_161 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_751 ( .A ( ropt_net_162 ) , - .X ( ropt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_80 ( .A ( chany_top_in[16] ) , - .X ( BUF_net_80 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_81 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_169 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_776 ( .A ( ropt_net_173 ) , - .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_83 ( .A ( chany_bottom_in[4] ) , - .X ( chany_top_out[5] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_84 ( .A ( chany_bottom_in[8] ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_757 ( .A ( ropt_net_161 ) , + .X ( ropt_net_204 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_14__13 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_177 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_16__15 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_17__16 ( .A ( chany_bottom_in[6] ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , + .HI ( optlc_net_160 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_758 ( .A ( ropt_net_162 ) , + .X ( ropt_net_205 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_163 ) , + .X ( ropt_net_215 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_21__20 ( .A ( chany_bottom_in[12] ) , + .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_22__21 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_187 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 FTB_23__22 ( .A ( chany_bottom_in[14] ) , .X ( ropt_net_176 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_778 ( .A ( ropt_net_174 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_86 ( .A ( chany_bottom_in[13] ) , - .X ( ropt_net_165 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_175 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 FTB_24__23 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_760 ( .A ( ropt_net_164 ) , + .X ( ropt_net_218 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_761 ( + .A ( chany_bottom_in[10] ) , .X ( chany_top_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_762 ( .A ( ropt_net_166 ) , + .X ( chany_bottom_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_763 ( + .A ( chany_bottom_in[17] ) , .X ( chany_top_out[18] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_764 ( .A ( ropt_net_168 ) , + .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_798 ( .A ( ropt_net_199 ) , + .X ( chany_top_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_799 ( .A ( ropt_net_200 ) , .X ( chany_top_out[7] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_88 ( .A ( chany_bottom_in[16] ) , - .X ( ropt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_89 ( - .A ( left_bottom_grid_pin_35_[0] ) , .X ( BUF_net_89 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_752 ( .A ( ropt_net_163 ) , - .X ( chany_top_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_753 ( - .A ( chany_bottom_in[14] ) , .X ( ropt_net_173 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_755 ( .A ( ropt_net_165 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_756 ( .A ( ropt_net_166 ) , - .X ( chany_bottom_out[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_759 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[6] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_760 ( .A ( ropt_net_168 ) , - .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_169 ) , - .X ( ropt_net_171 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_170 ) , - .X ( ropt_net_174 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_109 ( .A ( chany_top_in[8] ) , - .X ( ropt_net_168 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_110 ( .A ( chany_bottom_in[18] ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_176 ) , - .X ( chany_top_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_177 ) , - .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_178 ) , - .X ( chanx_left_out[12] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_179 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_128 ( .A ( BUF_net_80 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_765 ( .A ( ropt_net_169 ) , + .X ( chanx_left_out[8] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_766 ( .A ( ropt_net_170 ) , + .X ( ropt_net_206 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_767 ( .A ( ropt_net_171 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_801 ( .A ( ropt_net_201 ) , + .X ( chanx_left_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_802 ( .A ( ropt_net_202 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_RR_89 ( .A ( Test_en__FEEDTHRU_0[0] ) , + .X ( Test_en__FEEDTHRU_1[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_768 ( .A ( chany_top_in[13] ) , + .X ( ropt_net_222 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_769 ( .A ( ropt_net_173 ) , + .X ( ropt_net_219 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_770 ( + .A ( left_bottom_grid_pin_35_[0] ) , .X ( ropt_net_221 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_771 ( .A ( chany_top_in[18] ) , + .X ( ropt_net_203 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_772 ( .A ( ropt_net_176 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_773 ( .A ( ropt_net_177 ) , + .X ( chany_top_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_117 ( .A ( chany_top_in[14] ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_118 ( .A ( chany_bottom_in[4] ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_119 ( .A ( chany_bottom_in[8] ) , + .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_120 ( .A ( chany_bottom_in[18] ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_774 ( .A ( ropt_net_178 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_181 ) , - .X ( chany_bottom_out[14] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_131 ( .A ( BUF_net_89 ) , +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_775 ( .A ( ropt_net_179 ) , + .X ( chany_top_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_138 ( .A ( chany_top_in[12] ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_805 ( .A ( ropt_net_203 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 BUFT_P_140 ( .A ( chany_bottom_in[9] ) , + .X ( ropt_net_184 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_806 ( .A ( ropt_net_204 ) , + .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_776 ( .A ( ropt_net_180 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_777 ( .A ( ropt_net_181 ) , + .X ( ropt_net_213 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_778 ( .A ( ropt_net_182 ) , + .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_779 ( .A ( ropt_net_183 ) , + .X ( ropt_net_209 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_780 ( .A ( ropt_net_184 ) , + .X ( ropt_net_214 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_781 ( .A ( ropt_net_185 ) , + .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_782 ( .A ( ropt_net_186 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_783 ( .A ( ropt_net_187 ) , + .X ( ropt_net_212 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_785 ( .A ( ropt_net_188 ) , + .X ( ropt_net_216 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_786 ( .A ( ropt_net_189 ) , + .X ( ropt_net_211 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_787 ( .A ( ropt_net_190 ) , + .X ( ropt_net_217 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_788 ( .A ( ropt_net_191 ) , + .X ( ropt_net_208 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_791 ( .A ( ropt_net_192 ) , + .X ( ropt_net_202 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_793 ( .A ( ropt_net_193 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_795 ( .A ( ropt_net_194 ) , + .X ( ropt_net_210 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_810 ( .A ( ropt_net_205 ) , + .X ( chanx_left_out[17] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_812 ( .A ( ropt_net_206 ) , + .X ( chanx_left_out[4] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_813 ( .A ( ropt_net_207 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_814 ( .A ( ropt_net_208 ) , + .X ( chany_bottom_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_816 ( .A ( ropt_net_209 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_817 ( .A ( ropt_net_210 ) , + .X ( chany_top_out[6] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_819 ( .A ( ropt_net_211 ) , + .X ( chany_bottom_out[9] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_820 ( .A ( ropt_net_212 ) , + .X ( chany_top_out[14] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_823 ( .A ( ropt_net_213 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_824 ( .A ( ropt_net_214 ) , + .X ( chany_top_out[10] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_825 ( .A ( ropt_net_215 ) , + .X ( chany_bottom_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_826 ( .A ( ropt_net_216 ) , + .X ( chany_top_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_827 ( .A ( ropt_net_217 ) , + .X ( chany_bottom_out[5] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_828 ( .A ( ropt_net_218 ) , + .X ( chanx_left_out[3] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_829 ( .A ( ropt_net_219 ) , + .X ( chanx_left_out[0] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_830 ( .A ( ropt_net_220 ) , + .X ( chany_bottom_out[7] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_831 ( .A ( ropt_net_221 ) , .X ( chanx_left_out[13] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_832 ( .A ( ropt_net_222 ) , + .X ( chany_bottom_out[14] ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v index 3271d55..6ac85c9 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.fm.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21,7 +21,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -38,8 +38,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -55,12 +55,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module const1 ( const1 ) ; +module sb_2__2__const1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -71,7 +71,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1 const1_0_ ( +sb_2__2__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -86,12 +86,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_33 ( const1 ) ; +module sb_2__2__const1_33 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -102,7 +102,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_33 const1_0_ ( +sb_2__2__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -117,12 +117,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module const1_32 ( const1 ) ; +module sb_2__2__const1_32 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -133,7 +133,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -const1_32 const1_0_ ( +sb_2__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; @@ -148,7 +148,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -161,14 +161,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -184,8 +182,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -201,8 +199,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -218,8 +216,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -235,8 +233,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -252,8 +250,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -269,8 +267,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -286,8 +284,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -303,8 +301,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -320,8 +318,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -337,8 +335,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -354,8 +352,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -371,8 +369,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -388,8 +386,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -405,8 +403,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -422,8 +420,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -439,8 +437,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -456,8 +454,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -473,8 +471,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -490,8 +488,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -507,8 +505,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -524,8 +522,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -541,8 +539,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -558,12 +556,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module const1_31 ( const1 ) ; +module sb_2__2__const1_31 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -573,7 +571,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_31 const1_0_ ( +sb_2__2__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -585,12 +583,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_30 ( const1 ) ; +module sb_2__2__const1_30 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -600,7 +598,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_30 const1_0_ ( +sb_2__2__const1_30 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -612,12 +610,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_29 ( const1 ) ; +module sb_2__2__const1_29 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -627,7 +625,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_29 const1_0_ ( +sb_2__2__const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -639,12 +637,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_28 ( const1 ) ; +module sb_2__2__const1_28 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -654,7 +652,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_28 const1_0_ ( +sb_2__2__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -666,12 +664,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_27 ( const1 ) ; +module sb_2__2__const1_27 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -681,7 +679,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_27 const1_0_ ( +sb_2__2__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -693,12 +691,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_26 ( const1 ) ; +module sb_2__2__const1_26 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -708,7 +706,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_26 const1_0_ ( +sb_2__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -720,12 +718,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_25 ( const1 ) ; +module sb_2__2__const1_25 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -735,7 +733,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_25 const1_0_ ( +sb_2__2__const1_25 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -747,12 +745,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_24 ( const1 ) ; +module sb_2__2__const1_24 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -762,7 +760,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_24 const1_0_ ( +sb_2__2__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -774,12 +772,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_23 ( const1 ) ; +module sb_2__2__const1_23 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -789,7 +787,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_23 const1_0_ ( +sb_2__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -801,12 +799,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_22 ( const1 ) ; +module sb_2__2__const1_22 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -816,34 +814,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_22 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_21 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_21 const1_0_ ( +sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -855,12 +826,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_20 ( const1 ) ; +module sb_2__2__const1_21 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -870,7 +841,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_20 const1_0_ ( +sb_2__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -882,12 +853,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_19 ( const1 ) ; +module sb_2__2__const1_20 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -897,7 +868,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_19 const1_0_ ( +sb_2__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -909,12 +880,201 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_18 ( const1 ) ; +module sb_2__2__const1_19 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_19 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_18 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_18 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_17 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_17 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_16 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_16 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_15 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_15 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_14 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_14 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_13 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_13 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -923,7 +1083,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_18 const1_0_ ( +sb_2__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -932,12 +1092,12 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_17 ( const1 ) ; +module sb_2__2__const1_11 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -947,7 +1107,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -const1_17 const1_0_ ( +sb_2__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; @@ -959,12 +1119,66 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_16 ( const1 ) ; +module sb_2__2__const1_10 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_10 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sb_2__2__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__const1_8 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -973,7 +1187,7 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -const1_16 const1_0_ ( +sb_2__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -982,219 +1196,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module const1_15 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_15 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_14 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -const1_14 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module const1_13 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_13 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_11 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_11 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_10 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_10 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module const1_8 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -const1_8 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1213,8 +1215,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1232,8 +1234,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1251,8 +1253,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1270,12 +1272,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module const1_7 ( const1 ) ; +module sb_2__2__const1_7 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1288,7 +1290,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_7 const1_0_ ( +sb_2__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1309,12 +1311,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_6 ( const1 ) ; +module sb_2__2__const1_6 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1327,7 +1329,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_6 const1_0_ ( +sb_2__2__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1348,12 +1350,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_5 ( const1 ) ; +module sb_2__2__const1_5 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1366,7 +1368,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_5 const1_0_ ( +sb_2__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; @@ -1387,12 +1389,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_4 ( const1 ) ; +module sb_2__2__const1_4 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1405,10 +1407,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -const1_4 const1_0_ ( +sb_2__2__const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1423,10 +1423,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1445,8 +1449,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1464,8 +1468,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1483,8 +1487,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1502,12 +1506,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module const1_3 ( const1 ) ; +module sb_2__2__const1_3 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1521,7 +1525,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_3 const1_0_ ( +sb_2__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1545,12 +1549,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_2 ( const1 ) ; +module sb_2__2__const1_2 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1564,7 +1568,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_2 const1_0_ ( +sb_2__2__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1588,12 +1592,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_1 ( const1 ) ; +module sb_2__2__const1_1 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1607,7 +1611,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_1 const1_0_ ( +sb_2__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; @@ -1631,12 +1635,12 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module const1_0 ( const1 ) ; +module sb_2__2__const1_0 ( const1 ) ; output [0:0] const1 ; endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1648,12 +1652,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -const1_0 const1_0_ ( +sb_2__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1667,10 +1668,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1823,429 +1823,447 @@ wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6 mux_left_track_5 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5 mux_left_track_7 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v index e427a0f..2184480 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.lvs.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -28,7 +28,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -52,8 +52,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -76,7 +76,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -107,7 +108,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -138,7 +140,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -169,7 +172,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -189,14 +192,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -219,8 +220,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -243,8 +244,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -267,8 +268,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -291,8 +292,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -315,8 +316,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -339,8 +340,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -363,8 +364,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -387,8 +388,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -411,8 +412,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -435,8 +436,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -459,8 +460,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -483,8 +484,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -507,8 +508,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -531,8 +532,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -555,8 +556,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -579,8 +580,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -603,8 +604,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -627,8 +628,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -651,8 +652,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -675,8 +676,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -699,8 +700,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -723,8 +724,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -747,7 +748,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -773,8 +775,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -800,8 +802,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -827,8 +829,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -854,8 +856,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -881,8 +883,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -908,8 +910,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -935,8 +937,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -962,8 +964,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -989,35 +991,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1043,8 +1018,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1070,8 +1045,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1097,8 +1072,197 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1120,7 +1284,8 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1146,7 +1311,62 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -1168,211 +1388,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1399,8 +1415,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1426,8 +1442,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1453,8 +1469,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1480,7 +1496,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1520,7 +1537,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1560,7 +1578,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1600,7 +1619,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1617,9 +1637,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1637,10 +1654,15 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1667,8 +1689,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1694,8 +1716,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1721,8 +1743,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb , VDD , VSS ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb , VDD , VSS ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1748,7 +1770,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1792,7 +1815,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1836,7 +1860,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1880,7 +1905,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1894,13 +1920,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -1917,10 +1939,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2077,1480 +2099,1795 @@ supply0 VSS ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6 mux_left_track_5 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5 mux_left_track_7 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_9 ( + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1403 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1430 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1404 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1431 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1405 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1432 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1406 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1433 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1407 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1434 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1408 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1435 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1409 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1436 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1410 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1437 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1411 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1438 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1412 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1439 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1413 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1440 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1414 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1441 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1415 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1442 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1416 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1443 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1417 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1444 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1418 ( .VNB ( VSS ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1445 ( .VNB ( VSS ) , .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1446 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1447 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1448 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1449 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1450 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1451 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1452 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1453 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1454 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1455 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1456 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1457 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1458 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1459 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1460 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1461 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1462 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1463 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1464 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__tap_2 tapfiller_sky130_fd_sc_hd__tap_2_1465 ( .VNB ( VSS ) , + .VPB ( VDD ) , .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y0 ( +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y0 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y0 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y0 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y0 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y0 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y0 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y0 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y27200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x220800y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y27200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x404800y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x538200y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y27200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y27200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x312800y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x575000y54400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x749800y27200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x754400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y54400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x276000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x377200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y27200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x570400y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x239200y54400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x271400y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y81600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y81600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y81600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x782000y54400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y54400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y81600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y81600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y81600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x257600y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x276000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y108800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x368000y108800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x386400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x630200y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x648600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y108800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x713000y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y108800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y108800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y136000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x680800y108800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x381800y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x818800y108800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x855600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x892400y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x929200y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y108800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x78200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x96600y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x142600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x483000y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x193200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y136000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x243800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x726800y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x556600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x575000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y136000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y136000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y136000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y163200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y163200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y136000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y136000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y136000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x690000y163200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x188600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x234600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x386400y163200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x432400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y163200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x450800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y163200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x547400y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y190400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x565800y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y163200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x731400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x841800y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y163200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y163200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x142600y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x207000y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x335800y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x400200y190400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x634800y190400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x671600y190400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x708400y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y190400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y190400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y190400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y190400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y190400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x276000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x36800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x349600y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x197800y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x358800y217600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x216200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x621000y217600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x630200y217600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x759000y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x768200y217600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x570400y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x667000y217600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y217600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y217600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y217600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y217600 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x234600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x253000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x368000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x414000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x450800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x487600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x662400y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x671600y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y244800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y244800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y244800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x202400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y244800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x289800y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y244800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y244800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x27600y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x105800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x151800y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x170200y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x625600y272000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y272000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y272000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x772800y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x299000y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y272000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x469200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y272000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y272000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x547400y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y272000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y272000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y272000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y299200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x331200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x377200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y299200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x427800y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x483000y299200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x717600y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y299200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x726800y299200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y299200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y299200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x818800y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y299200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y326400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y326400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x179400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x197800y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x469200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x506000y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x653200y326400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x662400y326400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y326400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x708400y326400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x372600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x427800y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x639400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y326400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y326400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y326400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x110400y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x87400y353600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x220800y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x105800y353600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x239200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x115000y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x372600y353600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x644000y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x607200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x625600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y353600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y353600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y380800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x795800y353600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x87400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x837200y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x138000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y353600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x147200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y353600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x92000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y380800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x230000y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x326600y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x326600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x400200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x409400y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x460000y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x639400y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x519800y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x657800y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x538200y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x699200y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y380800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y380800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x782000y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x878600y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y380800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y380800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y380800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y380800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x64400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x119600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x239200y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x276000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x294400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x345000y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x363400y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x414000y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x161000y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x170200y408000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y408000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x565800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x579600y408000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y408000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x584200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x699200y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x717600y408000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x736000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x745200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y408000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x73600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y408000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y408000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y408000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x133400y435200 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x230000y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x92000y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x202400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x441600y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x211600y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x492200y435200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x552000y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x561200y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x588800y435200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x598000y435200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y435200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y435200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x915400y435200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y435200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x73600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x82800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x115000y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y462400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x216200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x234600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x303600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x312800y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x243800y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x358800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x395600y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y462400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x492200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x483000y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y462400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x533600y462400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x703800y462400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x763600y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y462400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x230000y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x285200y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x740600y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x331200y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y462400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y462400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y462400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x529000y489600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x584200y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y489600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y489600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y489600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x708400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x418600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x437000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x611800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x630200y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x726800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y489600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x119600y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x138000y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x800400y489600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x837200y489600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x36800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x46000y516800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x335800y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x552000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x570400y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x616400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x243800y516800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x634800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x340400y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x358800y516800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x446200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x473800y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y516800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x616400y516800 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y516800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y516800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y516800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y516800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y544000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x82800y544000 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x101200y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x151800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x193200y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x248400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x285200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x322000y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x501400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x519800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x565800y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x363400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x653200y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y544000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y544000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x768200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y544000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y544000 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y544000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x648600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x667000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x676200y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x694600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x703800y544000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x874000y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x910800y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x947600y544000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x165600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x174800y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x87400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x124200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x524400y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x542800y571200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y571200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x598000y571200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x354200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x515200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x524400y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x616400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x653200y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y571200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x690000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x726800y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x763600y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x55200y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y571200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x73600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y571200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y571200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x165600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x55200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x92000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x128800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x349600y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x386400y598400 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y598400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x395600y598400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x441600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x657800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x814200y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x851000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x887800y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x924600y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y598400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y598400 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x561200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x579600y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x588800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x634800y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x680800y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x699200y598400 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y598400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x36800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x202400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x262200y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x55200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x317400y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x335800y625600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x87400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x446200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x174800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x455400y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x211600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x248400y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x501400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x340400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x552000y625600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x349600y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x598000y625600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x634800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x694600y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x533600y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x768200y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x805000y625600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x621000y625600 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y625600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x657800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y625600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y625600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y625600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x55200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x59800y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x92000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x96600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x193200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x280600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x179400y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x299000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x188600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x234600y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x418600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x455400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x492200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x602600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x639400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x648600y652800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x280600y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x694600y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x299000y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x713000y652800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x308200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y652800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x101200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x110400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x354200y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x151800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x414000y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x188600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x464600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x207000y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x561200y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x685400y652800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x694600y652800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x216200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y652800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x308200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x823400y652800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y652800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x391000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x533600y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x667000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x685400y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x731400y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x101200y680000 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x768200y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x138000y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x156400y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y680000 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x165600y680000 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y680000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y680000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x345000y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x556600y680000 ( - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x685400y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x791200y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x828000y680000 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x230000y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x128800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x266800y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x303600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x322000y707200 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y707200 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x317400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x409400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x427800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y707200 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y707200 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x326600y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x184000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x239200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x257600y734400 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x423200y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x529000y734400 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x469200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x565800y734400 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x487600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x602600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y734400 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x142600y761600 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x161000y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x496800y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x253000y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x625600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x271400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x644000y707200 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x312800y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x690000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x349600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x368000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y761600 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y707200 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y761600 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y707200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x0y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x18400y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y761600 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x82800y734400 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y761600 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x331200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x460000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x510600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x547400y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x593400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x611800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x708400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x745200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y734400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y734400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x184000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x262200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x280600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x289800y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x414000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x506000y761600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x547400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x584200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x621000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x676200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x713000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x749800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x786600y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x823400y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x860200y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x897000y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x933800y761600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y761600 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; @@ -3564,47 +3901,379 @@ sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x404800y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x423200y788800 ( - .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x432400y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x220800y788800 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x446200y788800 ( +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x312800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x483000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x372600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x519800y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x409400y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x556600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x593400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x630200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x667000y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x703800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x740600y788800 ( +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x777400y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x814200y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x832600y788800 ( +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y788800 ( .VGND ( VSS ) , .VPWR ( VDD ) ) ; -sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x841800y788800 ( +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y788800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y788800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x317400y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x409400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x418600y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x598000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x607200y816000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x772800y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x809600y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x846400y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x883200y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x920000y816000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x147200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x156400y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x188600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x225400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x262200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x299000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x335800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x372600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x381800y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x423200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x460000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x496800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x533600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x570400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x607200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x644000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x680800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x717600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x754400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y843200 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y843200 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y870400 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y870400 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x257600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x294400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x331200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x368000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x404800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x441600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x478400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x515200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x552000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x588800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x625600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x662400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x699200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x736000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x772800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x782000y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y897600 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y897600 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x759000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y924800 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y924800 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x0y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x36800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x73600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x110400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x147200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x184000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x220800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x257600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x266800y952000 ( + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x280600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x317400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x354200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x391000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x427800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x464600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x501400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x538200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x575000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x611800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x648600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x685400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x722200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_4 xofiller_sky130_fd_sc_hd__fill_4_x759000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x777400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x795800y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x832600y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x869400y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_8 xofiller_sky130_fd_sc_hd__fill_8_x906200y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_2 xofiller_sky130_fd_sc_hd__fill_2_x943000y952000 ( + .VGND ( VSS ) , .VPWR ( VDD ) ) ; +sky130_fd_sc_hd__fill_1 xofiller_sky130_fd_sc_hd__fill_1_x952200y952000 ( .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v index 7aac881..d20f294 100644 --- a/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v +++ b/FPGA22_HIER_SKY_PNR/modules/verilog/sb_2__2__icv_in_design.pt.v @@ -4,8 +4,8 @@ // // // -module mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -21,7 +21,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_35__40 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size3_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -38,8 +38,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_34__39 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size3_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -55,7 +55,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_33__38 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -79,7 +79,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -103,7 +103,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -127,7 +127,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( endmodule -module mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size2_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -140,14 +140,12 @@ sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfxbp_1 sky130_fd_sc_hd__dfxbp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .Q ( mem_out[1] ) , .Q_N ( mem_outb[1] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 FTB_32__37 ( .A ( mem_out[1] ) , - .X ( net_net_48 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 BUFT_RR_48 ( .A ( net_net_48 ) , .X ( ccff_tail[0] ) ) ; endmodule -module mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_22 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -163,8 +161,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_31__36 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_21 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -180,8 +178,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_30__35 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_20 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -197,8 +195,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_29__34 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_19 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -214,8 +212,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_28__33 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_18 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -231,8 +229,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_27__32 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_17 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -248,8 +246,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_26__31 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_16 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -265,8 +263,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_25__30 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_15 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -282,8 +280,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_24__29 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_14 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -299,8 +297,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_23__28 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_13 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -316,8 +314,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_22__27 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_12 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -333,8 +331,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_21__26 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_11 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -350,8 +348,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_20__25 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_10 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -367,8 +365,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_19__24 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_8 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -384,8 +382,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_18__23 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_7 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -401,8 +399,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_17__22 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_6 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -418,8 +416,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_16__21 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_5 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -435,8 +433,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_15__20 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_4 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -452,8 +450,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_14__19 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_3 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -469,8 +467,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_13__18 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -486,8 +484,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_12__17 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -503,8 +501,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_11__16 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -520,8 +518,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_10__15 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size2_mem_9 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -537,7 +535,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_9__14 ( .A ( mem_out[1] ) , endmodule -module mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -557,7 +555,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_22 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -577,7 +575,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_21 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -597,7 +595,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -617,7 +615,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -637,7 +635,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -657,7 +655,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -677,7 +675,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -697,7 +695,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -717,27 +715,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_44 ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_14 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -757,7 +735,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_13 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -777,7 +755,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_12 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -797,7 +775,147 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_11 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_10 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -813,7 +931,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_8 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -833,7 +951,47 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_7 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -849,163 +1007,7 @@ sky130_fd_sc_hd__mux2_8 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module mux_tree_tapbuf_size2_6 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size2_9 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -endmodule - - -module mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size5_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1024,8 +1026,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_8__13 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1043,8 +1045,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_7__12 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1062,8 +1064,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_6__11 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size5_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1081,7 +1083,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_5__10 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1113,7 +1115,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_2 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1145,7 +1147,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_1 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1177,7 +1179,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size5_0 ( in , sram , sram_inv , out , p0 ) ; input [0:4] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1190,8 +1192,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1206,10 +1206,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_42 ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( BUF_net_42 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 BUFT_P_69 ( .A ( BUF_net_42 ) , + .X ( out[0] ) ) ; endmodule -module mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , +module sb_2__2__mux_tree_tapbuf_size6_mem ( prog_clk , ccff_head , ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; @@ -1228,8 +1232,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_4__9 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_2 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1247,8 +1251,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_3__8 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_1 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1266,8 +1270,8 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_2__7 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , ccff_tail , - mem_out , mem_outb ) ; +module sb_2__2__mux_tree_tapbuf_size6_mem_0 ( prog_clk , ccff_head , + ccff_tail , mem_out , mem_outb ) ; input [0:0] prog_clk ; input [0:0] ccff_head ; output [0:0] ccff_tail ; @@ -1285,7 +1289,7 @@ sky130_fd_sc_hd__dlygate4sd3_1 FTB_1__6 ( .A ( mem_out[2] ) , endmodule -module mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1321,7 +1325,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_2 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1357,7 +1361,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1393,7 +1397,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( endmodule -module mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; input [0:2] sram_inv ; @@ -1405,10 +1409,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -1422,10 +1423,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_8 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -1578,429 +1578,447 @@ wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ; assign SC_IN_TOP = SC_IN_BOT ; -mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( +sb_2__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( mux_tree_tapbuf_size6_0_sram_inv ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_1 mux_bottom_track_5 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_43_[0] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( mux_tree_tapbuf_size6_1_sram_inv ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_2 mux_left_track_1 ( + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_2 mux_left_track_1 ( .in ( { chany_bottom_in[19] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( mux_tree_tapbuf_size6_2_sram_inv ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6 mux_left_track_5 ( + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_35_[0] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( mux_tree_tapbuf_size6_3_sram_inv ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .prog_clk ( prog_clk ) , - .ccff_head ( ccff_head ) , + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_0_sram ) , .mem_outb ( mux_tree_tapbuf_size6_0_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_5 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_1_sram ) , .mem_outb ( mux_tree_tapbuf_size6_1_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem_2 mem_left_track_1 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_2_sram ) , .mem_outb ( mux_tree_tapbuf_size6_2_sram_inv ) ) ; -mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size6_mem mem_left_track_5 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_3_sram ) , .mem_outb ( mux_tree_tapbuf_size6_3_sram_inv ) ) ; -mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( +sb_2__2__mux_tree_tapbuf_size5_0 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size5_0_sram ) , - .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( + .sram_inv ( mux_tree_tapbuf_size5_0_sram_inv ) , + .out ( { ropt_net_87 } ) , + .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_1 mux_bottom_track_7 ( .in ( { bottom_left_grid_pin_42_[0] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( mux_tree_tapbuf_size5_1_sram_inv ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size5_2 mux_left_track_3 ( + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_2 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( mux_tree_tapbuf_size5_2_sram_inv ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5 mux_left_track_7 ( + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_bottom_grid_pin_34_[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( mux_tree_tapbuf_size5_3_sram_inv ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size5_mem_0 mem_bottom_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_0_sram ) , .mem_outb ( mux_tree_tapbuf_size5_0_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_1 mem_bottom_track_7 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_1_sram ) , .mem_outb ( mux_tree_tapbuf_size5_1_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem_2 mem_left_track_3 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_2_sram ) , .mem_outb ( mux_tree_tapbuf_size5_2_sram_inv ) ) ; -mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size5_mem mem_left_track_7 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_3_sram ) , .mem_outb ( mux_tree_tapbuf_size5_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( +sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_9 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( mux_tree_tapbuf_size2_0_sram_inv ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( mux_tree_tapbuf_size2_1_sram_inv ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_13 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( mux_tree_tapbuf_size2_2_sram_inv ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( mux_tree_tapbuf_size2_3_sram_inv ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( mux_tree_tapbuf_size2_4_sram_inv ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( mux_tree_tapbuf_size2_5_sram_inv ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , - .out ( { ropt_net_83 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( + .sram_inv ( mux_tree_tapbuf_size2_6_sram_inv ) , + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( mux_tree_tapbuf_size2_7_sram_inv ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_42_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( mux_tree_tapbuf_size2_8_sram_inv ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_29 ( .in ( { bottom_left_grid_pin_43_[0] , chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( mux_tree_tapbuf_size2_9_sram_inv ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_10 mux_left_track_11 ( + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_81 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_10 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( mux_tree_tapbuf_size2_10_sram_inv ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_11 mux_left_track_13 ( + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_11 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( mux_tree_tapbuf_size2_11_sram_inv ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_12 mux_left_track_15 ( + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_12 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( mux_tree_tapbuf_size2_12_sram_inv ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_13 mux_left_track_17 ( + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_13 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( mux_tree_tapbuf_size2_13_sram_inv ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_14 mux_left_track_19 ( + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_14 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , - .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , - .out ( { ropt_net_81 } ) , - .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_15 mux_left_track_21 ( + .sram_inv ( mux_tree_tapbuf_size2_14_sram_inv ) , + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( mux_tree_tapbuf_size2_15_sram_inv ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size2_16 mux_left_track_23 ( + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( mux_tree_tapbuf_size2_16_sram_inv ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_17 mux_left_track_27 ( + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_34_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( mux_tree_tapbuf_size2_17_sram_inv ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_18 mux_left_track_29 ( + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_bottom_grid_pin_35_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( mux_tree_tapbuf_size2_18_sram_inv ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_19 mux_left_track_31 ( + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( mux_tree_tapbuf_size2_19_sram_inv ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_20 mux_left_track_33 ( + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( mux_tree_tapbuf_size2_20_sram_inv ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_76 ) ) ; -mux_tree_tapbuf_size2_21 mux_left_track_35 ( + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( mux_tree_tapbuf_size2_21_sram_inv ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2_22 mux_left_track_37 ( + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( mux_tree_tapbuf_size2_22_sram_inv ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_74 ) ) ; -mux_tree_tapbuf_size2 mux_left_track_39 ( + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_84 ) ) ; +sb_2__2__mux_tree_tapbuf_size2 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( mux_tree_tapbuf_size2_23_sram_inv ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_77 ) ) ; -mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_9 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_0_sram ) , .mem_outb ( mux_tree_tapbuf_size2_0_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_1_sram ) , .mem_outb ( mux_tree_tapbuf_size2_1_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_2_sram ) , .mem_outb ( mux_tree_tapbuf_size2_2_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_3_sram ) , .mem_outb ( mux_tree_tapbuf_size2_3_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_4_sram ) , .mem_outb ( mux_tree_tapbuf_size2_4_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_5_sram ) , .mem_outb ( mux_tree_tapbuf_size2_5_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_6_sram ) , .mem_outb ( mux_tree_tapbuf_size2_6_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_7_sram ) , .mem_outb ( mux_tree_tapbuf_size2_7_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_8_sram ) , .mem_outb ( mux_tree_tapbuf_size2_8_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_9_sram ) , .mem_outb ( mux_tree_tapbuf_size2_9_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_10 mem_left_track_11 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) , .mem_outb ( mux_tree_tapbuf_size2_10_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_11 mem_left_track_13 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_11_sram ) , .mem_outb ( mux_tree_tapbuf_size2_11_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_12 mem_left_track_15 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_12_sram ) , .mem_outb ( mux_tree_tapbuf_size2_12_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_13 mem_left_track_17 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_13_sram ) , .mem_outb ( mux_tree_tapbuf_size2_13_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_14 mem_left_track_19 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_14_sram ) , .mem_outb ( mux_tree_tapbuf_size2_14_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_15 mem_left_track_21 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_15_sram ) , .mem_outb ( mux_tree_tapbuf_size2_15_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_16 mem_left_track_23 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_16_sram ) , .mem_outb ( mux_tree_tapbuf_size2_16_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_17 mem_left_track_27 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_17_sram ) , .mem_outb ( mux_tree_tapbuf_size2_17_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_18 mem_left_track_29 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_18_sram ) , .mem_outb ( mux_tree_tapbuf_size2_18_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_19 mem_left_track_31 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_19_sram ) , .mem_outb ( mux_tree_tapbuf_size2_19_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_20 mem_left_track_33 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_20_sram ) , .mem_outb ( mux_tree_tapbuf_size2_20_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_21 mem_left_track_35 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_21_sram ) , .mem_outb ( mux_tree_tapbuf_size2_21_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem_22 mem_left_track_37 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_22_sram ) , .mem_outb ( mux_tree_tapbuf_size2_22_sram_inv ) ) ; -mux_tree_tapbuf_size2_mem mem_left_track_39 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size2_mem mem_left_track_39 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) , - .ccff_tail ( { ropt_net_84 } ) , + .ccff_tail ( { ropt_net_92 } ) , .mem_out ( mux_tree_tapbuf_size2_23_sram ) , .mem_outb ( mux_tree_tapbuf_size2_23_sram_inv ) ) ; -mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( +sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_25 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( mux_tree_tapbuf_size3_0_sram_inv ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_75 ) ) ; -mux_tree_tapbuf_size3 mux_left_track_9 ( + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_83 ) ) ; +sb_2__2__mux_tree_tapbuf_size3 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( mux_tree_tapbuf_size3_1_sram_inv ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_1 mux_left_track_25 ( + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_1 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( mux_tree_tapbuf_size3_2_sram_inv ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_78 ) ) ; -mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( .prog_clk ( prog_clk ) , + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_82 ) ) ; +sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_0_sram ) , .mem_outb ( mux_tree_tapbuf_size3_0_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_9 ( .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .mem_outb ( mux_tree_tapbuf_size3_1_sram_inv ) ) ; -mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( .prog_clk ( prog_clk ) , +sb_2__2__mux_tree_tapbuf_size3_mem_1 mem_left_track_25 ( + .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_2_sram ) , .mem_outb ( mux_tree_tapbuf_size3_2_sram_inv ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_1__0 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_86 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_2__1 ( .A ( chanx_left_in[16] ) , - .X ( ropt_net_87 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_675 ( .A ( ropt_net_92 ) , - .X ( chanx_left_out[9] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_676 ( .A ( ropt_net_93 ) , - .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 FTB_5__4 ( .A ( chanx_left_in[19] ) , - .X ( ropt_net_88 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , - .X ( ropt_net_82 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_677 ( .A ( ropt_net_94 ) , - .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 BUFT_RR_46 ( .A ( chanx_left_in[18] ) , - .X ( BUF_net_46 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_678 ( .A ( ropt_net_95 ) , - .X ( chany_bottom_out[10] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_60 ( .A ( BUF_net_46 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_68 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , - .HI ( optlc_net_74 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_71 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_75 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_73 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , - .HI ( optlc_net_76 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_75 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , - .HI ( optlc_net_77 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_77 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , - .HI ( optlc_net_78 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_667 ( .A ( ropt_net_81 ) , - .X ( ropt_net_92 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_668 ( .A ( ropt_net_82 ) , - .X ( ropt_net_97 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_669 ( .A ( ropt_net_83 ) , - .X ( ropt_net_95 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_670 ( .A ( ropt_net_84 ) , +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_690 ( .A ( ropt_net_94 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_671 ( .A ( chanx_left_in[17] ) , - .X ( ropt_net_98 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_672 ( .A ( ropt_net_86 ) , - .X ( ropt_net_96 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_673 ( .A ( ropt_net_87 ) , - .X ( ropt_net_94 ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_674 ( .A ( ropt_net_88 ) , - .X ( ropt_net_93 ) ) ; -sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_679 ( .A ( ropt_net_96 ) , - .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_680 ( .A ( ropt_net_97 ) , +sky130_fd_sc_hd__conb_1 optlc_74 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , + .HI ( optlc_net_81 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_691 ( .A ( ropt_net_95 ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_681 ( .A ( ropt_net_98 ) , +sky130_fd_sc_hd__conb_1 optlc_76 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , + .HI ( optlc_net_82 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_692 ( .A ( ropt_net_96 ) , + .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 FTB_6__5 ( .A ( SC_OUT_TOP ) , + .X ( ropt_net_86 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_693 ( .A ( ropt_net_97 ) , .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_694 ( .A ( ropt_net_98 ) , + .X ( chany_bottom_out[19] ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_695 ( .A ( ropt_net_99 ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 BUFT_RR_50 ( .A ( chanx_left_in[19] ) , + .X ( BUF_net_50 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_78 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , + .HI ( optlc_net_83 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 BUFT_P_65 ( .A ( BUF_net_50 ) , + .X ( chany_bottom_out[18] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_80 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , + .HI ( optlc_net_84 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_683 ( .A ( ropt_net_86 ) , + .X ( ropt_net_95 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_684 ( .A ( ropt_net_87 ) , + .X ( chany_bottom_out[1] ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_685 ( .A ( chanx_left_in[17] ) , + .X ( ropt_net_97 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_686 ( .A ( chanx_left_in[0] ) , + .X ( ropt_net_98 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_687 ( .A ( chanx_left_in[18] ) , + .X ( ropt_net_99 ) ) ; +sky130_fd_sc_hd__dlymetal6s2s_1 ropt_mt_inst_688 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_96 ) ) ; +sky130_fd_sc_hd__dlymetal6s6s_1 ropt_mt_inst_689 ( .A ( ropt_net_92 ) , + .X ( ropt_net_94 ) ) ; endmodule